From: Ben Dooks <ben.dooks@codethink.co.uk>
To: Cyril.Jean@microchip.com, atishp@atishpatra.org
Cc: devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
Daire.McNamara@microchip.com, anup.patel@wdc.com,
linux-kernel@vger.kernel.org, atish.patra@wdc.com,
robh+dt@kernel.org, alistair.francis@wdc.com,
paul.walmsley@sifive.com, palmer@dabbelt.com,
linux-riscv@lists.infradead.org, Padmarao.Begari@microchip.com
Subject: Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
Date: Tue, 3 Nov 2020 18:28:11 +0000 [thread overview]
Message-ID: <fe079b4a-5410-5cc8-3f5e-8a95b573078a@codethink.co.uk> (raw)
In-Reply-To: <fbe404b5-3bb1-dd00-e558-e4a55960b767@microchip.com>
On 03/11/2020 18:10, Cyril.Jean@microchip.com wrote:
> On 11/3/20 3:07 PM, Atish Patra wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Fri, Oct 30, 2020 at 2:20 PM Ben Dooks <ben.dooks@codethink.co.uk> wrote:
,snip[
>>>> @Cyril : Can we enable both eMMC & sdcard at the same time ?
>>> I would put /both/ in but only enable the one in use for the moment.
>>> Our boards are booting of eMMC as supplied, so this isn't going to work
>>> as well. The eMMC is 8bit wide, and thus is only delivering 11MB/sec
>>> instead of 22MB/sec. This performance is still not great, but losing
>>> half the data-rate is just not good.
>>>
>> I am not sure what should be enabled by default. Updating sdcard is much
>> easier than eMMC card and we use that approach.
>>
>> @Cyril: Is there a way that we can enable both ?
>>
> Yes, we can enable both but this requires a modification to the FPGA
> design. One of the guys prototyped this while I was away. We will move
> this along. This will require reprogramming the FPGA with a new design
> and HSS version.
>
> Regards,
>
> Cyril.
I either missed or couldn't find a way of forcing the boot mode to be
from the SD slot. Have I missed something? At the moment we'd like to
have more storage available as the ~7G free on the eMMC is not enough.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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next prev parent reply other threads:[~2020-11-03 18:28 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 23:27 [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Atish Patra
2020-10-28 23:27 ` [RFC PATCH 1/3] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-10-30 9:08 ` Anup Patel
2020-11-03 9:55 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-10-29 10:24 ` Ben Dooks
2020-10-30 7:11 ` Atish Patra
2020-10-30 21:19 ` Ben Dooks
2020-11-03 15:07 ` Atish Patra
2020-11-03 15:19 ` Ben Dooks
2020-11-03 18:10 ` Cyril.Jean
2020-11-03 18:28 ` Ben Dooks [this message]
2020-11-03 18:36 ` Atish Patra
2020-11-03 18:39 ` Ben Dooks
2020-11-03 18:45 ` Atish Patra
2020-11-03 18:40 ` Cyril.Jean
2020-11-03 18:46 ` Ben Dooks
2020-11-04 2:41 ` Bin Meng
2020-10-30 9:05 ` Anup Patel
2020-10-30 20:27 ` Atish Patra
2020-11-03 10:59 ` Ben Dooks
2020-11-03 15:08 ` Atish Patra
2020-10-30 21:20 ` Ben Dooks
2020-11-03 10:00 ` Bin Meng
2020-11-03 18:19 ` Cyril.Jean
2020-11-03 18:38 ` Atish Patra
2020-11-03 18:50 ` Cyril.Jean
2020-11-03 19:02 ` Atish Patra
2020-11-06 7:14 ` Palmer Dabbelt
2020-10-28 23:27 ` [RFC PATCH 3/3] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-10-30 9:09 ` Anup Patel
2020-10-30 21:21 ` Ben Dooks
2020-11-03 10:03 ` Bin Meng
2020-11-06 7:14 ` Palmer Dabbelt
2020-11-06 7:14 ` [RFC PATCH 0/3] Add Microchip PolarFire Soc Support Palmer Dabbelt
2020-11-06 7:37 ` Atish Patra
2020-11-06 8:11 ` Palmer Dabbelt
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