Re: [PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC

From: Greentime Hu <greentime.hu@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	hes@sifive.com,  Erik Danie <erik.danie@sifive.com>,
	Zong Li <zong.li@sifive.com>,
	 Bjorn Helgaas <bhelgaas@google.com>,
	robh+dt@kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
	 Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	 Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	 alex.dewar90@gmail.com, khilman@baylibre.com,
	hayashi.kunihiko@socionext.com,  vidyas@nvidia.com,
	jh80.chung@samsung.com, linux-pci@vger.kernel.org,
	 devicetree@vger.kernel.org,
	linux-riscv <linux-riscv@lists.infradead.org>,
	 Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	linux-clk@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>
Subject: Re: [PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
Date: Mon, 19 Apr 2021 10:48:46 +0800	[thread overview]
Message-ID: <CAHCEehLG-FmQiBJpNExO8wa_8LYWmw-1R7KfyEEMyz=Y3srcUw@mail.gmail.com> (raw)
In-Reply-To: <CAHCEehL+3ZxKv_nxSR6s0vWEFtNHSYOX_dHrpfGq1hM8xwhHRQ@mail.gmail.com>

Greentime Hu <greentime.hu@sifive.com> 於 2021年4月19日 週一 上午10:43寫道：
>
> Palmer Dabbelt <palmer@dabbelt.com> 於 2021年3月31日 週三 上午8:24寫道：
> >
> > On Wed, 17 Mar 2021 23:08:13 PDT (-0700), greentime.hu@sifive.com wrote:
> > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > > ---
> > >  arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++++
> > >  1 file changed, 34 insertions(+)
> > >
> > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > index d1bb22b11920..d0839739b425 100644
> > > --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > @@ -158,6 +158,7 @@ prci: clock-controller@10000000 {
> > >                       reg = <0x0 0x10000000 0x0 0x1000>;
> > >                       clocks = <&hfclk>, <&rtcclk>;
> > >                       #clock-cells = <1>;
> > > +                     #reset-cells = <1>;
> > >               };
> > >               uart0: serial@10010000 {
> > >                       compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> > > @@ -288,5 +289,38 @@ gpio: gpio@10060000 {
> > >                       clocks = <&prci PRCI_CLK_PCLK>;
> > >                       status = "disabled";
> > >               };
> > > +             pcie@e00000000 {
> > > +                     #address-cells = <3>;
> > > +                     #interrupt-cells = <1>;
> > > +                     #num-lanes = <8>;
> > > +                     #size-cells = <2>;
> > > +                     compatible = "sifive,fu740-pcie";
> > > +                     reg = <0xe 0x00000000 0x1 0x0
> > > +                            0xd 0xf0000000 0x0 0x10000000
> > > +                            0x0 0x100d0000 0x0 0x1000>;
> > > +                     reg-names = "dbi", "config", "mgmt";
> > > +                     device_type = "pci";
> > > +                     dma-coherent;
> > > +                     bus-range = <0x0 0xff>;
> > > +                     ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000        /* I/O */
> > > +                               0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000      /* mem */
> > > +                               0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000      /* mem */
> > > +                               0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
> > > +                     num-lanes = <0x8>;
> > > +                     interrupts = <56 57 58 59 60 61 62 63 64>;
> > > +                     interrupt-names = "msi", "inta", "intb", "intc", "intd";
> > > +                     interrupt-parent = <&plic0>;
> > > +                     interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> > > +                     interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
> > > +                                     <0x0 0x0 0x0 0x2 &plic0 58>,
> > > +                                     <0x0 0x0 0x0 0x3 &plic0 59>,
> > > +                                     <0x0 0x0 0x0 0x4 &plic0 60>;
> > > +                     clock-names = "pcie_aux";
> > > +                     clocks = <&prci PRCI_CLK_PCIE_AUX>;
> > > +                     pwren-gpios = <&gpio 5 0>;
> > > +                     perstn-gpios = <&gpio 8 0>;
> > > +                     resets = <&prci 4>;
> > > +                     status = "okay";
> > > +             };
> > >       };
> > >  };
> >
> > Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> >
> > I'm happy to take these all through the RISC-V tree if that helps, but
> > as usual I'd like reviews or acks from the subsystem maintainers.  It
> > looks like there are some issues so I'm going to drop this from my
> > inbox.
>
> Hi Palmer,
>
> Since the subsystem maintainer has pick the first 5 patches to his
> branch, would you please help to pick the 6th patch of version 6?

Sorry there is no version 6, I mean version 5. :p

> Thank you. :)
>
> https://www.spinics.net/lists/linux-clk/msg57213.html
> https://patchwork.kernel.org/project/linux-riscv/patch/20210406092634.50465-7-greentime.hu@sifive.com/

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