Re: [PATCH -next V8 06/14] riscv: convert to generic entry

From: Guo Ren <guoren@kernel.org>
To: "Björn Töpel" <bjorn@kernel.org>
Cc: arnd@arndb.de, palmer@rivosinc.com, tglx@linutronix.de,
	 peterz@infradead.org, luto@kernel.org,
	conor.dooley@microchip.com,  heiko@sntech.de, jszhang@kernel.org,
	lazyparser@gmail.com, falcon@tinylab.org,  chenhuacai@kernel.org,
	apatel@ventanamicro.com, atishp@atishpatra.org,
	 palmer@dabbelt.com, paul.walmsley@sifive.com,
	mark.rutland@arm.com,  zouyipeng@huawei.com,
	bigeasy@linutronix.de, David.Laight@aculab.com,
	 chenzhongjin@huawei.com, greentime.hu@sifive.com,
	andy.chiu@sifive.com,  linux-arch@vger.kernel.org,
	linux-kernel@vger.kernel.org,  linux-riscv@lists.infradead.org,
	Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH -next V8 06/14] riscv: convert to generic entry
Date: Tue, 6 Dec 2022 14:39:58 +0800	[thread overview]
Message-ID: <CAJF2gTRsZMM9vPqRWEwzOOhW2czo8uOJEtTGjixJig1kdQP1hg@mail.gmail.com> (raw)
In-Reply-To: <874jua9lcp.fsf@all.your.base.are.belong.to.us>

On Mon, Dec 5, 2022 at 6:49 PM Björn Töpel <bjorn@kernel.org> wrote:
>
> guoren@kernel.org writes:
>
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > This patch converts riscv to use the generic entry infrastructure from
> > kernel/entry/*. The generic entry makes maintainers' work easier and
> > codes more elegant. Here are the changes than before:
> >
> >  - More clear entry.S with handle_exception and ret_from_exception
> >  - Get rid of complex custom signal implementation
> >  - More readable syscall procedure
> >  - Little modification on ret_from_fork & ret_from_kernel_thread
> >  - Wrap with irqentry_enter/exit and syscall_enter/exit_from_user_mode
> >  - Use the standard preemption code instead of custom
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > Suggested-by: Huacai Chen <chenhuacai@kernel.org>
> > Tested-by: Yipeng Zou <zouyipeng@huawei.com>
> > ---
>
> [...]
>
> > diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
> > index 5d3f2fbeb33c..c86d0eafdf6a 100644
> > --- a/arch/riscv/kernel/sys_riscv.c
> > +++ b/arch/riscv/kernel/sys_riscv.c
> > @@ -5,8 +5,10 @@
> >   * Copyright (C) 2017 SiFive
> >   */
> >
> > +#include <linux/entry-common.h>
> >  #include <linux/syscalls.h>
> >  #include <asm/unistd.h>
> > +#include <asm/syscall.h>
> >  #include <asm/cacheflush.h>
> >  #include <asm-generic/mman-common.h>
> >
> > @@ -69,3 +71,28 @@ SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
> >
> >       return 0;
> >  }
> > +
> > +typedef long (*syscall_t)(ulong, ulong, ulong, ulong, ulong, ulong, ulong);
> > +
> > +asmlinkage void do_sys_ecall_u(struct pt_regs *regs)
> > +{
> > +     syscall_t syscall;
> > +     ulong nr = regs->a7;
> > +
> > +     regs->epc += 4;
> > +     regs->orig_a0 = regs->a0;
> > +     regs->a0 = -ENOSYS;
> > +
> > +     nr = syscall_enter_from_user_mode(regs, nr);
> > +#ifdef CONFIG_COMPAT
> > +     if ((regs->status & SR_UXL) == SR_UXL_32)
> > +             syscall = compat_sys_call_table[nr];
> > +     else
> > +#endif
> > +             syscall = sys_call_table[nr];
> > +
> > +     if (nr < NR_syscalls)
> > +             regs->a0 = syscall(regs->orig_a0, regs->a1, regs->a2,
> > +                                regs->a3, regs->a4, regs->a5,
> >       regs->a6);
>
> Now that we're doing the "pt_regs to call" dance, it would make sense to
> introduce a syscall wrapper (like x86 and arm64) for riscv, so that we
> don't need to unwrap all regs for all syscalls (See __MAP() in
> include/linux/syscalls.h). That would be an optimization, so it could be
> done as a follow-up, and not part of the series.
Thx for the reminder; I will have a look at "pt_regs to call."

>
>
> Björn


-- 
Best Regards
 Guo Ren

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