From: Rob Herring <robh+dt@kernel.org>
To: Atish Patra <atish.patra@wdc.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
Yangtao Li <tiny.windzz@gmail.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Johan Hovold <johan@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>, Gary Guo <gary@garyguo.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, Enrico Weigelt <info@metux.net>,
Thomas Gleixner <tglx@linutronix.de>,
Allison Randal <allison@lohutok.net>
Subject: Re: [PATCH v3 5/5] dt-bindings: Update the riscv, isa string description
Date: Thu, 1 Aug 2019 09:50:37 -0600 [thread overview]
Message-ID: <CAL_JsqLqxN1+fvrdD24Ho6s7gB+pGy-0sZaL-jJqkYZ2yC4JEA@mail.gmail.com> (raw)
In-Reply-To: <20190801005843.10343-6-atish.patra@wdc.com>
On Wed, Jul 31, 2019 at 6:58 PM Atish Patra <atish.patra@wdc.com> wrote:
>
> Since the RISC-V specification states that ISA description strings are
> case-insensitive, there's no functional difference between mixed-case,
> upper-case, and lower-case ISA strings. Thus, to simplify parsing,
> specify that the letters present in "riscv,isa" must be all lowercase.
>
> Suggested-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index c899111aa5e3..4f0acb00185a 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -46,10 +46,12 @@ properties:
> - rv64imafdc
> description:
> Identifies the specific RISC-V instruction set architecture
> - supported by the hart. These are documented in the RISC-V
> + supported by the hart. These are documented in the RISC-V
> User-Level ISA document, available from
> https://riscv.org/specifications/
>
> + Letters in the riscv,isa string must be all lowercase.
> +
The schemas are case sensitive this looks pretty pointless without the
context of the commit msg. Can you prefix with 'While the
specification is case insensitive, "
For some background, FDT generally always has been case sensitive too
(dtc won't merge/override nodes/properties with differing case). It's
really only some older true OF systems that were case insensitive. The
kernel had a mixture of case sensitive and insensitive comparisons
somewhat depending on the arch and whether of_prop_cmp/of_node_cmp or
str*cmp functions were used. There's been a lot of clean-up and now
most comparisons are case sensitive with only Sparc having some
deviation.
Rob
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next prev parent reply other threads:[~2019-08-01 15:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-01 0:58 [PATCH v3 0/5] Miscellaneous fixes Atish Patra
2019-08-01 0:58 ` [PATCH v3 1/5] RISC-V: Remove per cpu clocksource Atish Patra
2019-08-01 0:58 ` [PATCH v3 2/5] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Atish Patra
2019-08-01 0:58 ` [PATCH v3 3/5] RISC-V: Fix unsupported isa string info Atish Patra
2019-08-06 23:27 ` Paul Walmsley
2019-08-07 1:13 ` Atish Patra
2019-08-07 1:26 ` Paul Walmsley
2019-08-07 15:37 ` Palmer Dabbelt
2019-08-07 17:31 ` Atish Patra
2019-08-07 17:42 ` Palmer Dabbelt
2019-08-01 0:58 ` [PATCH v3 4/5] RISC-V: Export few kernel symbols Atish Patra
2019-08-01 15:56 ` Christoph Hellwig
2019-08-01 23:04 ` Atish Patra
2019-08-01 0:58 ` [PATCH v3 5/5] dt-bindings: Update the riscv,isa string description Atish Patra
2019-08-01 15:50 ` Rob Herring [this message]
2019-08-01 23:07 ` Atish Patra
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