* [PATCH v3 00/15] Support ROHM BD71815 PMIC
@ 2021-03-08 10:39 Matti Vaittinen
2021-03-08 10:39 ` [PATCH v3 01/15] rtc: bd70528: Do not require parent data Matti Vaittinen
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Matti Vaittinen @ 2021-03-08 10:39 UTC (permalink / raw)
To: matti.vaittinen, mazziesaccount
Cc: Lee Jones, Rob Herring, Liam Girdwood, Mark Brown,
Matti Vaittinen, Michael Turquette, Stephen Boyd, Linus Walleij,
Bartosz Golaszewski, Alessandro Zummo, Alexandre Belloni,
devicetree, linux-kernel, linux-power, linux-clk, linux-gpio,
linux-rtc
Patch series introducing support for ROHM BD71815 PMIC
ROHM BD71815 is a power management IC used in some battery powered
systems. It contains regulators, GPO(s), charger + coulomb counter, RTC
and a clock gate.
All regulators can be controlled via I2C. LDO4 can additionally be set to
be enabled/disabled by a GPIO. LDO3 voltage could be selected from two
voltages written into separate VSEL reisters using GPIO but this mode is
not supported by driver. On top of that the PMIC has the typical HW
state machine which is present also on many other ROHM PMICs.
IC contains two GPOs - but one of the GPOs is marked as GND in
data-sheet. Thus the driver by default only exposes one GPO. The second
GPO can be enabled by special DT property.
RTC is almost similar to what is on BD71828. For currently used features
only the register address offset to RTC block differs.
The charger driver is not included in this series. ROHM has a charger
driver with some fuel-gauging logig written in but this is not included
here. I am working on separating the logic from HW specific driver and
supporting both BD71815 and BD71828 chargers in separate patch series.
Changelog v3:
- GPIO clean-up as suggested by Bartosz
- MFD clean-up as suggested by Lee
- clk-mode dt-binding handling in MFD driver corrected to reflect new
property values.
- Dropped already applied patches
- Rebased on v5.12-rc2
Changelog v2:
- Rebased on top of v5.11-rc3
- Added another "preliminary patch" which fixes HW-dvs voltage
handling (patch 1)
- split regulator patch to two.
- changed dt-binding patch ordering.
regulators:
- staticized probe
- removed some unnecessary defines
- updated comments
- split rohm-regulator patch adding SNVS and supporting simple
linear mapping into two - one adding support for mapping, other
adding SNVS.
GPIO:
- removed unnecessary headers
- clarified dev/parent->dev usage
- removed forgotten #define DEBUG
dt-bindings:
- changed patch order to meet ref-dependencies
- added missing regulator nodes
- changed string property for clk mode to tristated
MFD:
- header cleanups.
CLK:
- fixed commit message
Matti Vaittinen (15):
rtc: bd70528: Do not require parent data
mfd: bd718x7: simplify by cleaning unnecessary device data
dt_bindings: bd71828: Add clock output mode
dt_bindings: regulator: Add ROHM BD71815 PMIC regulators
dt_bindings: mfd: Add ROHM BD71815 PMIC
mfd: Add ROHM BD71815 ID
mfd: Support for ROHM BD71815 PMIC core
gpio: support ROHM BD71815 GPOs
regulator: helpers: Export helper voltage listing
regulator: rohm-regulator: linear voltage support
regulator: rohm-regulator: Support SNVS HW state.
regulator: Support ROHM BD71815 regulators
clk: bd718x7: Add support for clk gate on ROHM BD71815 PMIC
rtc: bd70528: Support RTC on ROHM BD71815
MAINTAINERS: Add ROHM BD71815AGW
.../bindings/mfd/rohm,bd71815-pmic.yaml | 201 ++++++
.../bindings/mfd/rohm,bd71828-pmic.yaml | 6 +
.../regulator/rohm,bd71815-regulator.yaml | 116 +++
MAINTAINERS | 3 +
drivers/clk/clk-bd718x7.c | 9 +-
drivers/gpio/Kconfig | 10 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-bd71815.c | 176 +++++
drivers/mfd/Kconfig | 15 +-
drivers/mfd/rohm-bd71828.c | 486 +++++++++----
drivers/mfd/rohm-bd718x7.c | 43 +-
drivers/regulator/Kconfig | 11 +
drivers/regulator/Makefile | 1 +
drivers/regulator/bd71815-regulator.c | 682 ++++++++++++++++++
drivers/regulator/helpers.c | 36 +-
drivers/regulator/rohm-regulator.c | 23 +-
drivers/rtc/Kconfig | 6 +-
drivers/rtc/rtc-bd70528.c | 104 ++-
include/linux/mfd/rohm-bd71815.h | 563 +++++++++++++++
include/linux/mfd/rohm-bd71828.h | 3 +
include/linux/mfd/rohm-bd718x7.h | 13 -
include/linux/mfd/rohm-generic.h | 7 +-
include/linux/regulator/driver.h | 2 +
23 files changed, 2289 insertions(+), 228 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml
create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml
create mode 100644 drivers/gpio/gpio-bd71815.c
create mode 100644 drivers/regulator/bd71815-regulator.c
create mode 100644 include/linux/mfd/rohm-bd71815.h
base-commit: a38fd8748464831584a19438cbb3082b5a2dab15
--
2.25.4
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 01/15] rtc: bd70528: Do not require parent data
2021-03-08 10:39 [PATCH v3 00/15] Support ROHM BD71815 PMIC Matti Vaittinen
@ 2021-03-08 10:39 ` Matti Vaittinen
2021-03-08 10:41 ` [PATCH v3 06/15] mfd: Add ROHM BD71815 ID Matti Vaittinen
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Matti Vaittinen @ 2021-03-08 10:39 UTC (permalink / raw)
To: matti.vaittinen, mazziesaccount
Cc: Lee Jones, Matti Vaittinen, Alessandro Zummo, Alexandre Belloni,
linux-kernel, linux-power, linux-rtc
The ROHM BD71828 and BD71815 RTC drivers only need the regmap
pointer from parent. Regmap can be obtained via dev_get_regmap()
so do not require parent to populate driver data for that.
BD70528 on the other hand requires parent data to access the
watchdog so leave the parent data for BD70528 here for now.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/rtc/rtc-bd70528.c | 67 ++++++++++++++++++---------------------
1 file changed, 31 insertions(+), 36 deletions(-)
diff --git a/drivers/rtc/rtc-bd70528.c b/drivers/rtc/rtc-bd70528.c
index 17cb67f5bf6e..fb4476bb5ab6 100644
--- a/drivers/rtc/rtc-bd70528.c
+++ b/drivers/rtc/rtc-bd70528.c
@@ -52,6 +52,7 @@ struct bd70528_rtc_alm {
struct bd70528_rtc {
struct rohm_regmap_dev *parent;
+ struct regmap *regmap;
struct device *dev;
u8 reg_time_start;
bool has_rtc_timers;
@@ -234,9 +235,8 @@ static int bd71828_set_alarm(struct device *dev, struct rtc_wkalrm *a)
int ret;
struct bd71828_rtc_alm alm;
struct bd70528_rtc *r = dev_get_drvdata(dev);
- struct rohm_regmap_dev *parent = r->parent;
- ret = regmap_bulk_read(parent->regmap, BD71828_REG_RTC_ALM_START,
+ ret = regmap_bulk_read(r->regmap, BD71828_REG_RTC_ALM_START,
&alm, sizeof(alm));
if (ret) {
dev_err(dev, "Failed to read alarm regs\n");
@@ -250,7 +250,7 @@ static int bd71828_set_alarm(struct device *dev, struct rtc_wkalrm *a)
else
alm.alm_mask |= BD70528_MASK_ALM_EN;
- ret = regmap_bulk_write(parent->regmap, BD71828_REG_RTC_ALM_START,
+ ret = regmap_bulk_write(r->regmap, BD71828_REG_RTC_ALM_START,
&alm, sizeof(alm));
if (ret)
dev_err(dev, "Failed to set alarm time\n");
@@ -265,17 +265,16 @@ static int bd70528_set_alarm(struct device *dev, struct rtc_wkalrm *a)
struct bd70528_rtc_alm alm;
int ret;
struct bd70528_rtc *r = dev_get_drvdata(dev);
- struct rohm_regmap_dev *parent = r->parent;
- ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_WAKE_START,
- &wake, sizeof(wake));
+ ret = regmap_bulk_read(r->regmap, BD70528_REG_RTC_WAKE_START, &wake,
+ sizeof(wake));
if (ret) {
dev_err(dev, "Failed to read wake regs\n");
return ret;
}
- ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_ALM_START,
- &alm, sizeof(alm));
+ ret = regmap_bulk_read(r->regmap, BD70528_REG_RTC_ALM_START, &alm,
+ sizeof(alm));
if (ret) {
dev_err(dev, "Failed to read alarm regs\n");
return ret;
@@ -292,15 +291,14 @@ static int bd70528_set_alarm(struct device *dev, struct rtc_wkalrm *a)
wake.ctrl &= ~BD70528_MASK_WAKE_EN;
}
- ret = regmap_bulk_write(parent->regmap,
- BD70528_REG_RTC_WAKE_START, &wake,
+ ret = regmap_bulk_write(r->regmap, BD70528_REG_RTC_WAKE_START, &wake,
sizeof(wake));
if (ret) {
dev_err(dev, "Failed to set wake time\n");
return ret;
}
- ret = regmap_bulk_write(parent->regmap, BD70528_REG_RTC_ALM_START,
- &alm, sizeof(alm));
+ ret = regmap_bulk_write(r->regmap, BD70528_REG_RTC_ALM_START, &alm,
+ sizeof(alm));
if (ret)
dev_err(dev, "Failed to set alarm time\n");
@@ -312,9 +310,8 @@ static int bd71828_read_alarm(struct device *dev, struct rtc_wkalrm *a)
int ret;
struct bd71828_rtc_alm alm;
struct bd70528_rtc *r = dev_get_drvdata(dev);
- struct rohm_regmap_dev *parent = r->parent;
- ret = regmap_bulk_read(parent->regmap, BD71828_REG_RTC_ALM_START,
+ ret = regmap_bulk_read(r->regmap, BD71828_REG_RTC_ALM_START,
&alm, sizeof(alm));
if (ret) {
dev_err(dev, "Failed to read alarm regs\n");
@@ -336,10 +333,9 @@ static int bd70528_read_alarm(struct device *dev, struct rtc_wkalrm *a)
struct bd70528_rtc_alm alm;
int ret;
struct bd70528_rtc *r = dev_get_drvdata(dev);
- struct rohm_regmap_dev *parent = r->parent;
- ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_ALM_START,
- &alm, sizeof(alm));
+ ret = regmap_bulk_read(r->regmap, BD70528_REG_RTC_ALM_START, &alm,
+ sizeof(alm));
if (ret) {
dev_err(dev, "Failed to read alarm regs\n");
return ret;
@@ -360,14 +356,12 @@ static int bd70528_set_time_locked(struct device *dev, struct rtc_time *t)
int ret, tmpret, old_states;
struct bd70528_rtc_data rtc_data;
struct bd70528_rtc *r = dev_get_drvdata(dev);
- struct rohm_regmap_dev *parent = r->parent;
ret = bd70528_disable_rtc_based_timers(r, &old_states);
if (ret)
return ret;
- tmpret = regmap_bulk_read(parent->regmap,
- r->reg_time_start, &rtc_data,
+ tmpret = regmap_bulk_read(r->regmap, r->reg_time_start, &rtc_data,
sizeof(rtc_data));
if (tmpret) {
dev_err(dev, "Failed to read RTC time registers\n");
@@ -375,8 +369,7 @@ static int bd70528_set_time_locked(struct device *dev, struct rtc_time *t)
}
tm2rtc(t, &rtc_data);
- tmpret = regmap_bulk_write(parent->regmap,
- r->reg_time_start, &rtc_data,
+ tmpret = regmap_bulk_write(r->regmap, r->reg_time_start, &rtc_data,
sizeof(rtc_data));
if (tmpret) {
dev_err(dev, "Failed to set RTC time\n");
@@ -410,13 +403,11 @@ static int bd70528_set_time(struct device *dev, struct rtc_time *t)
static int bd70528_get_time(struct device *dev, struct rtc_time *t)
{
struct bd70528_rtc *r = dev_get_drvdata(dev);
- struct rohm_regmap_dev *parent = r->parent;
struct bd70528_rtc_data rtc_data;
int ret;
/* read the RTC date and time registers all at once */
- ret = regmap_bulk_read(parent->regmap,
- r->reg_time_start, &rtc_data,
+ ret = regmap_bulk_read(r->regmap, r->reg_time_start, &rtc_data,
sizeof(rtc_data));
if (ret) {
dev_err(dev, "Failed to read RTC time (err %d)\n", ret);
@@ -443,7 +434,7 @@ static int bd70528_alm_enable(struct device *dev, unsigned int enabled)
dev_err(dev, "Failed to change wake state\n");
goto out_unlock;
}
- ret = regmap_update_bits(r->parent->regmap, BD70528_REG_RTC_ALM_MASK,
+ ret = regmap_update_bits(r->regmap, BD70528_REG_RTC_ALM_MASK,
BD70528_MASK_ALM_EN, enableval);
if (ret)
dev_err(dev, "Failed to change alarm state\n");
@@ -462,7 +453,7 @@ static int bd71828_alm_enable(struct device *dev, unsigned int enabled)
if (!enabled)
enableval = 0;
- ret = regmap_update_bits(r->parent->regmap, BD71828_REG_RTC_ALM0_MASK,
+ ret = regmap_update_bits(r->regmap, BD71828_REG_RTC_ALM0_MASK,
BD70528_MASK_ALM_EN, enableval);
if (ret)
dev_err(dev, "Failed to change alarm state\n");
@@ -498,7 +489,6 @@ static int bd70528_probe(struct platform_device *pdev)
{
struct bd70528_rtc *bd_rtc;
const struct rtc_class_ops *rtc_ops;
- struct rohm_regmap_dev *parent;
const char *irq_name;
int ret;
struct rtc_device *rtc;
@@ -508,20 +498,25 @@ static int bd70528_probe(struct platform_device *pdev)
u8 hour_reg;
enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data;
- parent = dev_get_drvdata(pdev->dev.parent);
- if (!parent) {
- dev_err(&pdev->dev, "No MFD driver data\n");
- return -EINVAL;
- }
bd_rtc = devm_kzalloc(&pdev->dev, sizeof(*bd_rtc), GFP_KERNEL);
if (!bd_rtc)
return -ENOMEM;
- bd_rtc->parent = parent;
+ bd_rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!bd_rtc->regmap) {
+ dev_err(&pdev->dev, "No regmap\n");
+ return -EINVAL;
+ }
+
bd_rtc->dev = &pdev->dev;
switch (chip) {
case ROHM_CHIP_TYPE_BD70528:
+ bd_rtc->parent = dev_get_drvdata(pdev->dev.parent);
+ if (!bd_rtc->parent) {
+ dev_err(&pdev->dev, "No MFD data\n");
+ return -EINVAL;
+ }
irq_name = "bd70528-rtc-alm";
bd_rtc->has_rtc_timers = true;
bd_rtc->reg_time_start = BD70528_REG_RTC_START;
@@ -547,7 +542,7 @@ static int bd70528_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, bd_rtc);
- ret = regmap_read(parent->regmap, hour_reg, &hr);
+ ret = regmap_read(bd_rtc->regmap, hour_reg, &hr);
if (ret) {
dev_err(&pdev->dev, "Failed to reag RTC clock\n");
@@ -595,7 +590,7 @@ static int bd70528_probe(struct platform_device *pdev)
* from sub-registers when IRQ is disabled or freed.
*/
if (enable_main_irq) {
- ret = regmap_update_bits(parent->regmap,
+ ret = regmap_update_bits(bd_rtc->regmap,
BD70528_REG_INT_MAIN_MASK,
BD70528_INT_RTC_MASK, 0);
if (ret) {
--
2.25.4
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 06/15] mfd: Add ROHM BD71815 ID
2021-03-08 10:39 [PATCH v3 00/15] Support ROHM BD71815 PMIC Matti Vaittinen
2021-03-08 10:39 ` [PATCH v3 01/15] rtc: bd70528: Do not require parent data Matti Vaittinen
@ 2021-03-08 10:41 ` Matti Vaittinen
2021-03-10 10:36 ` Lee Jones
2021-03-08 10:42 ` [PATCH v3 07/15] mfd: Support for ROHM BD71815 PMIC core Matti Vaittinen
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Matti Vaittinen @ 2021-03-08 10:41 UTC (permalink / raw)
To: matti.vaittinen, mazziesaccount
Cc: Lee Jones, matti.vaittinen, linux-kernel, linux-power, linux-clk,
linux-gpio, linux-rtc
Add chip ID for ROHM BD71815 and PMIC so that drivers can identify
this IC.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
include/linux/mfd/rohm-generic.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h
index 66f673c35303..e5392bcbc098 100644
--- a/include/linux/mfd/rohm-generic.h
+++ b/include/linux/mfd/rohm-generic.h
@@ -14,6 +14,7 @@ enum rohm_chip_type {
ROHM_CHIP_TYPE_BD71828,
ROHM_CHIP_TYPE_BD9571,
ROHM_CHIP_TYPE_BD9574,
+ ROHM_CHIP_TYPE_BD71815,
ROHM_CHIP_TYPE_AMOUNT
};
--
2.25.4
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 07/15] mfd: Support for ROHM BD71815 PMIC core
2021-03-08 10:39 [PATCH v3 00/15] Support ROHM BD71815 PMIC Matti Vaittinen
2021-03-08 10:39 ` [PATCH v3 01/15] rtc: bd70528: Do not require parent data Matti Vaittinen
2021-03-08 10:41 ` [PATCH v3 06/15] mfd: Add ROHM BD71815 ID Matti Vaittinen
@ 2021-03-08 10:42 ` Matti Vaittinen
2021-03-10 10:40 ` Lee Jones
2021-03-08 10:45 ` [PATCH v3 14/15] rtc: bd70528: Support RTC on ROHM BD71815 Matti Vaittinen
2021-03-08 10:45 ` [PATCH v3 15/15] MAINTAINERS: Add ROHM BD71815AGW Matti Vaittinen
4 siblings, 1 reply; 14+ messages in thread
From: Matti Vaittinen @ 2021-03-08 10:42 UTC (permalink / raw)
To: matti.vaittinen, mazziesaccount
Cc: Lee Jones, Rob Herring, Liam Girdwood, Mark Brown,
Matti Vaittinen, Michael Turquette, Stephen Boyd, Linus Walleij,
Bartosz Golaszewski, Alessandro Zummo, Alexandre Belloni,
devicetree, linux-kernel, linux-power, linux-clk, linux-gpio,
linux-rtc
Add core support for ROHM BD71815 Power Management IC.
The IC integrates regulators, a battery charger with a coulomb counter,
a real-time clock (RTC), clock gate and general-purpose outputs (GPO).
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
---
Changes since v2:
- styling / clean-ups suggested by Lee
- corrected clk-mode dt property values to match changed bindings
drivers/mfd/Kconfig | 15 +-
drivers/mfd/rohm-bd71828.c | 486 +++++++++++++++++++-------
include/linux/mfd/rohm-bd71815.h | 563 +++++++++++++++++++++++++++++++
include/linux/mfd/rohm-bd71828.h | 3 +
4 files changed, 934 insertions(+), 133 deletions(-)
create mode 100644 include/linux/mfd/rohm-bd71815.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b74efa469e90..60d9ae559f0a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1975,19 +1975,20 @@ config MFD_ROHM_BD70528
charger.
config MFD_ROHM_BD71828
- tristate "ROHM BD71828 Power Management IC"
+ tristate "ROHM BD71828 and BD71815 Power Management IC"
depends on I2C=y
depends on OF
select REGMAP_I2C
select REGMAP_IRQ
select MFD_CORE
help
- Select this option to get support for the ROHM BD71828 Power
- Management IC. BD71828GW is a single-chip power management IC for
- battery-powered portable devices. The IC integrates 7 buck
- converters, 7 LDOs, and a 1500 mA single-cell linear charger.
- Also included is a Coulomb counter, a real-time clock (RTC), and
- a 32.768 kHz clock gate.
+ Select this option to get support for the ROHM BD71828 and BD71815
+ Power Management ICs. BD71828GW and BD71815AGW are single-chip power
+ management ICs mainly for battery-powered portable devices.
+ The BD71828 integrates 7 buck converters and 7 LDOs. The BD71815
+ has 5 bucks, 7 LDOs, and a boost for driving LEDs. Both ICs provide
+ also a single-cell linear charger, a Coulomb counter, a real-time
+ clock (RTC), GPIOs and a 32.768 kHz clock gate.
config MFD_STM32_LPTIMER
tristate "Support for STM32 Low-Power Timer"
diff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c
index 210261d026f2..714d9fcbf07b 100644
--- a/drivers/mfd/rohm-bd71828.c
+++ b/drivers/mfd/rohm-bd71828.c
@@ -2,7 +2,7 @@
//
// Copyright (C) 2019 ROHM Semiconductors
//
-// ROHM BD71828 PMIC driver
+// ROHM BD71828/BD71815 PMIC driver
#include <linux/gpio_keys.h>
#include <linux/i2c.h>
@@ -11,7 +11,9 @@
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
+#include <linux/mfd/rohm-bd71815.h>
#include <linux/mfd/rohm-bd71828.h>
+#include <linux/mfd/rohm-generic.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
@@ -29,12 +31,84 @@ static struct gpio_keys_platform_data bd71828_powerkey_data = {
.name = "bd71828-pwrkey",
};
-static const struct resource rtc_irqs[] = {
+static const struct resource bd71815_rtc_irqs[] = {
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd71815-rtc-alm-0"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd71815-rtc-alm-1"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd71815-rtc-alm-2"),
+};
+
+static const struct resource bd71828_rtc_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd71828-rtc-alm-0"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd71828-rtc-alm-1"),
DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd71828-rtc-alm-2"),
};
+static struct resource bd71815_power_irqs[] = {
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-clps-out"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-clps-in"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-bat-low-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-bat-low-det"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-bat-hi-res"),
+ DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-bat-hi-det"),
+};
+
+static struct mfd_cell bd71815_mfd_cells[] = {
+ { .name = "bd71815-pmic", },
+ { .name = "bd71815-clk", },
+ { .name = "bd71815-gpo", },
+ {
+ .name = "bd71815-power",
+ .num_resources = ARRAY_SIZE(bd71815_power_irqs),
+ .resources = &bd71815_power_irqs[0],
+ },
+ {
+ .name = "bd71815-rtc",
+ .num_resources = ARRAY_SIZE(bd71815_rtc_irqs),
+ .resources = &bd71815_rtc_irqs[0],
+ },
+};
+
static struct mfd_cell bd71828_mfd_cells[] = {
{ .name = "bd71828-pmic", },
{ .name = "bd71828-gpio", },
@@ -47,8 +121,8 @@ static struct mfd_cell bd71828_mfd_cells[] = {
{ .name = "bd71827-power", },
{
.name = "bd71828-rtc",
- .resources = rtc_irqs,
- .num_resources = ARRAY_SIZE(rtc_irqs),
+ .resources = bd71828_rtc_irqs,
+ .num_resources = ARRAY_SIZE(bd71828_rtc_irqs),
}, {
.name = "gpio-keys",
.platform_data = &bd71828_powerkey_data,
@@ -56,7 +130,35 @@ static struct mfd_cell bd71828_mfd_cells[] = {
},
};
-static const struct regmap_range volatile_ranges[] = {
+static const struct regmap_range bd71815_volatile_ranges[] = {
+ {
+ .range_min = BD71815_REG_SEC,
+ .range_max = BD71815_REG_YEAR,
+ }, {
+ .range_min = BD71815_REG_CONF,
+ .range_max = BD71815_REG_BAT_TEMP,
+ }, {
+ .range_min = BD71815_REG_VM_IBAT_U,
+ .range_max = BD71815_REG_CC_CTRL,
+ }, {
+ .range_min = BD71815_REG_CC_STAT,
+ .range_max = BD71815_REG_CC_CURCD_L,
+ }, {
+ .range_min = BD71815_REG_VM_BTMP_MON,
+ .range_max = BD71815_REG_VM_BTMP_MON,
+ }, {
+ .range_min = BD71815_REG_INT_STAT,
+ .range_max = BD71815_REG_INT_UPDATE,
+ }, {
+ .range_min = BD71815_REG_VM_VSYS_U,
+ .range_max = BD71815_REG_REX_CTRL_1,
+ }, {
+ .range_min = BD71815_REG_FULL_CCNTD_3,
+ .range_max = BD71815_REG_CCNTD_CHG_2,
+ },
+};
+
+static const struct regmap_range bd71828_volatile_ranges[] = {
{
.range_min = BD71828_REG_PS_CTRL_1,
.range_max = BD71828_REG_PS_CTRL_1,
@@ -80,15 +182,28 @@ static const struct regmap_range volatile_ranges[] = {
},
};
-static const struct regmap_access_table volatile_regs = {
- .yes_ranges = &volatile_ranges[0],
- .n_yes_ranges = ARRAY_SIZE(volatile_ranges),
+static const struct regmap_access_table bd71815_volatile_regs = {
+ .yes_ranges = &bd71815_volatile_ranges[0],
+ .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges),
+};
+
+static const struct regmap_access_table bd71828_volatile_regs = {
+ .yes_ranges = &bd71828_volatile_ranges[0],
+ .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges),
+};
+
+static const struct regmap_config bd71815_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .volatile_table = &bd71815_volatile_regs,
+ .max_register = BD71815_MAX_REGISTER - 1,
+ .cache_type = REGCACHE_RBTREE,
};
-static struct regmap_config bd71828_regmap = {
+static const struct regmap_config bd71828_regmap = {
.reg_bits = 8,
.val_bits = 8,
- .volatile_table = &volatile_regs,
+ .volatile_table = &bd71828_volatile_regs,
.max_register = BD71828_MAX_REGISTER,
.cache_type = REGCACHE_RBTREE,
};
@@ -96,7 +211,7 @@ static struct regmap_config bd71828_regmap = {
/*
* Mapping of main IRQ register bits to sub-IRQ register offsets so that we can
* access corect sub-IRQ registers based on bits that are set in main IRQ
- * register.
+ * register. BD71815 and BD71828 have same sub-register-block offests.
*/
static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */
@@ -108,7 +223,7 @@ static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */
static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */
static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */
-static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = {
+static struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = {
REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
@@ -119,6 +234,88 @@ static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = {
REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
};
+static const struct regmap_irq bd71815_irqs[] = {
+ REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK),
+ /* DCIN1 interrupts */
+ REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK),
+ /* DCIN2 interrupts */
+ REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK),
+ /* Vsys */
+ REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK),
+ /* Charger */
+ REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4,
+ BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK),
+ /* Battery */
+ REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK),
+ /* Battery Mon 1 */
+ REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK),
+ /* Battery Mon 2 */
+ REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK),
+ /* Battery Mon 3 (Coulomb counter) */
+ REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK),
+ /* Battery Mon 4 */
+ REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK),
+ /* Temperature */
+ REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10,
+ BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10,
+ BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10,
+ BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10,
+ BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK),
+ /* RTC Alarm */
+ REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK),
+ REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK),
+};
+
static struct regmap_irq bd71828_irqs[] = {
REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK),
REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK),
@@ -134,10 +331,8 @@ static struct regmap_irq bd71828_irqs[] = {
REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK),
REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK),
/* DCIN2 interrupts */
- REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2,
- BD71828_INT_DCIN_MON_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2,
- BD71828_INT_DCIN_MON_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK),
REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK),
REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK),
@@ -145,102 +340,59 @@ static struct regmap_irq bd71828_irqs[] = {
REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK),
REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK),
/* Vsys */
- REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3,
- BD71828_INT_VSYS_UV_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3,
- BD71828_INT_VSYS_UV_DET_MASK),
- REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3,
- BD71828_INT_VSYS_LOW_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3,
- BD71828_INT_VSYS_LOW_DET_MASK),
- REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3,
- BD71828_INT_VSYS_HALL_IN_MASK),
- REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3,
- BD71828_INT_VSYS_HALL_TOGGLE_MASK),
- REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3,
- BD71828_INT_VSYS_MON_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3,
- BD71828_INT_VSYS_MON_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK),
/* Charger */
- REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4,
- BD71828_INT_CHG_DCIN_ILIM_MASK),
- REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4,
- BD71828_INT_CHG_TOPOFF_TO_DONE_MASK),
- REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4,
- BD71828_INT_CHG_WDG_TEMP_MASK),
- REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4,
- BD71828_INT_CHG_WDG_TIME_MASK),
- REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4,
- BD71828_INT_CHG_RECHARGE_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4,
- BD71828_INT_CHG_RECHARGE_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4,
BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK),
- REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4,
- BD71828_INT_CHG_STATE_TRANSITION_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK),
/* Battery */
- REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5,
- BD71828_INT_BAT_TEMP_NORMAL_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5,
- BD71828_INT_BAT_TEMP_ERANGE_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5,
- BD71828_INT_BAT_TEMP_WARN_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5,
- BD71828_INT_BAT_REMOVED_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5,
- BD71828_INT_BAT_DETECTED_MASK),
- REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5,
- BD71828_INT_THERM_REMOVED_MASK),
- REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5,
- BD71828_INT_THERM_DETECTED_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK),
/* Battery Mon 1 */
REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6,
- BD71828_INT_BAT_SHORTC_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6,
- BD71828_INT_BAT_SHORTC_DET_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6,
- BD71828_INT_BAT_LOW_VOLT_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6,
- BD71828_INT_BAT_LOW_VOLT_DET_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6,
- BD71828_INT_BAT_OVER_VOLT_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6,
- BD71828_INT_BAT_OVER_VOLT_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK),
/* Battery Mon 2 */
- REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7,
- BD71828_INT_BAT_MON_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7,
- BD71828_INT_BAT_MON_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK),
/* Battery Mon 3 (Coulomb counter) */
- REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8,
- BD71828_INT_BAT_CC_MON1_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8,
- BD71828_INT_BAT_CC_MON2_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8,
- BD71828_INT_BAT_CC_MON3_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK),
/* Battery Mon 4 */
- REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9,
- BD71828_INT_BAT_OVER_CURR_1_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9,
- BD71828_INT_BAT_OVER_CURR_1_DET_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9,
- BD71828_INT_BAT_OVER_CURR_2_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9,
- BD71828_INT_BAT_OVER_CURR_2_DET_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9,
- BD71828_INT_BAT_OVER_CURR_3_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9,
- BD71828_INT_BAT_OVER_CURR_3_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK),
/* Temperature */
- REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10,
- BD71828_INT_TEMP_BAT_LOW_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10,
- BD71828_INT_TEMP_BAT_LOW_DET_MASK),
- REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10,
- BD71828_INT_TEMP_BAT_HI_RES_MASK),
- REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10,
- BD71828_INT_TEMP_BAT_HI_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK),
+ REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10,
BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK),
REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10,
@@ -267,57 +419,133 @@ static struct regmap_irq_chip bd71828_irq_chip = {
.init_ack_masked = true,
.num_regs = 12,
.num_main_regs = 1,
- .sub_reg_offsets = &bd71828_sub_irq_offsets[0],
+ .sub_reg_offsets = &bd718xx_sub_irq_offsets[0],
+ .num_main_status_bits = 8,
+ .irq_reg_stride = 1,
+};
+
+static struct regmap_irq_chip bd71815_irq_chip = {
+ .name = "bd71815_irq",
+ .main_status = BD71815_REG_INT_STAT,
+ .irqs = &bd71815_irqs[0],
+ .num_irqs = ARRAY_SIZE(bd71815_irqs),
+ .status_base = BD71815_REG_INT_STAT_01,
+ .mask_base = BD71815_REG_INT_EN_01,
+ .ack_base = BD71815_REG_INT_STAT_01,
+ .mask_invert = true,
+ .init_ack_masked = true,
+ .num_regs = 12,
+ .num_main_regs = 1,
+ .sub_reg_offsets = &bd718xx_sub_irq_offsets[0],
.num_main_status_bits = 8,
.irq_reg_stride = 1,
};
+static int set_clk_mode(struct device *dev, struct regmap *regmap,
+ int clkmode_reg)
+{
+ int ret;
+ unsigned int open_drain;
+
+ ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain);
+ if (ret) {
+ if (ret == -EINVAL)
+ return 0;
+ return ret;
+ }
+ if (open_drain > 1) {
+ dev_err(dev, "bad clk32kout mode configuration");
+ return -EINVAL;
+ }
+
+ if (open_drain)
+ return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE,
+ OUT32K_MODE_OPEN_DRAIN);
+
+ return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE,
+ OUT32K_MODE_CMOS);
+}
+
static int bd71828_i2c_probe(struct i2c_client *i2c)
{
- struct rohm_regmap_dev *chip;
struct regmap_irq_chip_data *irq_data;
int ret;
+ struct regmap *regmap;
+ const struct regmap_config *regmap_config;
+ struct regmap_irq_chip *irqchip;
+ unsigned int chip_type;
+ struct mfd_cell *mfd;
+ int cells;
+ int button_irq;
+ int clkmode_reg;
if (!i2c->irq) {
dev_err(&i2c->dev, "No IRQ configured\n");
return -EINVAL;
}
- chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL);
- if (!chip)
- return -ENOMEM;
-
- dev_set_drvdata(&i2c->dev, chip);
+ chip_type = (unsigned int)(uintptr_t)
+ of_device_get_match_data(&i2c->dev);
+ switch (chip_type) {
+ case ROHM_CHIP_TYPE_BD71828:
+ mfd = bd71828_mfd_cells;
+ cells = ARRAY_SIZE(bd71828_mfd_cells);
+ regmap_config = &bd71828_regmap;
+ irqchip = &bd71828_irq_chip;
+ clkmode_reg = BD71828_REG_OUT32K;
+ button_irq = BD71828_INT_SHORTPUSH;
+ break;
+ case ROHM_CHIP_TYPE_BD71815:
+ mfd = bd71815_mfd_cells;
+ cells = ARRAY_SIZE(bd71815_mfd_cells);
+ regmap_config = &bd71815_regmap;
+ irqchip = &bd71815_irq_chip;
+ clkmode_reg = BD71815_REG_OUT32K;
+ /*
+ * If BD71817 support is needed we should be able to handle it
+ * with proper DT configs + BD71815 drivers + power-button.
+ * BD71815 data-sheet does not list the power-button IRQ so we
+ * don't use it.
+ */
+ button_irq = 0;
+ break;
+ default:
+ dev_err(&i2c->dev, "Unknown device type");
+ return -EINVAL;
+ }
- chip->regmap = devm_regmap_init_i2c(i2c, &bd71828_regmap);
- if (IS_ERR(chip->regmap)) {
+ regmap = devm_regmap_init_i2c(i2c, regmap_config);
+ if (IS_ERR(regmap)) {
dev_err(&i2c->dev, "Failed to initialize Regmap\n");
- return PTR_ERR(chip->regmap);
+ return PTR_ERR(regmap);
}
- ret = devm_regmap_add_irq_chip(&i2c->dev, chip->regmap,
- i2c->irq, IRQF_ONESHOT, 0,
- &bd71828_irq_chip, &irq_data);
+ ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq,
+ IRQF_ONESHOT, 0, irqchip, &irq_data);
if (ret) {
dev_err(&i2c->dev, "Failed to add IRQ chip\n");
return ret;
}
dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n",
- bd71828_irq_chip.num_irqs);
+ irqchip->num_irqs);
- ret = regmap_irq_get_virq(irq_data, BD71828_INT_SHORTPUSH);
- if (ret < 0) {
- dev_err(&i2c->dev, "Failed to get the power-key IRQ\n");
- return ret;
+ if (button_irq) {
+ ret = regmap_irq_get_virq(irq_data, button_irq);
+ if (ret < 0) {
+ dev_err(&i2c->dev, "Failed to get the power-key IRQ\n");
+ return ret;
+ }
+
+ button.irq = ret;
}
- button.irq = ret;
+ ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg);
+ if (ret)
+ return ret;
- ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
- bd71828_mfd_cells,
- ARRAY_SIZE(bd71828_mfd_cells), NULL, 0,
- regmap_irq_get_domain(irq_data));
+ ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells,
+ NULL, 0, regmap_irq_get_domain(irq_data));
if (ret)
dev_err(&i2c->dev, "Failed to create subdevices\n");
@@ -325,7 +553,13 @@ static int bd71828_i2c_probe(struct i2c_client *i2c)
}
static const struct of_device_id bd71828_of_match[] = {
- { .compatible = "rohm,bd71828", },
+ {
+ .compatible = "rohm,bd71828",
+ .data = (void *)ROHM_CHIP_TYPE_BD71828,
+ }, {
+ .compatible = "rohm,bd71815",
+ .data = (void *)ROHM_CHIP_TYPE_BD71815,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, bd71828_of_match);
diff --git a/include/linux/mfd/rohm-bd71815.h b/include/linux/mfd/rohm-bd71815.h
new file mode 100644
index 000000000000..9927aadac234
--- /dev/null
+++ b/include/linux/mfd/rohm-bd71815.h
@@ -0,0 +1,563 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *
+ * Copyright 2021 ROHM Semiconductors.
+ *
+ * Author: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
+ *
+ * Copyright 2014 Embest Technology Co. Ltd. Inc.
+ *
+ * Author: yanglsh@embest-tech.com
+ */
+
+#ifndef _MFD_BD71815_H
+#define _MFD_BD71815_H
+
+#include <linux/regmap.h>
+
+enum {
+ BD71815_BUCK1 = 0,
+ BD71815_BUCK2,
+ BD71815_BUCK3,
+ BD71815_BUCK4,
+ BD71815_BUCK5,
+ /* General Purpose */
+ BD71815_LDO1,
+ BD71815_LDO2,
+ BD71815_LDO3,
+ /* LDOs for SD Card and SD Card Interface */
+ BD71815_LDO4,
+ BD71815_LDO5,
+ /* LDO for DDR Reference Voltage */
+ BD71815_LDODVREF,
+ /* LDO for Low-Power State Retention */
+ BD71815_LDOLPSR,
+ BD71815_WLED,
+ BD71815_REGULATOR_CNT,
+};
+
+#define BD71815_SUPPLY_STATE_ENABLED 0x1
+
+enum {
+ BD71815_REG_DEVICE = 0,
+ BD71815_REG_PWRCTRL,
+ BD71815_REG_BUCK1_MODE,
+ BD71815_REG_BUCK2_MODE,
+ BD71815_REG_BUCK3_MODE,
+ BD71815_REG_BUCK4_MODE,
+ BD71815_REG_BUCK5_MODE,
+ BD71815_REG_BUCK1_VOLT_H,
+ BD71815_REG_BUCK1_VOLT_L,
+ BD71815_REG_BUCK2_VOLT_H,
+ BD71815_REG_BUCK2_VOLT_L,
+ BD71815_REG_BUCK3_VOLT,
+ BD71815_REG_BUCK4_VOLT,
+ BD71815_REG_BUCK5_VOLT,
+ BD71815_REG_LED_CTRL,
+ BD71815_REG_LED_DIMM,
+ BD71815_REG_LDO_MODE1,
+ BD71815_REG_LDO_MODE2,
+ BD71815_REG_LDO_MODE3,
+ BD71815_REG_LDO_MODE4,
+ BD71815_REG_LDO1_VOLT,
+ BD71815_REG_LDO2_VOLT,
+ BD71815_REG_LDO3_VOLT,
+ BD71815_REG_LDO4_VOLT,
+ BD71815_REG_LDO5_VOLT_H,
+ BD71815_REG_LDO5_VOLT_L,
+ BD71815_REG_BUCK_PD_DIS,
+ BD71815_REG_LDO_PD_DIS,
+ BD71815_REG_GPO,
+ BD71815_REG_OUT32K,
+ BD71815_REG_SEC,
+ BD71815_REG_MIN,
+ BD71815_REG_HOUR,
+ BD71815_REG_WEEK,
+ BD71815_REG_DAY,
+ BD71815_REG_MONTH,
+ BD71815_REG_YEAR,
+ BD71815_REG_ALM0_SEC,
+
+ BD71815_REG_ALM1_SEC = 0x2C,
+
+ BD71815_REG_ALM0_MASK = 0x33,
+ BD71815_REG_ALM1_MASK,
+ BD71815_REG_ALM2,
+ BD71815_REG_TRIM,
+ BD71815_REG_CONF,
+ BD71815_REG_SYS_INIT,
+ BD71815_REG_CHG_STATE,
+ BD71815_REG_CHG_LAST_STATE,
+ BD71815_REG_BAT_STAT,
+ BD71815_REG_DCIN_STAT,
+ BD71815_REG_VSYS_STAT,
+ BD71815_REG_CHG_STAT,
+ BD71815_REG_CHG_WDT_STAT,
+ BD71815_REG_BAT_TEMP,
+ BD71815_REG_IGNORE_0,
+ BD71815_REG_INHIBIT_0,
+ BD71815_REG_DCIN_CLPS,
+ BD71815_REG_VSYS_REG,
+ BD71815_REG_VSYS_MAX,
+ BD71815_REG_VSYS_MIN,
+ BD71815_REG_CHG_SET1,
+ BD71815_REG_CHG_SET2,
+ BD71815_REG_CHG_WDT_PRE,
+ BD71815_REG_CHG_WDT_FST,
+ BD71815_REG_CHG_IPRE,
+ BD71815_REG_CHG_IFST,
+ BD71815_REG_CHG_IFST_TERM,
+ BD71815_REG_CHG_VPRE,
+ BD71815_REG_CHG_VBAT_1,
+ BD71815_REG_CHG_VBAT_2,
+ BD71815_REG_CHG_VBAT_3,
+ BD71815_REG_CHG_LED_1,
+ BD71815_REG_VF_TH,
+ BD71815_REG_BAT_SET_1,
+ BD71815_REG_BAT_SET_2,
+ BD71815_REG_BAT_SET_3,
+ BD71815_REG_ALM_VBAT_TH_U,
+ BD71815_REG_ALM_VBAT_TH_L,
+ BD71815_REG_ALM_DCIN_TH,
+ BD71815_REG_ALM_VSYS_TH,
+ BD71815_REG_VM_IBAT_U,
+ BD71815_REG_VM_IBAT_L,
+ BD71815_REG_VM_VBAT_U,
+ BD71815_REG_VM_VBAT_L,
+ BD71815_REG_VM_BTMP,
+ BD71815_REG_VM_VTH,
+ BD71815_REG_VM_DCIN_U,
+ BD71815_REG_VM_DCIN_L,
+ BD71815_REG_VM_VSYS,
+ BD71815_REG_VM_VF,
+ BD71815_REG_VM_OCI_PRE_U,
+ BD71815_REG_VM_OCI_PRE_L,
+ BD71815_REG_VM_OCV_PRE_U,
+ BD71815_REG_VM_OCV_PRE_L,
+ BD71815_REG_VM_OCI_PST_U,
+ BD71815_REG_VM_OCI_PST_L,
+ BD71815_REG_VM_OCV_PST_U,
+ BD71815_REG_VM_OCV_PST_L,
+ BD71815_REG_VM_SA_VBAT_U,
+ BD71815_REG_VM_SA_VBAT_L,
+ BD71815_REG_VM_SA_IBAT_U,
+ BD71815_REG_VM_SA_IBAT_L,
+ BD71815_REG_CC_CTRL,
+ BD71815_REG_CC_BATCAP1_TH_U,
+ BD71815_REG_CC_BATCAP1_TH_L,
+ BD71815_REG_CC_BATCAP2_TH_U,
+ BD71815_REG_CC_BATCAP2_TH_L,
+ BD71815_REG_CC_BATCAP3_TH_U,
+ BD71815_REG_CC_BATCAP3_TH_L,
+ BD71815_REG_CC_STAT,
+ BD71815_REG_CC_CCNTD_3,
+ BD71815_REG_CC_CCNTD_2,
+ BD71815_REG_CC_CCNTD_1,
+ BD71815_REG_CC_CCNTD_0,
+ BD71815_REG_CC_CURCD_U,
+ BD71815_REG_CC_CURCD_L,
+ BD71815_REG_VM_OCUR_THR_1,
+ BD71815_REG_VM_OCUR_DUR_1,
+ BD71815_REG_VM_OCUR_THR_2,
+ BD71815_REG_VM_OCUR_DUR_2,
+ BD71815_REG_VM_OCUR_THR_3,
+ BD71815_REG_VM_OCUR_DUR_3,
+ BD71815_REG_VM_OCUR_MON,
+ BD71815_REG_VM_BTMP_OV_THR,
+ BD71815_REG_VM_BTMP_OV_DUR,
+ BD71815_REG_VM_BTMP_LO_THR,
+ BD71815_REG_VM_BTMP_LO_DUR,
+ BD71815_REG_VM_BTMP_MON,
+ BD71815_REG_INT_EN_01,
+
+ BD71815_REG_INT_EN_11 = 0x95,
+ BD71815_REG_INT_EN_12,
+ BD71815_REG_INT_STAT,
+ BD71815_REG_INT_STAT_01,
+ BD71815_REG_INT_STAT_02,
+ BD71815_REG_INT_STAT_03,
+ BD71815_REG_INT_STAT_04,
+ BD71815_REG_INT_STAT_05,
+ BD71815_REG_INT_STAT_06,
+ BD71815_REG_INT_STAT_07,
+ BD71815_REG_INT_STAT_08,
+ BD71815_REG_INT_STAT_09,
+ BD71815_REG_INT_STAT_10,
+ BD71815_REG_INT_STAT_11,
+ BD71815_REG_INT_STAT_12,
+ BD71815_REG_INT_UPDATE,
+
+ BD71815_REG_VM_VSYS_U = 0xC0,
+ BD71815_REG_VM_VSYS_L,
+ BD71815_REG_VM_SA_VSYS_U,
+ BD71815_REG_VM_SA_VSYS_L,
+
+ BD71815_REG_VM_SA_IBAT_MIN_U = 0xD0,
+ BD71815_REG_VM_SA_IBAT_MIN_L,
+ BD71815_REG_VM_SA_IBAT_MAX_U,
+ BD71815_REG_VM_SA_IBAT_MAX_L,
+ BD71815_REG_VM_SA_VBAT_MIN_U,
+ BD71815_REG_VM_SA_VBAT_MIN_L,
+ BD71815_REG_VM_SA_VBAT_MAX_U,
+ BD71815_REG_VM_SA_VBAT_MAX_L,
+ BD71815_REG_VM_SA_VSYS_MIN_U,
+ BD71815_REG_VM_SA_VSYS_MIN_L,
+ BD71815_REG_VM_SA_VSYS_MAX_U,
+ BD71815_REG_VM_SA_VSYS_MAX_L,
+ BD71815_REG_VM_SA_MINMAX_CLR,
+
+ BD71815_REG_REX_CCNTD_3 = 0xE0,
+ BD71815_REG_REX_CCNTD_2,
+ BD71815_REG_REX_CCNTD_1,
+ BD71815_REG_REX_CCNTD_0,
+ BD71815_REG_REX_SA_VBAT_U,
+ BD71815_REG_REX_SA_VBAT_L,
+ BD71815_REG_REX_CTRL_1,
+ BD71815_REG_REX_CTRL_2,
+ BD71815_REG_FULL_CCNTD_3,
+ BD71815_REG_FULL_CCNTD_2,
+ BD71815_REG_FULL_CCNTD_1,
+ BD71815_REG_FULL_CCNTD_0,
+ BD71815_REG_FULL_CTRL,
+
+ BD71815_REG_CCNTD_CHG_3 = 0xF0,
+ BD71815_REG_CCNTD_CHG_2,
+
+ BD71815_REG_TEST_MODE = 0xFE,
+ BD71815_MAX_REGISTER,
+};
+
+/* BD71815_REG_BUCK1_MODE bits */
+#define BD71815_BUCK_RAMPRATE_MASK 0xC0
+#define BD71815_BUCK_RAMPRATE_10P00MV 0x0
+#define BD71815_BUCK_RAMPRATE_5P00MV 0x01
+#define BD71815_BUCK_RAMPRATE_2P50MV 0x02
+#define BD71815_BUCK_RAMPRATE_1P25MV 0x03
+
+#define BD71815_BUCK_PWM_FIXED BIT(4)
+#define BD71815_BUCK_SNVS_ON BIT(3)
+#define BD71815_BUCK_RUN_ON BIT(2)
+#define BD71815_BUCK_LPSR_ON BIT(1)
+#define BD71815_BUCK_SUSP_ON BIT(0)
+
+/* BD71815_REG_BUCK1_VOLT_H bits */
+#define BD71815_BUCK_DVSSEL BIT(7)
+#define BD71815_BUCK_STBY_DVS BIT(6)
+#define BD71815_VOLT_MASK 0x3F
+#define BD71815_BUCK1_H_DEFAULT 0x14
+#define BD71815_BUCK1_L_DEFAULT 0x14
+
+/* BD71815_REG_BUCK2_VOLT_H bits */
+#define BD71815_BUCK2_H_DEFAULT 0x14
+#define BD71815_BUCK2_L_DEFAULT 0x14
+
+/* WLED output */
+/* current register mask */
+#define LED_DIMM_MASK 0x3f
+/* LED enable bits at LED_CTRL reg */
+#define LED_CHGDONE_EN BIT(4)
+#define LED_RUN_ON BIT(2)
+#define LED_LPSR_ON BIT(1)
+#define LED_SUSP_ON BIT(0)
+
+/* BD71815_REG_LDO1_CTRL bits */
+#define LDO1_EN BIT(0)
+#define LDO2_EN BIT(1)
+#define LDO3_EN BIT(2)
+#define DVREF_EN BIT(3)
+#define VOSNVS_SW_EN BIT(4)
+
+/* LDO_MODE1_register */
+#define LDO1_SNVS_ON BIT(7)
+#define LDO1_RUN_ON BIT(6)
+#define LDO1_LPSR_ON BIT(5)
+#define LDO1_SUSP_ON BIT(4)
+/* set => register control, unset => GPIO control */
+#define LDO4_MODE_MASK BIT(3)
+#define LDO4_MODE_I2C BIT(3)
+#define LDO4_MODE_GPIO 0
+/* set => register control, unset => start when DCIN connected */
+#define LDO3_MODE_MASK BIT(2)
+#define LDO3_MODE_I2C BIT(2)
+#define LDO3_MODE_DCIN 0
+
+/* LDO_MODE2 register */
+#define LDO3_SNVS_ON BIT(7)
+#define LDO3_RUN_ON BIT(6)
+#define LDO3_LPSR_ON BIT(5)
+#define LDO3_SUSP_ON BIT(4)
+#define LDO2_SNVS_ON BIT(3)
+#define LDO2_RUN_ON BIT(2)
+#define LDO2_LPSR_ON BIT(1)
+#define LDO2_SUSP_ON BIT(0)
+
+
+/* LDO_MODE3 register */
+#define LDO5_SNVS_ON BIT(7)
+#define LDO5_RUN_ON BIT(6)
+#define LDO5_LPSR_ON BIT(5)
+#define LDO5_SUSP_ON BIT(4)
+#define LDO4_SNVS_ON BIT(3)
+#define LDO4_RUN_ON BIT(2)
+#define LDO4_LPSR_ON BIT(1)
+#define LDO4_SUSP_ON BIT(0)
+
+/* LDO_MODE4 register */
+#define DVREF_SNVS_ON BIT(7)
+#define DVREF_RUN_ON BIT(6)
+#define DVREF_LPSR_ON BIT(5)
+#define DVREF_SUSP_ON BIT(4)
+#define LDO_LPSR_SNVS_ON BIT(3)
+#define LDO_LPSR_RUN_ON BIT(2)
+#define LDO_LPSR_LPSR_ON BIT(1)
+#define LDO_LPSR_SUSP_ON BIT(0)
+
+/* BD71815_REG_OUT32K bits */
+#define OUT32K_EN BIT(0)
+#define OUT32K_MODE BIT(1)
+#define OUT32K_MODE_CMOS BIT(1)
+#define OUT32K_MODE_OPEN_DRAIN 0
+
+/* BD71815_REG_BAT_STAT bits */
+#define BAT_DET BIT(5)
+#define BAT_DET_OFFSET 5
+#define BAT_DET_DONE BIT(4)
+#define VBAT_OV BIT(3)
+#define DBAT_DET BIT(0)
+
+/* BD71815_REG_VBUS_STAT bits */
+#define VBUS_DET BIT(0)
+
+#define BD71815_REG_RTC_START BD71815_REG_SEC
+#define BD71815_REG_RTC_ALM_START BD71815_REG_ALM0_SEC
+
+/* BD71815_REG_ALM0_MASK bits */
+#define A0_ONESEC BIT(7)
+
+/* BD71815_REG_INT_EN_00 bits */
+#define ALMALE BIT(0)
+
+/* BD71815_REG_INT_STAT_03 bits */
+#define DCIN_MON_DET BIT(1)
+#define DCIN_MON_RES BIT(0)
+#define POWERON_LONG BIT(2)
+#define POWERON_MID BIT(3)
+#define POWERON_SHORT BIT(4)
+#define POWERON_PRESS BIT(5)
+
+/* BD71805_REG_INT_STAT_08 bits */
+#define VBAT_MON_DET BIT(1)
+#define VBAT_MON_RES BIT(0)
+
+/* BD71805_REG_INT_STAT_11 bits */
+#define INT_STAT_11_VF_DET BIT(7)
+#define INT_STAT_11_VF_RES BIT(6)
+#define INT_STAT_11_VF125_DET BIT(5)
+#define INT_STAT_11_VF125_RES BIT(4)
+#define INT_STAT_11_OVTMP_DET BIT(3)
+#define INT_STAT_11_OVTMP_RES BIT(2)
+#define INT_STAT_11_LOTMP_DET BIT(1)
+#define INT_STAT_11_LOTMP_RES BIT(0)
+
+#define VBAT_MON_DET BIT(1)
+#define VBAT_MON_RES BIT(0)
+
+/* BD71815_REG_PWRCTRL bits */
+#define RESTARTEN BIT(0)
+
+/* BD71815_REG_GPO bits */
+#define READY_FORCE_LOW BIT(2)
+#define BD71815_GPIO_DRIVE_MASK BIT(4)
+#define BD71815_GPIO_OPEN_DRAIN 0
+#define BD71815_GPIO_CMOS BIT(4)
+
+/* BD71815 interrupt masks */
+enum {
+ BD71815_INT_EN_01_BUCKAST_MASK = 0x0F,
+ BD71815_INT_EN_02_DCINAST_MASK = 0x3E,
+ BD71815_INT_EN_03_DCINAST_MASK = 0x3F,
+ BD71815_INT_EN_04_VSYSAST_MASK = 0xCF,
+ BD71815_INT_EN_05_CHGAST_MASK = 0xFC,
+ BD71815_INT_EN_06_BATAST_MASK = 0xF3,
+ BD71815_INT_EN_07_BMONAST_MASK = 0xFE,
+ BD71815_INT_EN_08_BMONAST_MASK = 0x03,
+ BD71815_INT_EN_09_BMONAST_MASK = 0x07,
+ BD71815_INT_EN_10_BMONAST_MASK = 0x3F,
+ BD71815_INT_EN_11_TMPAST_MASK = 0xFF,
+ BD71815_INT_EN_12_ALMAST_MASK = 0x07,
+};
+/* BD71815 interrupt irqs */
+enum {
+ /* BUCK reg interrupts */
+ BD71815_INT_BUCK1_OCP,
+ BD71815_INT_BUCK2_OCP,
+ BD71815_INT_BUCK3_OCP,
+ BD71815_INT_BUCK4_OCP,
+ BD71815_INT_BUCK5_OCP,
+ BD71815_INT_LED_OVP,
+ BD71815_INT_LED_OCP,
+ BD71815_INT_LED_SCP,
+ /* DCIN1 interrupts */
+ BD71815_INT_DCIN_RMV,
+ BD71815_INT_CLPS_OUT,
+ BD71815_INT_CLPS_IN,
+ BD71815_INT_DCIN_OVP_RES,
+ BD71815_INT_DCIN_OVP_DET,
+ /* DCIN2 interrupts */
+ BD71815_INT_DCIN_MON_RES,
+ BD71815_INT_DCIN_MON_DET,
+ BD71815_INT_WDOG,
+ /* Vsys INT_STAT_04 */
+ BD71815_INT_VSYS_UV_RES,
+ BD71815_INT_VSYS_UV_DET,
+ BD71815_INT_VSYS_LOW_RES,
+ BD71815_INT_VSYS_LOW_DET,
+ BD71815_INT_VSYS_MON_RES,
+ BD71815_INT_VSYS_MON_DET,
+ /* Charger INT_STAT_05 */
+ BD71815_INT_CHG_WDG_TEMP,
+ BD71815_INT_CHG_WDG_TIME,
+ BD71815_INT_CHG_RECHARGE_RES,
+ BD71815_INT_CHG_RECHARGE_DET,
+ BD71815_INT_CHG_RANGED_TEMP_TRANSITION,
+ BD71815_INT_CHG_STATE_TRANSITION,
+ /* Battery INT_STAT_06 */
+ BD71815_INT_BAT_TEMP_NORMAL,
+ BD71815_INT_BAT_TEMP_ERANGE,
+ BD71815_INT_BAT_REMOVED,
+ BD71815_INT_BAT_DETECTED,
+ BD71815_INT_THERM_REMOVED,
+ BD71815_INT_THERM_DETECTED,
+ /* Battery Mon 1 INT_STAT_07 */
+ BD71815_INT_BAT_DEAD,
+ BD71815_INT_BAT_SHORTC_RES,
+ BD71815_INT_BAT_SHORTC_DET,
+ BD71815_INT_BAT_LOW_VOLT_RES,
+ BD71815_INT_BAT_LOW_VOLT_DET,
+ BD71815_INT_BAT_OVER_VOLT_RES,
+ BD71815_INT_BAT_OVER_VOLT_DET,
+ /* Battery Mon 2 INT_STAT_08 */
+ BD71815_INT_BAT_MON_RES,
+ BD71815_INT_BAT_MON_DET,
+ /* Battery Mon 3 (Coulomb counter) INT_STAT_09 */
+ BD71815_INT_BAT_CC_MON1,
+ BD71815_INT_BAT_CC_MON2,
+ BD71815_INT_BAT_CC_MON3,
+ /* Battery Mon 4 INT_STAT_10 */
+ BD71815_INT_BAT_OVER_CURR_1_RES,
+ BD71815_INT_BAT_OVER_CURR_1_DET,
+ BD71815_INT_BAT_OVER_CURR_2_RES,
+ BD71815_INT_BAT_OVER_CURR_2_DET,
+ BD71815_INT_BAT_OVER_CURR_3_RES,
+ BD71815_INT_BAT_OVER_CURR_3_DET,
+ /* Temperature INT_STAT_11 */
+ BD71815_INT_TEMP_BAT_LOW_RES,
+ BD71815_INT_TEMP_BAT_LOW_DET,
+ BD71815_INT_TEMP_BAT_HI_RES,
+ BD71815_INT_TEMP_BAT_HI_DET,
+ BD71815_INT_TEMP_CHIP_OVER_125_RES,
+ BD71815_INT_TEMP_CHIP_OVER_125_DET,
+ BD71815_INT_TEMP_CHIP_OVER_VF_RES,
+ BD71815_INT_TEMP_CHIP_OVER_VF_DET,
+ /* RTC Alarm INT_STAT_12 */
+ BD71815_INT_RTC0,
+ BD71815_INT_RTC1,
+ BD71815_INT_RTC2,
+};
+
+#define BD71815_INT_BUCK1_OCP_MASK BIT(0)
+#define BD71815_INT_BUCK2_OCP_MASK BIT(1)
+#define BD71815_INT_BUCK3_OCP_MASK BIT(2)
+#define BD71815_INT_BUCK4_OCP_MASK BIT(3)
+#define BD71815_INT_BUCK5_OCP_MASK BIT(4)
+#define BD71815_INT_LED_OVP_MASK BIT(5)
+#define BD71815_INT_LED_OCP_MASK BIT(6)
+#define BD71815_INT_LED_SCP_MASK BIT(7)
+
+#define BD71815_INT_DCIN_RMV_MASK BIT(1)
+#define BD71815_INT_CLPS_OUT_MASK BIT(2)
+#define BD71815_INT_CLPS_IN_MASK BIT(3)
+#define BD71815_INT_DCIN_OVP_RES_MASK BIT(4)
+#define BD71815_INT_DCIN_OVP_DET_MASK BIT(5)
+
+#define BD71815_INT_DCIN_MON_RES_MASK BIT(0)
+#define BD71815_INT_DCIN_MON_DET_MASK BIT(1)
+#define BD71815_INT_WDOG_MASK BIT(6)
+
+#define BD71815_INT_VSYS_UV_RES_MASK BIT(0)
+#define BD71815_INT_VSYS_UV_DET_MASK BIT(1)
+#define BD71815_INT_VSYS_LOW_RES_MASK BIT(2)
+#define BD71815_INT_VSYS_LOW_DET_MASK BIT(3)
+#define BD71815_INT_VSYS_MON_RES_MASK BIT(6)
+#define BD71815_INT_VSYS_MON_DET_MASK BIT(7)
+
+#define BD71815_INT_CHG_WDG_TEMP_MASK BIT(2)
+#define BD71815_INT_CHG_WDG_TIME_MASK BIT(3)
+#define BD71815_INT_CHG_RECHARGE_RES_MASK BIT(4)
+#define BD71815_INT_CHG_RECHARGE_DET_MASK BIT(5)
+#define BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK BIT(6)
+#define BD71815_INT_CHG_STATE_TRANSITION_MASK BIT(7)
+
+#define BD71815_INT_BAT_TEMP_NORMAL_MASK BIT(0)
+#define BD71815_INT_BAT_TEMP_ERANGE_MASK BIT(1)
+#define BD71815_INT_BAT_REMOVED_MASK BIT(4)
+#define BD71815_INT_BAT_DETECTED_MASK BIT(5)
+#define BD71815_INT_THERM_REMOVED_MASK BIT(6)
+#define BD71815_INT_THERM_DETECTED_MASK BIT(7)
+
+#define BD71815_INT_BAT_DEAD_MASK BIT(1)
+#define BD71815_INT_BAT_SHORTC_RES_MASK BIT(2)
+#define BD71815_INT_BAT_SHORTC_DET_MASK BIT(3)
+#define BD71815_INT_BAT_LOW_VOLT_RES_MASK BIT(4)
+#define BD71815_INT_BAT_LOW_VOLT_DET_MASK BIT(5)
+#define BD71815_INT_BAT_OVER_VOLT_RES_MASK BIT(6)
+#define BD71815_INT_BAT_OVER_VOLT_DET_MASK BIT(7)
+
+#define BD71815_INT_BAT_MON_RES_MASK BIT(0)
+#define BD71815_INT_BAT_MON_DET_MASK BIT(1)
+
+#define BD71815_INT_BAT_CC_MON1_MASK BIT(0)
+#define BD71815_INT_BAT_CC_MON2_MASK BIT(1)
+#define BD71815_INT_BAT_CC_MON3_MASK BIT(2)
+
+#define BD71815_INT_BAT_OVER_CURR_1_RES_MASK BIT(0)
+#define BD71815_INT_BAT_OVER_CURR_1_DET_MASK BIT(1)
+#define BD71815_INT_BAT_OVER_CURR_2_RES_MASK BIT(2)
+#define BD71815_INT_BAT_OVER_CURR_2_DET_MASK BIT(3)
+#define BD71815_INT_BAT_OVER_CURR_3_RES_MASK BIT(4)
+#define BD71815_INT_BAT_OVER_CURR_3_DET_MASK BIT(5)
+
+#define BD71815_INT_TEMP_BAT_LOW_RES_MASK BIT(0)
+#define BD71815_INT_TEMP_BAT_LOW_DET_MASK BIT(1)
+#define BD71815_INT_TEMP_BAT_HI_RES_MASK BIT(2)
+#define BD71815_INT_TEMP_BAT_HI_DET_MASK BIT(3)
+#define BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK BIT(4)
+#define BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK BIT(5)
+#define BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK BIT(6)
+#define BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK BIT(7)
+
+#define BD71815_INT_RTC0_MASK BIT(0)
+#define BD71815_INT_RTC1_MASK BIT(1)
+#define BD71815_INT_RTC2_MASK BIT(2)
+
+/* BD71815_REG_CC_CTRL bits */
+#define CCNTRST 0x80
+#define CCNTENB 0x40
+#define CCCALIB 0x20
+
+/* BD71815_REG_CC_CURCD */
+#define CURDIR_Discharging 0x8000
+
+/* BD71815_REG_VM_SA_IBAT */
+#define IBAT_SA_DIR_Discharging 0x8000
+
+/* BD71815_REG_REX_CTRL_1 bits */
+#define REX_CLR BIT(4)
+
+/* BD71815_REG_REX_CTRL_1 bits */
+#define REX_PMU_STATE_MASK BIT(2)
+
+/* BD71815_REG_LED_CTRL bits */
+#define CHGDONE_LED_EN BIT(4)
+
+#endif /* __LINUX_MFD_BD71815_H */
diff --git a/include/linux/mfd/rohm-bd71828.h b/include/linux/mfd/rohm-bd71828.h
index 017a4c01cb31..c7ab69c87ee8 100644
--- a/include/linux/mfd/rohm-bd71828.h
+++ b/include/linux/mfd/rohm-bd71828.h
@@ -151,6 +151,9 @@ enum {
#define BD71828_REG_GPIO_CTRL3 0x49
#define BD71828_REG_IO_STAT 0xed
+/* clk */
+#define BD71828_REG_OUT32K 0x4b
+
/* RTC */
#define BD71828_REG_RTC_SEC 0x4c
#define BD71828_REG_RTC_MINUTE 0x4d
--
2.25.4
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 14/15] rtc: bd70528: Support RTC on ROHM BD71815
2021-03-08 10:39 [PATCH v3 00/15] Support ROHM BD71815 PMIC Matti Vaittinen
` (2 preceding siblings ...)
2021-03-08 10:42 ` [PATCH v3 07/15] mfd: Support for ROHM BD71815 PMIC core Matti Vaittinen
@ 2021-03-08 10:45 ` Matti Vaittinen
2021-03-08 10:45 ` [PATCH v3 15/15] MAINTAINERS: Add ROHM BD71815AGW Matti Vaittinen
4 siblings, 0 replies; 14+ messages in thread
From: Matti Vaittinen @ 2021-03-08 10:45 UTC (permalink / raw)
To: matti.vaittinen, mazziesaccount
Cc: Lee Jones, Matti Vaittinen, Alessandro Zummo, Alexandre Belloni,
linux-kernel, linux-power, linux-rtc
BD71815 contains similar RTC block as BD71828. Only the address offsets
seem different. Support also BD71815 RTC using rtc-bd70528.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
drivers/rtc/Kconfig | 6 +++---
drivers/rtc/rtc-bd70528.c | 45 ++++++++++++++++++++++++++++++++-------
2 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index ce723dc54aa4..622af1314ece 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -501,11 +501,11 @@ config RTC_DRV_M41T80_WDT
watchdog timer in the ST M41T60 and M41T80 RTC chips series.
config RTC_DRV_BD70528
- tristate "ROHM BD70528 PMIC RTC"
- depends on MFD_ROHM_BD70528 && (BD70528_WATCHDOG || !BD70528_WATCHDOG)
+ tristate "ROHM BD70528, BD71815 and BD71828 PMIC RTC"
+ depends on MFD_ROHM_BD71828 || MFD_ROHM_BD70528 && (BD70528_WATCHDOG || !BD70528_WATCHDOG)
help
If you say Y here you will get support for the RTC
- block on ROHM BD70528 and BD71828 Power Management IC.
+ block on ROHM BD70528, BD71815 and BD71828 Power Management IC.
This driver can also be built as a module. If so, the module
will be called rtc-bd70528.
diff --git a/drivers/rtc/rtc-bd70528.c b/drivers/rtc/rtc-bd70528.c
index fb4476bb5ab6..6454afca02a6 100644
--- a/drivers/rtc/rtc-bd70528.c
+++ b/drivers/rtc/rtc-bd70528.c
@@ -6,6 +6,7 @@
#include <linux/bcd.h>
#include <linux/mfd/rohm-bd70528.h>
+#include <linux/mfd/rohm-bd71815.h>
#include <linux/mfd/rohm-bd71828.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -13,6 +14,12 @@
#include <linux/regmap.h>
#include <linux/rtc.h>
+/*
+ * On BD71828 and BD71815 the ALM0 MASK is 14 bytes after the ALM0
+ * block start
+ */
+#define BD718XX_ALM_EN_OFFSET 14
+
/*
* We read regs RTC_SEC => RTC_YEAR
* this struct is ordered according to chip registers.
@@ -55,6 +62,7 @@ struct bd70528_rtc {
struct regmap *regmap;
struct device *dev;
u8 reg_time_start;
+ u8 bd718xx_alm_block_start;
bool has_rtc_timers;
};
@@ -236,8 +244,8 @@ static int bd71828_set_alarm(struct device *dev, struct rtc_wkalrm *a)
struct bd71828_rtc_alm alm;
struct bd70528_rtc *r = dev_get_drvdata(dev);
- ret = regmap_bulk_read(r->regmap, BD71828_REG_RTC_ALM_START,
- &alm, sizeof(alm));
+ ret = regmap_bulk_read(r->regmap, r->bd718xx_alm_block_start, &alm,
+ sizeof(alm));
if (ret) {
dev_err(dev, "Failed to read alarm regs\n");
return ret;
@@ -250,8 +258,8 @@ static int bd71828_set_alarm(struct device *dev, struct rtc_wkalrm *a)
else
alm.alm_mask |= BD70528_MASK_ALM_EN;
- ret = regmap_bulk_write(r->regmap, BD71828_REG_RTC_ALM_START,
- &alm, sizeof(alm));
+ ret = regmap_bulk_write(r->regmap, r->bd718xx_alm_block_start, &alm,
+ sizeof(alm));
if (ret)
dev_err(dev, "Failed to set alarm time\n");
@@ -311,8 +319,8 @@ static int bd71828_read_alarm(struct device *dev, struct rtc_wkalrm *a)
struct bd71828_rtc_alm alm;
struct bd70528_rtc *r = dev_get_drvdata(dev);
- ret = regmap_bulk_read(r->regmap, BD71828_REG_RTC_ALM_START,
- &alm, sizeof(alm));
+ ret = regmap_bulk_read(r->regmap, r->bd718xx_alm_block_start, &alm,
+ sizeof(alm));
if (ret) {
dev_err(dev, "Failed to read alarm regs\n");
return ret;
@@ -453,8 +461,9 @@ static int bd71828_alm_enable(struct device *dev, unsigned int enabled)
if (!enabled)
enableval = 0;
- ret = regmap_update_bits(r->regmap, BD71828_REG_RTC_ALM0_MASK,
- BD70528_MASK_ALM_EN, enableval);
+ ret = regmap_update_bits(r->regmap, r->bd718xx_alm_block_start +
+ BD718XX_ALM_EN_OFFSET, BD70528_MASK_ALM_EN,
+ enableval);
if (ret)
dev_err(dev, "Failed to change alarm state\n");
@@ -524,9 +533,28 @@ static int bd70528_probe(struct platform_device *pdev)
enable_main_irq = true;
rtc_ops = &bd70528_rtc_ops;
break;
+ case ROHM_CHIP_TYPE_BD71815:
+ irq_name = "bd71815-rtc-alm-0";
+ bd_rtc->reg_time_start = BD71815_REG_RTC_START;
+
+ /*
+ * See also BD718XX_ALM_EN_OFFSET:
+ * This works for BD71828 and BD71815 as they have same offset
+ * between ALM0 start and ALM0_MASK. If new ICs are to be
+ * added this requires proper check as ALM0_MASK is not located
+ * at the end of ALM0 block - but after all ALM blocks so if
+ * amount of ALMs differ the offset to enable/disable is likely
+ * to be incorrect and enable/disable must be given as own
+ * reg address here.
+ */
+ bd_rtc->bd718xx_alm_block_start = BD71815_REG_RTC_ALM_START;
+ hour_reg = BD71815_REG_HOUR;
+ rtc_ops = &bd71828_rtc_ops;
+ break;
case ROHM_CHIP_TYPE_BD71828:
irq_name = "bd71828-rtc-alm-0";
bd_rtc->reg_time_start = BD71828_REG_RTC_START;
+ bd_rtc->bd718xx_alm_block_start = BD71828_REG_RTC_ALM_START;
hour_reg = BD71828_REG_RTC_HOUR;
rtc_ops = &bd71828_rtc_ops;
break;
@@ -605,6 +633,7 @@ static int bd70528_probe(struct platform_device *pdev)
static const struct platform_device_id bd718x7_rtc_id[] = {
{ "bd70528-rtc", ROHM_CHIP_TYPE_BD70528 },
{ "bd71828-rtc", ROHM_CHIP_TYPE_BD71828 },
+ { "bd71815-rtc", ROHM_CHIP_TYPE_BD71815 },
{ },
};
MODULE_DEVICE_TABLE(platform, bd718x7_rtc_id);
--
2.25.4
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v3 15/15] MAINTAINERS: Add ROHM BD71815AGW
2021-03-08 10:39 [PATCH v3 00/15] Support ROHM BD71815 PMIC Matti Vaittinen
` (3 preceding siblings ...)
2021-03-08 10:45 ` [PATCH v3 14/15] rtc: bd70528: Support RTC on ROHM BD71815 Matti Vaittinen
@ 2021-03-08 10:45 ` Matti Vaittinen
4 siblings, 0 replies; 14+ messages in thread
From: Matti Vaittinen @ 2021-03-08 10:45 UTC (permalink / raw)
To: matti.vaittinen, mazziesaccount
Cc: Lee Jones, Rob Herring, Liam Girdwood, Mark Brown,
Matti Vaittinen, Michael Turquette, Stephen Boyd, Linus Walleij,
Bartosz Golaszewski, Alessandro Zummo, Alexandre Belloni,
devicetree, linux-kernel, linux-power, linux-clk, linux-gpio,
linux-rtc
Add maintainer entries for ROHM BD71815AGW drivers.
New regulator and GPIO drivers were introduced for these PMICs.
Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..ac6eb095ab0c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15452,18 +15452,21 @@ F: Documentation/devicetree/bindings/mfd/rohm,bd70528-pmic.txt
F: Documentation/devicetree/bindings/regulator/rohm,bd70528-regulator.txt
F: drivers/clk/clk-bd718x7.c
F: drivers/gpio/gpio-bd70528.c
+F: drivers/gpio/gpio-bd71815.c
F: drivers/gpio/gpio-bd71828.c
F: drivers/mfd/rohm-bd70528.c
F: drivers/mfd/rohm-bd71828.c
F: drivers/mfd/rohm-bd718x7.c
F: drivers/power/supply/bd70528-charger.c
F: drivers/regulator/bd70528-regulator.c
+F: drivers/regulator/bd71815-regulator.c
F: drivers/regulator/bd71828-regulator.c
F: drivers/regulator/bd718x7-regulator.c
F: drivers/regulator/rohm-regulator.c
F: drivers/rtc/rtc-bd70528.c
F: drivers/watchdog/bd70528_wdt.c
F: include/linux/mfd/rohm-bd70528.h
+F: include/linux/mfd/rohm-bd71815.h
F: include/linux/mfd/rohm-bd71828.h
F: include/linux/mfd/rohm-bd718x7.h
F: include/linux/mfd/rohm-generic.h
--
2.25.4
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~
Thanks to Simon Glass for the translation =]
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v3 06/15] mfd: Add ROHM BD71815 ID
2021-03-08 10:41 ` [PATCH v3 06/15] mfd: Add ROHM BD71815 ID Matti Vaittinen
@ 2021-03-10 10:36 ` Lee Jones
2021-03-10 11:07 ` Vaittinen, Matti
0 siblings, 1 reply; 14+ messages in thread
From: Lee Jones @ 2021-03-10 10:36 UTC (permalink / raw)
To: Matti Vaittinen
Cc: mazziesaccount, linux-kernel, linux-power, linux-clk, linux-gpio,
linux-rtc
On Mon, 08 Mar 2021, Matti Vaittinen wrote:
> Add chip ID for ROHM BD71815 and PMIC so that drivers can identify
> this IC.
>
> Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> ---
> include/linux/mfd/rohm-generic.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h
> index 66f673c35303..e5392bcbc098 100644
> --- a/include/linux/mfd/rohm-generic.h
> +++ b/include/linux/mfd/rohm-generic.h
> @@ -14,6 +14,7 @@ enum rohm_chip_type {
> ROHM_CHIP_TYPE_BD71828,
> ROHM_CHIP_TYPE_BD9571,
> ROHM_CHIP_TYPE_BD9574,
> + ROHM_CHIP_TYPE_BD71815,
Is there a technical reason why these can't be re-ordered?
> ROHM_CHIP_TYPE_AMOUNT
> };
>
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 07/15] mfd: Support for ROHM BD71815 PMIC core
2021-03-08 10:42 ` [PATCH v3 07/15] mfd: Support for ROHM BD71815 PMIC core Matti Vaittinen
@ 2021-03-10 10:40 ` Lee Jones
0 siblings, 0 replies; 14+ messages in thread
From: Lee Jones @ 2021-03-10 10:40 UTC (permalink / raw)
To: Matti Vaittinen
Cc: mazziesaccount, Rob Herring, Liam Girdwood, Mark Brown,
Michael Turquette, Stephen Boyd, Linus Walleij,
Bartosz Golaszewski, Alessandro Zummo, Alexandre Belloni,
devicetree, linux-kernel, linux-power, linux-clk, linux-gpio,
linux-rtc
On Mon, 08 Mar 2021, Matti Vaittinen wrote:
> Add core support for ROHM BD71815 Power Management IC.
>
> The IC integrates regulators, a battery charger with a coulomb counter,
> a real-time clock (RTC), clock gate and general-purpose outputs (GPO).
>
> Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
> ---
> Changes since v2:
> - styling / clean-ups suggested by Lee
> - corrected clk-mode dt property values to match changed bindings
>
> drivers/mfd/Kconfig | 15 +-
> drivers/mfd/rohm-bd71828.c | 486 +++++++++++++++++++-------
> include/linux/mfd/rohm-bd71815.h | 563 +++++++++++++++++++++++++++++++
> include/linux/mfd/rohm-bd71828.h | 3 +
> 4 files changed, 934 insertions(+), 133 deletions(-)
> create mode 100644 include/linux/mfd/rohm-bd71815.h
[...]
> diff --git a/include/linux/mfd/rohm-bd71815.h b/include/linux/mfd/rohm-bd71815.h
> new file mode 100644
> index 000000000000..9927aadac234
> --- /dev/null
> +++ b/include/linux/mfd/rohm-bd71815.h
> @@ -0,0 +1,563 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + *
Nit: If you rework this for any reason, please remove this line.
For my own reference (apply this as-is to your sign-off block):
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 06/15] mfd: Add ROHM BD71815 ID
2021-03-10 10:36 ` Lee Jones
@ 2021-03-10 11:07 ` Vaittinen, Matti
2021-03-10 11:17 ` Lee Jones
0 siblings, 1 reply; 14+ messages in thread
From: Vaittinen, Matti @ 2021-03-10 11:07 UTC (permalink / raw)
To: lee.jones; +Cc: linux-power, linux-gpio, linux-clk, linux-kernel, linux-rtc
Hello Lee,
On Wed, 2021-03-10 at 10:36 +0000, Lee Jones wrote:
> On Mon, 08 Mar 2021, Matti Vaittinen wrote:
>
> > Add chip ID for ROHM BD71815 and PMIC so that drivers can identify
> > this IC.
> >
> > Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
> > Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > include/linux/mfd/rohm-generic.h | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/include/linux/mfd/rohm-generic.h
> > b/include/linux/mfd/rohm-generic.h
> > index 66f673c35303..e5392bcbc098 100644
> > --- a/include/linux/mfd/rohm-generic.h
> > +++ b/include/linux/mfd/rohm-generic.h
> > @@ -14,6 +14,7 @@ enum rohm_chip_type {
> > ROHM_CHIP_TYPE_BD71828,
> > ROHM_CHIP_TYPE_BD9571,
> > ROHM_CHIP_TYPE_BD9574,
> > + ROHM_CHIP_TYPE_BD71815,
>
> Is there a technical reason why these can't be re-ordered?
No, I don't think so.
BTW. there will probably be a (trivial) conflict here as both this
series and the BD9576/BD9573 series add an ID here. Let me guess, you'd
like to see them sorted?
>
> > ROHM_CHIP_TYPE_AMOUNT
> > };
> >
Br,
Matti Vaittinen
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 06/15] mfd: Add ROHM BD71815 ID
2021-03-10 11:07 ` Vaittinen, Matti
@ 2021-03-10 11:17 ` Lee Jones
2021-03-10 13:02 ` Matti Vaittinen
0 siblings, 1 reply; 14+ messages in thread
From: Lee Jones @ 2021-03-10 11:17 UTC (permalink / raw)
To: Vaittinen, Matti
Cc: linux-power, linux-gpio, linux-clk, linux-kernel, linux-rtc
On Wed, 10 Mar 2021, Vaittinen, Matti wrote:
> Hello Lee,
>
> On Wed, 2021-03-10 at 10:36 +0000, Lee Jones wrote:
> > On Mon, 08 Mar 2021, Matti Vaittinen wrote:
> >
> > > Add chip ID for ROHM BD71815 and PMIC so that drivers can identify
> > > this IC.
> > >
> > > Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
> > > Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> > > ---
> > > include/linux/mfd/rohm-generic.h | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/include/linux/mfd/rohm-generic.h
> > > b/include/linux/mfd/rohm-generic.h
> > > index 66f673c35303..e5392bcbc098 100644
> > > --- a/include/linux/mfd/rohm-generic.h
> > > +++ b/include/linux/mfd/rohm-generic.h
> > > @@ -14,6 +14,7 @@ enum rohm_chip_type {
> > > ROHM_CHIP_TYPE_BD71828,
> > > ROHM_CHIP_TYPE_BD9571,
> > > ROHM_CHIP_TYPE_BD9574,
> > > + ROHM_CHIP_TYPE_BD71815,
> >
> > Is there a technical reason why these can't be re-ordered?
>
> No, I don't think so.
>
> BTW. there will probably be a (trivial) conflict here as both this
> series and the BD9576/BD9573 series add an ID here. Let me guess, you'd
That's fine. I will resolve that manually.
> like to see them sorted?
Wouldn't that be nice? :)
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 06/15] mfd: Add ROHM BD71815 ID
2021-03-10 11:17 ` Lee Jones
@ 2021-03-10 13:02 ` Matti Vaittinen
2021-03-10 13:31 ` Lee Jones
0 siblings, 1 reply; 14+ messages in thread
From: Matti Vaittinen @ 2021-03-10 13:02 UTC (permalink / raw)
To: Lee Jones; +Cc: linux-power, linux-gpio, linux-clk, linux-kernel, linux-rtc
On Wed, 2021-03-10 at 11:17 +0000, Lee Jones wrote:
> On Wed, 10 Mar 2021, Vaittinen, Matti wrote:
>
> > Hello Lee,
> >
> > On Wed, 2021-03-10 at 10:36 +0000, Lee Jones wrote:
> > > On Mon, 08 Mar 2021, Matti Vaittinen wrote:
> > >
> > > > Add chip ID for ROHM BD71815 and PMIC so that drivers can
> > > > identify
> > > > this IC.
> > > >
> > > > Signed-off-by: Matti Vaittinen <
> > > > matti.vaittinen@fi.rohmeurope.com>
> > > > Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> > > > ---
> > > > include/linux/mfd/rohm-generic.h | 1 +
> > > > 1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/include/linux/mfd/rohm-generic.h
> > > > b/include/linux/mfd/rohm-generic.h
> > > > index 66f673c35303..e5392bcbc098 100644
> > > > --- a/include/linux/mfd/rohm-generic.h
> > > > +++ b/include/linux/mfd/rohm-generic.h
> > > > @@ -14,6 +14,7 @@ enum rohm_chip_type {
> > > > ROHM_CHIP_TYPE_BD71828,
> > > > ROHM_CHIP_TYPE_BD9571,
> > > > ROHM_CHIP_TYPE_BD9574,
> > > > + ROHM_CHIP_TYPE_BD71815,
> > >
> > > Is there a technical reason why these can't be re-ordered?
> >
> > No, I don't think so.
> >
> > BTW. there will probably be a (trivial) conflict here as both this
> > series and the BD9576/BD9573 series add an ID here. Let me guess,
> > you'd
>
> That's fine. I will resolve that manually.
Thanks :)
>
> > like to see them sorted?
>
> Wouldn't that be nice? :)
Aesthetics is not really my cup of tea. OTOH, if amount of IDs grow,
then sorting helps spotting whether some IC has an ID here. So yes, it
kind of makes sense.
Can you do sorting while resolving the conflict between series or do
you want me to
a) do sorting if (when) I re-spin the series
b) send separate sorting patch as a part of this series
c) send sepatate sorting patch after all the pending patches touching
these IDs have been merged?
--Matti
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 06/15] mfd: Add ROHM BD71815 ID
2021-03-10 13:02 ` Matti Vaittinen
@ 2021-03-10 13:31 ` Lee Jones
2021-03-10 14:39 ` Matti Vaittinen
0 siblings, 1 reply; 14+ messages in thread
From: Lee Jones @ 2021-03-10 13:31 UTC (permalink / raw)
To: Matti Vaittinen
Cc: linux-power, linux-gpio, linux-clk, linux-kernel, linux-rtc
On Wed, 10 Mar 2021, Matti Vaittinen wrote:
> On Wed, 2021-03-10 at 11:17 +0000, Lee Jones wrote:
> > On Wed, 10 Mar 2021, Vaittinen, Matti wrote:
> >
> > > Hello Lee,
> > >
> > > On Wed, 2021-03-10 at 10:36 +0000, Lee Jones wrote:
> > > > On Mon, 08 Mar 2021, Matti Vaittinen wrote:
> > > >
> > > > > Add chip ID for ROHM BD71815 and PMIC so that drivers can
> > > > > identify
> > > > > this IC.
> > > > >
> > > > > Signed-off-by: Matti Vaittinen <
> > > > > matti.vaittinen@fi.rohmeurope.com>
> > > > > Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> > > > > ---
> > > > > include/linux/mfd/rohm-generic.h | 1 +
> > > > > 1 file changed, 1 insertion(+)
> > > > >
> > > > > diff --git a/include/linux/mfd/rohm-generic.h
> > > > > b/include/linux/mfd/rohm-generic.h
> > > > > index 66f673c35303..e5392bcbc098 100644
> > > > > --- a/include/linux/mfd/rohm-generic.h
> > > > > +++ b/include/linux/mfd/rohm-generic.h
> > > > > @@ -14,6 +14,7 @@ enum rohm_chip_type {
> > > > > ROHM_CHIP_TYPE_BD71828,
> > > > > ROHM_CHIP_TYPE_BD9571,
> > > > > ROHM_CHIP_TYPE_BD9574,
> > > > > + ROHM_CHIP_TYPE_BD71815,
> > > >
> > > > Is there a technical reason why these can't be re-ordered?
> > >
> > > No, I don't think so.
> > >
> > > BTW. there will probably be a (trivial) conflict here as both this
> > > series and the BD9576/BD9573 series add an ID here. Let me guess,
> > > you'd
> >
> > That's fine. I will resolve that manually.
>
> Thanks :)
>
> >
> > > like to see them sorted?
> >
> > Wouldn't that be nice? :)
> Aesthetics is not really my cup of tea. OTOH, if amount of IDs grow,
> then sorting helps spotting whether some IC has an ID here. So yes, it
> kind of makes sense.
By 'nice' I don't mean 'pretty'.
I mean 'improving readability/maintainability would be nice'.
> Can you do sorting while resolving the conflict between series or do
> you want me to
> a) do sorting if (when) I re-spin the series
> b) send separate sorting patch as a part of this series
> c) send sepatate sorting patch after all the pending patches touching
> these IDs have been merged?
I'll let you use your imagination.
I just noticed that the latest entry did not fit well inside the
current list. Why don't you start by putting that in the list where
it makes the most sense i.e. somewhere near ROHM_CHIP_TYPE_BD71828,
and see how you get on.
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 06/15] mfd: Add ROHM BD71815 ID
2021-03-10 13:31 ` Lee Jones
@ 2021-03-10 14:39 ` Matti Vaittinen
2021-03-10 16:38 ` Lee Jones
0 siblings, 1 reply; 14+ messages in thread
From: Matti Vaittinen @ 2021-03-10 14:39 UTC (permalink / raw)
To: Lee Jones; +Cc: linux-power, linux-gpio, linux-clk, linux-kernel, linux-rtc
On Wed, 2021-03-10 at 13:31 +0000, Lee Jones wrote:
> On Wed, 10 Mar 2021, Matti Vaittinen wrote:
>
> > On Wed, 2021-03-10 at 11:17 +0000, Lee Jones wrote:
> > > On Wed, 10 Mar 2021, Vaittinen, Matti wrote:
> > >
> > > > Hello Lee,
> > > >
> > > > On Wed, 2021-03-10 at 10:36 +0000, Lee Jones wrote:
> > > > > On Mon, 08 Mar 2021, Matti Vaittinen wrote:
> > > > >
> > > > > > Add chip ID for ROHM BD71815 and PMIC so that drivers can
> > > > > > identify
> > > > > > this IC.
> > > > > >
> > > > > > Signed-off-by: Matti Vaittinen <
> > > > > > matti.vaittinen@fi.rohmeurope.com>
> > > > > > Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> > > > > > ---
> > > > > > include/linux/mfd/rohm-generic.h | 1 +
> > > > > > 1 file changed, 1 insertion(+)
> > > > > >
> > > > > > diff --git a/include/linux/mfd/rohm-generic.h
> > > > > > b/include/linux/mfd/rohm-generic.h
> > > > > > index 66f673c35303..e5392bcbc098 100644
> > > > > > --- a/include/linux/mfd/rohm-generic.h
> > > > > > +++ b/include/linux/mfd/rohm-generic.h
> > > > > > @@ -14,6 +14,7 @@ enum rohm_chip_type {
> > > > > > ROHM_CHIP_TYPE_BD71828,
> > > > > > ROHM_CHIP_TYPE_BD9571,
> > > > > > ROHM_CHIP_TYPE_BD9574,
> > > > > > + ROHM_CHIP_TYPE_BD71815,
> > > > >
> > > > > Is there a technical reason why these can't be re-ordered?
> > > >
> > > > No, I don't think so.
> > > >
> > > > BTW. there will probably be a (trivial) conflict here as both
> > > > this
> > > > series and the BD9576/BD9573 series add an ID here. Let me
> > > > guess,
> > > > you'd
> > >
> > > That's fine. I will resolve that manually.
> >
> > Thanks :)
> >
> > > > like to see them sorted?
> > >
> > > Wouldn't that be nice? :)
> > Aesthetics is not really my cup of tea. OTOH, if amount of IDs
> > grow,
> > then sorting helps spotting whether some IC has an ID here. So yes,
> > it
> > kind of makes sense.
>
> By 'nice' I don't mean 'pretty'.
>
> I mean 'improving readability/maintainability would be nice'.
>
> > Can you do sorting while resolving the conflict between series or
> > do
> > you want me to
> > a) do sorting if (when) I re-spin the series
> > b) send separate sorting patch as a part of this series
> > c) send sepatate sorting patch after all the pending patches
> > touching
> > these IDs have been merged?
>
> I'll let you use your imagination.
>
Right :)
I'll sort the ID enum when I respin a series which is touching it, ok?
Or do you want me to resend this even if there were no other changes?
It's just an old habit to add new enums at the bottom to maintain
binary compatibility - which does not matter in this case.
Br,
Matti Vaittinen
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v3 06/15] mfd: Add ROHM BD71815 ID
2021-03-10 14:39 ` Matti Vaittinen
@ 2021-03-10 16:38 ` Lee Jones
0 siblings, 0 replies; 14+ messages in thread
From: Lee Jones @ 2021-03-10 16:38 UTC (permalink / raw)
To: Matti Vaittinen
Cc: linux-power, linux-gpio, linux-clk, linux-kernel, linux-rtc
On Wed, 10 Mar 2021, Matti Vaittinen wrote:
>
> On Wed, 2021-03-10 at 13:31 +0000, Lee Jones wrote:
> > On Wed, 10 Mar 2021, Matti Vaittinen wrote:
> >
> > > On Wed, 2021-03-10 at 11:17 +0000, Lee Jones wrote:
> > > > On Wed, 10 Mar 2021, Vaittinen, Matti wrote:
> > > >
> > > > > Hello Lee,
> > > > >
> > > > > On Wed, 2021-03-10 at 10:36 +0000, Lee Jones wrote:
> > > > > > On Mon, 08 Mar 2021, Matti Vaittinen wrote:
> > > > > >
> > > > > > > Add chip ID for ROHM BD71815 and PMIC so that drivers can
> > > > > > > identify
> > > > > > > this IC.
> > > > > > >
> > > > > > > Signed-off-by: Matti Vaittinen <
> > > > > > > matti.vaittinen@fi.rohmeurope.com>
> > > > > > > Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> > > > > > > ---
> > > > > > > include/linux/mfd/rohm-generic.h | 1 +
> > > > > > > 1 file changed, 1 insertion(+)
> > > > > > >
> > > > > > > diff --git a/include/linux/mfd/rohm-generic.h
> > > > > > > b/include/linux/mfd/rohm-generic.h
> > > > > > > index 66f673c35303..e5392bcbc098 100644
> > > > > > > --- a/include/linux/mfd/rohm-generic.h
> > > > > > > +++ b/include/linux/mfd/rohm-generic.h
> > > > > > > @@ -14,6 +14,7 @@ enum rohm_chip_type {
> > > > > > > ROHM_CHIP_TYPE_BD71828,
> > > > > > > ROHM_CHIP_TYPE_BD9571,
> > > > > > > ROHM_CHIP_TYPE_BD9574,
> > > > > > > + ROHM_CHIP_TYPE_BD71815,
> > > > > >
> > > > > > Is there a technical reason why these can't be re-ordered?
> > > > >
> > > > > No, I don't think so.
> > > > >
> > > > > BTW. there will probably be a (trivial) conflict here as both
> > > > > this
> > > > > series and the BD9576/BD9573 series add an ID here. Let me
> > > > > guess,
> > > > > you'd
> > > >
> > > > That's fine. I will resolve that manually.
> > >
> > > Thanks :)
> > >
> > > > > like to see them sorted?
> > > >
> > > > Wouldn't that be nice? :)
> > > Aesthetics is not really my cup of tea. OTOH, if amount of IDs
> > > grow,
> > > then sorting helps spotting whether some IC has an ID here. So yes,
> > > it
> > > kind of makes sense.
> >
> > By 'nice' I don't mean 'pretty'.
> >
> > I mean 'improving readability/maintainability would be nice'.
> >
> > > Can you do sorting while resolving the conflict between series or
> > > do
> > > you want me to
> > > a) do sorting if (when) I re-spin the series
> > > b) send separate sorting patch as a part of this series
> > > c) send sepatate sorting patch after all the pending patches
> > > touching
> > > these IDs have been merged?
> >
> > I'll let you use your imagination.
> >
>
> Right :)
>
> I'll sort the ID enum when I respin a series which is touching it, ok?
> Or do you want me to resend this even if there were no other changes?
>
> It's just an old habit to add new enums at the bottom to maintain
> binary compatibility - which does not matter in this case.
I won't let this alone hold up merging of the whole set, but it looks
like you're still short of quite a few reviews. I'd be surprised if
it's this version that gets applied.
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-03-10 16:39 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-08 10:39 [PATCH v3 00/15] Support ROHM BD71815 PMIC Matti Vaittinen
2021-03-08 10:39 ` [PATCH v3 01/15] rtc: bd70528: Do not require parent data Matti Vaittinen
2021-03-08 10:41 ` [PATCH v3 06/15] mfd: Add ROHM BD71815 ID Matti Vaittinen
2021-03-10 10:36 ` Lee Jones
2021-03-10 11:07 ` Vaittinen, Matti
2021-03-10 11:17 ` Lee Jones
2021-03-10 13:02 ` Matti Vaittinen
2021-03-10 13:31 ` Lee Jones
2021-03-10 14:39 ` Matti Vaittinen
2021-03-10 16:38 ` Lee Jones
2021-03-08 10:42 ` [PATCH v3 07/15] mfd: Support for ROHM BD71815 PMIC core Matti Vaittinen
2021-03-10 10:40 ` Lee Jones
2021-03-08 10:45 ` [PATCH v3 14/15] rtc: bd70528: Support RTC on ROHM BD71815 Matti Vaittinen
2021-03-08 10:45 ` [PATCH v3 15/15] MAINTAINERS: Add ROHM BD71815AGW Matti Vaittinen
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).