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From: Michael Schmitz <schmitzmic@gmail.com>
To: James Bottomley <jejb@linux.ibm.com>,
	Kars de Jong <jongk@linux-m68k.org>,
	"Martin K. Petersen" <martin.petersen@oracle.com>
Cc: linux-scsi@vger.kernel.org, linux-m68k@vger.kernel.org
Subject: Re: [PATCH] zorro_esp: increase maximum dma length to 65536 bytes
Date: Sun, 10 Nov 2019 15:36:54 +1300	[thread overview]
Message-ID: <6b914b12-cbc7-6fe6-7cba-3e89b2f6f19b@gmail.com> (raw)
In-Reply-To: <1573330351.3650.4.camel@linux.ibm.com>

James,

Am 10.11.2019 um 09:12 schrieb James Bottomley:
> On Sat, 2019-11-09 at 20:14 +0100, Kars de Jong wrote:
>> When using this driver on a Blizzard 1260, there were failures
>> whenever DMA transfers from the SCSI bus to memory of 65535 bytes
>> were followed by a DMA transfer of 1 byte. This caused the byte at
>> offset 65535 to be overwritten with 0xff. The Blizzard hardware can't
>> handle single byte DMA transfers.
>>
>> Besides this issue, limiting the DMA length to something that is not
>> a multiple of the page size is very inefficient on most file systems.
>>
>> It seems this limit was chosen because the DMA transfer counter of
>> the ESP by default is 16 bits wide, thus limiting the length to 65535
>> bytes. However, the value 0 means 65536 bytes, which is handled by
>> the ESP and the Blizzard just fine. It is also the default maximum
>> used by esp_scsi when drivers don't provide their own
>> dma_length_limit() function.
>
> Have you tested this on any other hardware?  the reason most legacy
> hardware would have a setting like this is because they have a two byte
> transfer length register and zero doesn't mean 65536.  If this is the

The data book for the NCR53FC94/NCR53FC96 (the 'fast' SCSI controller 
used on the board Kars tried) states that with the features enable bit 
clear (no 24 bit DMA counts used), zero does mean 64k indeed. The 
features enable bit is never set by esp_scsi.c. I chose the incorrect 
length limit without realizing this special case for the transfer count. 
and before we found out that 1-byte DMA just won't work.

I need to confirm this from a data book of the older (pre-fast) 
revisions of this chip family. but since as Kars also states, the core 
driver default for the 16 bit transfer size is 64k as well, I very much 
suspect the same behaviour for the older revisions.

All of the old board-specific drivers used a max transfer length of 
0x1000000, only the fastlane driver used 0xfffc. That lower limit might 
be due to a DMA limitation on the fastlane board. We could accommodate 
the different limit for this board by using a board-specific 
dma_length_limit() callback...

> case for any of the cards the zorro_esp drives, it might be better to
> lower the max length to 61440 (64k-4k) so the residual is a page.

For the benefit of keeping the code simple, and avoid retesting the 
fastlane board, that might indeed be the better solution.

Cheers,

	Michael

>
> James
>

  reply	other threads:[~2019-11-10  2:37 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CACz-3rh9ZCyU1825yU8xxty5BGrwFhpbjKNoWnn0mGiv_h2Kag@mail.gmail.com>
2019-11-09 19:14 ` [PATCH] zorro_esp: increase maximum dma length to 65536 bytes Kars de Jong
2019-11-09 20:12   ` James Bottomley
2019-11-10  2:36     ` Michael Schmitz [this message]
2019-11-10  9:01       ` Kars de Jong
2019-11-10 19:26         ` Michael Schmitz
2019-11-11  8:47           ` Kars de Jong
2019-11-10 19:35       ` James Bottomley
2019-11-12 17:55         ` [PATCH v2] zorro_esp: Limit DMA transfers to 65536 bytes (except on Fastlane) Kars de Jong
2019-11-12 22:46           ` Finn Thain
2019-11-13  2:27           ` Martin K. Petersen
2019-11-12  9:34       ` [PATCH] zorro_esp: increase maximum dma length to 65536 bytes Kars de Jong
2019-11-09 22:53   ` Finn Thain
2019-11-10  9:06     ` Kars de Jong

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