From: Akash Asthana <akashast@codeaurora.org>
To: gregkh@linuxfoundation.org, agross@kernel.org,
bjorn.andersson@linaro.org, wsa@the-dreams.de,
broonie@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org,
georgi.djakov@linaro.org
Cc: linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, swboyd@chromium.org,
mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org,
linux-serial@vger.kernel.org, mka@chromium.org,
dianders@chromium.org, evgreen@chromium.org,
Akash Asthana <akashast@codeaurora.org>
Subject: [PATCH V4 8/9] spi: spi-qcom-qspi: Add interconnect support
Date: Wed, 15 Apr 2020 15:53:17 +0530 [thread overview]
Message-ID: <1586946198-13912-9-git-send-email-akashast@codeaurora.org> (raw)
In-Reply-To: <1586946198-13912-1-git-send-email-akashast@codeaurora.org>
Get the interconnect paths for QSPI device and vote according to the
current bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed by: Matthias Kaehlcke <mka@chromium.org>
---
Changes in V2:
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- No Change.
Changes in V4:
- As per Mark's comment move peak_bw guess as twice of avg_bw if
nothing mentioned explicitly to ICC core.
drivers/spi/spi-qcom-qspi.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c
index 3c4f83b..5aaf454 100644
--- a/drivers/spi/spi-qcom-qspi.c
+++ b/drivers/spi/spi-qcom-qspi.c
@@ -2,6 +2,7 @@
// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
#include <linux/clk.h>
+#include <linux/interconnect.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -139,7 +140,10 @@ struct qcom_qspi {
struct device *dev;
struct clk_bulk_data *clks;
struct qspi_xfer xfer;
- /* Lock to protect xfer and IRQ accessed registers */
+ struct icc_path *icc_path_cpu_to_qspi;
+ unsigned int avg_bw_cpu;
+ unsigned int peak_bw_cpu;
+ /* Lock to protect data accessed by IRQs */
spinlock_t lock;
};
@@ -241,6 +245,16 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
return ret;
}
+ /* Set BW quota for CPU as driver supports FIFO mode only. */
+ ctrl->avg_bw_cpu = Bps_to_icc(speed_hz);
+ ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, ctrl->avg_bw_cpu,
+ ctrl->peak_bw_cpu);
+ if (ret) {
+ dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu\n",
+ __func__);
+ return ret;
+ }
+
spin_lock_irqsave(&ctrl->lock, flags);
/* We are half duplex, so either rx or tx will be set */
@@ -458,6 +472,16 @@ static int qcom_qspi_probe(struct platform_device *pdev)
if (ret)
goto exit_probe_master_put;
+ ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
+ if (IS_ERR(ctrl->icc_path_cpu_to_qspi)) {
+ ret = PTR_ERR(ctrl->icc_path_cpu_to_qspi);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get cpu path, ret:%d\n", ret);
+ goto exit_probe_master_put;
+ }
+ /* Put BW vote on CPU path for register access */
+ ctrl->avg_bw_cpu = Bps_to_icc(1000);
+
ret = platform_get_irq(pdev, 0);
if (ret < 0)
goto exit_probe_master_put;
@@ -511,9 +535,17 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+ int ret;
clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
+ ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, 0, 0);
+ if (ret) {
+ dev_err_ratelimited(ctrl->dev, "%s: ICC BW remove failed for cpu\n",
+ __func__);
+ return ret;
+ }
+
return 0;
}
@@ -521,6 +553,15 @@ static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+ int ret;
+
+ ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, ctrl->avg_bw_cpu,
+ ctrl->peak_bw_cpu);
+ if (ret) {
+ dev_err_ratelimited(ctrl->dev, "%s: ICC BW voting failed for cpu\n",
+ __func__);
+ return ret;
+ }
return clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-04-15 10:27 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-15 10:23 [PATCH V4 0/9] Add interconnect support to QSPI and QUP drivers Akash Asthana
2020-04-15 10:23 ` [PATCH V4 1/9] interconnect: Add devm_of_icc_get() as exported API for users Akash Asthana
2020-04-28 16:04 ` Georgi Djakov
2020-04-15 10:23 ` [PATCH V4 2/9] interconnect: Set peak requirement as twice of average Akash Asthana
2020-04-23 9:31 ` Georgi Djakov
2020-04-28 9:46 ` Akash Asthana
2020-04-28 10:53 ` Georgi Djakov
2020-04-15 10:23 ` [PATCH V4 3/9] soc: qcom: geni: Support for ICC voting Akash Asthana
2020-04-15 23:36 ` Matthias Kaehlcke
2020-04-28 9:48 ` Akash Asthana
2020-04-15 10:23 ` [PATCH V4 4/9] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana
2020-04-16 0:31 ` Matthias Kaehlcke
2020-04-28 10:21 ` Akash Asthana
2020-04-28 15:48 ` Matthias Kaehlcke
2020-04-15 10:23 ` [PATCH V4 5/9] i2c: i2c-qcom-geni: Add interconnect support Akash Asthana
2020-04-16 17:09 ` Matthias Kaehlcke
2020-04-15 10:23 ` [PATCH V4 6/9] spi: spi-geni-qcom: " Akash Asthana
2020-04-15 11:39 ` Mark Brown
2020-04-15 10:23 ` [PATCH V4 7/9] tty: serial: qcom_geni_serial: " Akash Asthana
2020-04-16 17:17 ` Matthias Kaehlcke
2020-04-15 10:23 ` Akash Asthana [this message]
2020-04-15 10:23 ` [PATCH V4 9/9] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
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