From: Vineet.Gupta1@synopsys.com (Vineet Gupta)
To: linux-snps-arc@lists.infradead.org
Subject: [PATCH 2/6] ARCv2: mm: TLB Miss optim: Use double world load/stores LDD/STD
Date: Mon, 16 Sep 2019 14:32:03 -0700 [thread overview]
Message-ID: <20190916213207.12792-3-vgupta@synopsys.com> (raw)
In-Reply-To: <20190916213207.12792-1-vgupta@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta at synopsys.com>
---
arch/arc/mm/tlbex.S | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index d6fbdeda400a..110c72536e8b 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -122,17 +122,27 @@ ex_saved_reg1:
#else /* ARCv2 */
.macro TLBMISS_FREEUP_REGS
+#ifdef CONFIG_ARC_HAS_LL64
+ std r0, [sp, -16]
+ std r2, [sp, -8]
+#else
PUSH r0
PUSH r1
PUSH r2
PUSH r3
+#endif
.endm
.macro TLBMISS_RESTORE_REGS
+#ifdef CONFIG_ARC_HAS_LL64
+ ldd r0, [sp, -16]
+ ldd r2, [sp, -8]
+#else
POP r3
POP r2
POP r1
POP r0
+#endif
.endm
#endif
--
2.20.1
next prev parent reply other threads:[~2019-09-16 21:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-16 21:32 [PATCH 0/6] ARC MMU code updates Vineet Gupta
2019-09-16 21:32 ` [PATCH 1/6] ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg Vineet Gupta
2019-09-16 21:32 ` Vineet Gupta [this message]
2019-09-16 21:32 ` [PATCH 3/6] ARC: mm: TLB Miss optim: avoid re-reading ECR Vineet Gupta
2019-09-16 23:36 ` Alexey Brodkin
2019-09-17 21:08 ` Vineet Gupta
2019-09-16 21:32 ` [PATCH 4/6] ARC: mm: tlb flush optim: Make TLBWriteNI fallback to TLBWrite if not available Vineet Gupta
2019-09-16 21:32 ` [PATCH 5/6] ARC: mm: tlb flush optim: elide repeated uTLB invalidate in loop Vineet Gupta
2019-09-16 21:32 ` [PATCH 6/6] ARC: mm: tlb flush optim: elide redundant uTLB invalidates for MMUv3 Vineet Gupta
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