[PATCH 0/3] teach sparse about the '-march' for RISC-V

[PATCH 0/3] teach sparse about the '-march' for RISC-V

[Luc Van Oostenryck]

RISC-V architecture has a set of extensions and those are
reflected in the predefined macros.
This series add support for '-march' as an architecture-specific
option and uses for RISC-V to correctly predefine these macros.

Luc Van Oostenryck (3):
  arch: teach sparse about the '-march' option
  riscv: parse '-march=....'
  riscv: add the predefines for the extensions

 options.c      |  8 ++++
 target-riscv.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++
 target.h       |  2 +
 3 files changed, 109 insertions(+)

-- 
2.27.0

[PATCH 1/3] arch: teach sparse about the '-march' option

[Luc Van Oostenryck]

The option '-march' is not one of the common option but is
architecture specific.

So, teach sparse to delegate the parsing of this option to
the targets.

Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
---
 options.c | 8 ++++++++
 target.h  | 1 +
 2 files changed, 9 insertions(+)

diff --git a/options.c b/options.c
index 9f05bdf9cf4f..1a3fee3c6751 100644
--- a/options.c
+++ b/options.c
@@ -609,6 +609,13 @@ static char **handle_switch_M(char *arg, char **next)
 	return next;
 }
 
+static int handle_march(const char *opt, const char *arg, const struct flag *flag, int options)
+{
+	if (arch_target->parse_march)
+		arch_target->parse_march(arg);
+	return 1;
+}
+
 static int handle_mcmodel(const char *opt, const char *arg, const struct flag *flag, int options)
 {
 	static const struct val_map cmodels[] = {
@@ -650,6 +657,7 @@ static const struct flag mflags[] = {
 	{ "x32",&arch_m64, NULL, OPT_VAL, ARCH_X32 },
 	{ "size-llp64", &arch_m64, NULL, OPT_VAL, ARCH_LLP64 },
 	{ "size-long", &arch_msize_long },
+	{ "arch=", NULL, handle_march },
 	{ "big-endian", &arch_big_endian, NULL },
 	{ "little-endian", &arch_big_endian, NULL, OPT_INVERSE },
 	{ "cmodel", &arch_cmodel, handle_mcmodel },
diff --git a/target.h b/target.h
index 8f79426c096a..54e97e83b10d 100644
--- a/target.h
+++ b/target.h
@@ -76,6 +76,7 @@ struct target {
 	const struct builtin_fn *builtins;
 
 	void (*init)(const struct target *self);
+	void (*parse_march)(const char *arg);
 	void (*predefine)(const struct target *self);
 	const char *(*asm_constraint)(struct asm_operand *op, int c, const char *str);
 };
-- 
2.27.0

[PATCH 2/3] riscv: parse '-march=....'

[Luc Van Oostenryck]

The RISC-V architecture has quite a bit of extensions.
Some of these correspond to a predefined macro and thus
parsing correctly the '-march' flag can be important.

So, teach sparse how to parse this flag for RISC-V.

Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
---
 target-riscv.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++
 target.h       |  1 +
 2 files changed, 81 insertions(+)

diff --git a/target-riscv.c b/target-riscv.c
index d68fb585c254..9431ebc9cabb 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -1,7 +1,80 @@
+#include "lib.h"
 #include "symbol.h"
 #include "target.h"
 #include "machine.h"
+#include <string.h>
 
+#define RISCV_32BIT	(1 << 0)
+#define RISCV_64BIT	(1 << 1)
+#define RISCV_MUL	(1 << 2)
+#define RISCV_DIV	(1 << 3)
+#define RISCV_ATOMIC	(1 << 4)
+#define RISCV_FLOAT	(1 << 5)
+#define RISCV_DOUBLE	(1 << 6)
+#define RISCV_FDIV	(1 << 7)
+#define RISCV_COMP	(1 << 8)
+#define RISCV_EMBD	(1 << 9)
+#define RISCV_FPU	(RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV)
+#define RISCV_GENERIC	(RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU)
+
+static unsigned int riscv_flags;
+
+static void parse_march_riscv(const char *arg)
+{
+	static struct {
+		const char *pattern;
+		unsigned int flags;
+	} basic_sets[] = {
+		{ "rv32i",	RISCV_32BIT },
+		{ "rv32e",	RISCV_32BIT|RISCV_EMBD },
+		{ "rv32g",	RISCV_32BIT|RISCV_GENERIC },
+		{ "rv64i",	RISCV_64BIT },
+		{ "rv64g",	RISCV_64BIT|RISCV_GENERIC },
+	}, extensions[] = {
+		{ "m",		RISCV_MUL|RISCV_DIV },
+		{ "a",		RISCV_ATOMIC },
+		{ "f",		RISCV_FLOAT|RISCV_FDIV },
+		{ "d",		RISCV_DOUBLE|RISCV_FDIV },
+		{ "g",		RISCV_GENERIC },
+		{ "q",		0 },
+		{ "l",		0 },
+		{ "c",		RISCV_COMP },
+		{ "b",		0 },
+		{ "j",		0 },
+		{ "t",		0 },
+		{ "p",		0 },
+		{ "v",		0 },
+		{ "n",		0 },
+		{ "h",		0 },
+		{ "s",		0 },
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(basic_sets); i++) {
+		const char *pat = basic_sets[i].pattern;
+		size_t len = strlen(pat);
+
+		if (!strncmp(arg, pat, len)) {
+			riscv_flags |= basic_sets[i].flags;
+			arg += len;
+			goto ext;
+		}
+	}
+	die("invalid argument to '-march': '%s'\n", arg);
+
+ext:
+	for (i = 0; i < ARRAY_SIZE(extensions); i++) {
+		const char *pat = extensions[i].pattern;
+		size_t len = strlen(pat);
+
+		if (!strncmp(arg, pat, len)) {
+			riscv_flags |= extensions[i].flags;
+			arg += len;
+		}
+	}
+	if (arg[0])
+		die("invalid argument to '-march': '%s'\n", arg);
+}
 
 static void init_riscv(const struct target *self)
 {
@@ -9,6 +82,9 @@ static void init_riscv(const struct target *self)
 		arch_cmodel = CMODEL_MEDLOW;
 	if (fpic)
 		arch_cmodel = CMODEL_PIC;
+
+	if (riscv_flags == 0)
+		riscv_flags = self->flags;
 }
 
 static void predefine_riscv(const struct target *self)
@@ -32,11 +108,13 @@ const struct target target_riscv32 = {
 	.bitness = ARCH_LP32,
 	.big_endian = 0,
 	.unsigned_char = 1,
+	.flags = RISCV_32BIT|RISCV_GENERIC|RISCV_COMP,
 
 	.target_64bit = &target_riscv64,
 
 	.init = init_riscv,
 	.predefine = predefine_riscv,
+	.parse_march = parse_march_riscv,
 };
 
 const struct target target_riscv64 = {
@@ -45,9 +123,11 @@ const struct target target_riscv64 = {
 	.big_endian = 0,
 	.unsigned_char = 1,
 	.has_int128 = 1,
+	.flags = RISCV_64BIT|RISCV_GENERIC|RISCV_COMP,
 
 	.target_32bit = &target_riscv32,
 
 	.init = init_riscv,
 	.predefine = predefine_riscv,
+	.parse_march = parse_march_riscv,
 };
diff --git a/target.h b/target.h
index 54e97e83b10d..76b7d12318c6 100644
--- a/target.h
+++ b/target.h
@@ -63,6 +63,7 @@ struct target {
 	unsigned int	unsigned_char:1;
 	unsigned int	size_t_long:1;
 	unsigned int	has_int128:1;
+	unsigned long	flags;
 
 	struct symbol	*wchar;
 	struct symbol	*wint;
-- 
2.27.0

[PATCH 3/3] riscv: add the predefines for the extensions

[Luc Van Oostenryck]

The RISC-V architecture has some predefined macros
to specify which extensions are supported.

So, now that these extensions are known via the '-march'
options, add the corresponding predefines.

Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
---
 target-riscv.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/target-riscv.c b/target-riscv.c
index 9431ebc9cabb..e7f2b03b821b 100644
--- a/target-riscv.c
+++ b/target-riscv.c
@@ -99,6 +99,25 @@ static void predefine_riscv(const struct target *self)
 	predefine("__riscv", 1, "1");
 	predefine("__riscv_xlen", 1, "%d", ptr_ctype.bit_size);
 
+	if (riscv_flags & RISCV_ATOMIC)
+		predefine("__riscv_atomic", 1, "1");
+	if (riscv_flags & RISCV_COMP)
+		predefine("__riscv_compressed", 1, "1");
+	if (riscv_flags & RISCV_DIV)
+		predefine("__riscv_div", 1, "1");
+	if (riscv_flags & RISCV_EMBD)
+		predefine("__riscv_32e", 1, "1");
+	if (riscv_flags & RISCV_FPU)
+		predefine("__riscv_flen", 1, "%d", (riscv_flags & RISCV_DOUBLE) ? 64 : 32);
+	if (riscv_flags & RISCV_FDIV)
+		predefine("__riscv_fdiv", 1, "1");
+	if (riscv_flags & RISCV_FDIV)
+		predefine("__riscv_fsqrt", 1, "1");
+	if (riscv_flags & RISCV_MUL)
+		predefine("__riscv_mul", 1, "1");
+	if ((riscv_flags & RISCV_MUL) && (riscv_flags & RISCV_DIV))
+		predefine("__riscv_muldiv", 1, "1");
+
 	if (cmodel)
 		predefine_strong("__riscv_cmodel_%s", cmodel);
 }
-- 
2.27.0