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* [PATCH] spi: spi-cadence: add support for chip select high
@ 2020-07-10  4:51 Shreyas Joshi
  2020-07-10 15:35 ` Mark Brown
  2020-07-10 21:16 ` Shreyas Joshi
  0 siblings, 2 replies; 7+ messages in thread
From: Shreyas Joshi @ 2020-07-10  4:51 UTC (permalink / raw)
  To: broonie, linux-spi, shreyasjoshi15; +Cc: linux-kernel, Shreyas Joshi

spi cadence driver should support spi-cs-high in mode bits
so that the peripherals that needs the chip select to be high active can
use it. Add the SPI-CS-HIGH flag in the supported mode bits.

Signed-off-by: Shreyas Joshi <shreyas.joshi@biamp.com>
---
 drivers/spi/spi-cadence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 82a0ee09cbe1..2b6b9c1ad9d0 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -556,7 +556,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
 	master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 	master->set_cs = cdns_spi_chipselect;
 	master->auto_runtime_pm = true;
-	master->mode_bits = SPI_CPOL | SPI_CPHA;
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 	/* Set to default valid value */
 	master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
--
2.20.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] spi: spi-cadence: add support for chip select high
  2020-07-10  4:51 [PATCH] spi: spi-cadence: add support for chip select high Shreyas Joshi
@ 2020-07-10 15:35 ` Mark Brown
  2020-07-10 21:16 ` Shreyas Joshi
  1 sibling, 0 replies; 7+ messages in thread
From: Mark Brown @ 2020-07-10 15:35 UTC (permalink / raw)
  To: Shreyas Joshi; +Cc: linux-spi, shreyasjoshi15, linux-kernel


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On Fri, Jul 10, 2020 at 02:51:40PM +1000, Shreyas Joshi wrote:

> spi cadence driver should support spi-cs-high in mode bits
> so that the peripherals that needs the chip select to be high active can
> use it. Add the SPI-CS-HIGH flag in the supported mode bits.

This doesn't apply against current code, please check and resend:

HEAD is now at 3ea4eac3e29f SPI SUBSYSTEM: Replace HTTP links with HTTPS ones
Applying: spi: spi-cadence: add support for chip select high
error: corrupt patch at line 18
error: could not build fake ancestor
Patch failed at 0001 spi: spi-cadence: add support for chip select high

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^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH] spi: spi-cadence: add support for chip select high
  2020-07-10  4:51 [PATCH] spi: spi-cadence: add support for chip select high Shreyas Joshi
  2020-07-10 15:35 ` Mark Brown
@ 2020-07-10 21:16 ` Shreyas Joshi
  2020-07-20  3:55   ` Shreyas Joshi
                     ` (2 more replies)
  1 sibling, 3 replies; 7+ messages in thread
From: Shreyas Joshi @ 2020-07-10 21:16 UTC (permalink / raw)
  To: broonie, linux-spi, shreyasjoshi15; +Cc: linux-kernel, Shreyas Joshi

The spi cadence driver should support spi-cs-high in mode bits
so that the peripherals that needs the chip select to be high active can
use it. Add the SPI-CS-HIGH flag in the supported mode bits.

Signed-off-by: Shreyas Joshi <shreyas.joshi@biamp.com>
---
 drivers/spi/spi-cadence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 82a0ee09cbe1..2b6b9c1ad9d0 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -556,7 +556,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
 	master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 	master->set_cs = cdns_spi_chipselect;
 	master->auto_runtime_pm = true;
-	master->mode_bits = SPI_CPOL | SPI_CPHA;
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
 	/* Set to default valid value */
 	master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
-- 
2.20.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* RE: [PATCH] spi: spi-cadence: add support for chip select high
  2020-07-10 21:16 ` Shreyas Joshi
@ 2020-07-20  3:55   ` Shreyas Joshi
  2020-07-20 12:54     ` Mark Brown
  2020-07-21  0:08   ` Shreyas Joshi
  2020-07-22 13:45   ` Mark Brown
  2 siblings, 1 reply; 7+ messages in thread
From: Shreyas Joshi @ 2020-07-20  3:55 UTC (permalink / raw)
  To: Shreyas Joshi, broonie, linux-spi, shreyasjoshi15; +Cc: linux-kernel

Were you able to patch my driver successfully?

-----Original Message-----
From: Shreyas Joshi <shreyas.joshi@biamp.com> 
Sent: Saturday, 11 July 2020 7:17 AM
To: broonie@kernel.org; linux-spi@vger.kernel.org; shreyasjoshi15@gmail.com
Cc: linux-kernel@vger.kernel.org; Shreyas Joshi <Shreyas.Joshi@biamp.com>
Subject: [PATCH] spi: spi-cadence: add support for chip select high

The spi cadence driver should support spi-cs-high in mode bits so that the peripherals that needs the chip select to be high active can use it. Add the SPI-CS-HIGH flag in the supported mode bits.

Signed-off-by: Shreyas Joshi <shreyas.joshi@biamp.com>
---
 drivers/spi/spi-cadence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 82a0ee09cbe1..2b6b9c1ad9d0 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -556,7 +556,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
 	master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 	master->set_cs = cdns_spi_chipselect;
 	master->auto_runtime_pm = true;
-	master->mode_bits = SPI_CPOL | SPI_CPHA;
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
 	/* Set to default valid value */
 	master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
--
2.20.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] spi: spi-cadence: add support for chip select high
  2020-07-20  3:55   ` Shreyas Joshi
@ 2020-07-20 12:54     ` Mark Brown
  0 siblings, 0 replies; 7+ messages in thread
From: Mark Brown @ 2020-07-20 12:54 UTC (permalink / raw)
  To: Shreyas Joshi; +Cc: linux-spi, shreyasjoshi15, linux-kernel


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On Mon, Jul 20, 2020 at 03:55:55AM +0000, Shreyas Joshi wrote:
> Were you able to patch my driver successfully?
> 
> -----Original Message-----

Please don't send content free pings and please allow a reasonable time
for review.  People get busy, go on holiday, attend conferences and so 
on so unless there is some reason for urgency (like critical bug fixes)
please allow at least a couple of weeks for review.  If there have been
review comments then people may be waiting for those to be addressed.

Sending content free pings adds to the mail volume (if they are seen at
all) which is often the problem and since they can't be reviewed
directly if something has gone wrong you'll have to resend the patches
anyway, so sending again is generally a better approach though there are
some other maintainers who like them - if in doubt look at how patches
for the subsystem are normally handled.

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^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH] spi: spi-cadence: add support for chip select high
  2020-07-10 21:16 ` Shreyas Joshi
  2020-07-20  3:55   ` Shreyas Joshi
@ 2020-07-21  0:08   ` Shreyas Joshi
  2020-07-22 13:45   ` Mark Brown
  2 siblings, 0 replies; 7+ messages in thread
From: Shreyas Joshi @ 2020-07-21  0:08 UTC (permalink / raw)
  To: broonie, linux-spi, shreyasjoshi15; +Cc: linux-kernel, Shreyas Joshi

The spi cadence driver should support spi-cs-high in mode bits
so that the peripherals that needs the chip select to be high active can
use it. Add the SPI-CS-HIGH flag in the supported mode bits.

Signed-off-by: Shreyas Joshi <shreyas.joshi@biamp.com>
---
 drivers/spi/spi-cadence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 82a0ee09cbe1..2b6b9c1ad9d0 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -556,7 +556,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
 	master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 	master->set_cs = cdns_spi_chipselect;
 	master->auto_runtime_pm = true;
-	master->mode_bits = SPI_CPOL | SPI_CPHA;
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
 	/* Set to default valid value */
 	master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
-- 
2.20.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] spi: spi-cadence: add support for chip select high
  2020-07-10 21:16 ` Shreyas Joshi
  2020-07-20  3:55   ` Shreyas Joshi
  2020-07-21  0:08   ` Shreyas Joshi
@ 2020-07-22 13:45   ` Mark Brown
  2 siblings, 0 replies; 7+ messages in thread
From: Mark Brown @ 2020-07-22 13:45 UTC (permalink / raw)
  To: linux-spi, Shreyas Joshi, shreyasjoshi15; +Cc: linux-kernel

On Sat, 11 Jul 2020 07:16:55 +1000, Shreyas Joshi wrote:
> The spi cadence driver should support spi-cs-high in mode bits
> so that the peripherals that needs the chip select to be high active can
> use it. Add the SPI-CS-HIGH flag in the supported mode bits.

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: spi-cadence: add support for chip select high
      commit: ce8e60fe4f517b3b2b1deb44cf364a9080521567

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

^ permalink raw reply	[flat|nested] 7+ messages in thread

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Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-10  4:51 [PATCH] spi: spi-cadence: add support for chip select high Shreyas Joshi
2020-07-10 15:35 ` Mark Brown
2020-07-10 21:16 ` Shreyas Joshi
2020-07-20  3:55   ` Shreyas Joshi
2020-07-20 12:54     ` Mark Brown
2020-07-21  0:08   ` Shreyas Joshi
2020-07-22 13:45   ` Mark Brown

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