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* [PATCH v5 0/9] Make atmel serial driver aware of GCLK
@ 2022-09-22 11:33 Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Sergiu Moga
                   ` (8 more replies)
  0 siblings, 9 replies; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga

This series of patches introduces the GCLK as a clock source for
the baudrate generator of UART on sama5d2 SoCs. Unlike the serial mode of
the USART offered by FLEXCOM, the UART does not provide a fractional part
that can be added to the clock divisor to obtain a more accurate result,
which greatly decreases the flexibility available for producing a higher
variety of baudrates. Now, with the last patch of the series, the driver
will check for a GCLK in the DT. If provided, whenever `atmel_set_termios`
is called, unless there is a fractional part, the driver will compare the
error rate between the desired baudrate and the actual baudrate obtained
through each of the available clock sources and will choose the clock source
with the lowest error rate. While at it, convert the DT binding
for UART/USART to json-schema, update the FLEXCOM binding to reference the
new UART/USART binding (while differentiating between the SPI of USART and the
SPI of FLEXCOM), do some small DT related fixups and do some small driver
cleanup.

The DT bindings related patches of this patch series depend on this patch
series converting atmel-flexcom bindings to json-schema:
https://lore.kernel.org/linux-arm-kernel/20220916075744.1879428-1-kavyasree.kotagiri@microchip.com/

v1 -> v2:
- [PATCH 3] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref
    binding:
	- use full schema paths

- [PATCH 5] dt-bindings: serial: atmel,at91-usart: convert to json-schema
	- only do what the commit says, split the addition of other compatibles
	(PATCH 6) and properties (PATCH 13) in other patches
	- remove unnecessary "|"'s
	- mention header in `atmel,usart-mode`'s description
	- place `if:` under `allOf:`
	- respect order of spi0's DT properties: compatible, then reg then the
	reset of properties

- two new baudrate clock source related patches:
  [PATCH 9] tty: serial: atmel: Add definition for GCLK as baudrate source clock
			+
  [PATCH 10] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode
    Register:
	- v1's bitfield definition of GCLK was wrong, so add two more patches:
		- one for the definition of GCLK of USART IP's
		- one for the definition of BRSRCCK bitmask and its bitfields
		for UART IP's

- a new cleanup related patch that introduces a new struct atmel_uart_port field:
  [PATCH 11] tty: serial: atmel: Only divide Clock Divisor if the IP is USART:
  	- this ensures a division by 8 which is unnecessary and unappliable to
	UART IP's is only done for USART IP's

- four new patches regarding DT fixes and a SPI binding update that I came
upon:
  [PATCH 1] spi: dt-bindings: atmel,at91rm9200-spi: Add DMA related properties
  [PATCH 2] ARM: dts: at91: sama7g5: Swap rx and tx for spi11
  [PATCH 4] ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1
  [PATCH 6] dt-bindings: serial: atmel,at91-usart: Highlight SAM9X60 incremental

- [PATCH 12] tty: serial: atmel: Make the driver aware of the existence of GCLK
	- take into account the different placement of the baudrate clock source
	into the IP's Mode Register (USART vs UART)
	- don't check for atmel_port->gclk != NULL
	- use clk_round_rate instead of clk_set_rate + clk_get_rate
	- remove clk_disable_unprepare from the end of the probe method

v2 -> v3:
- Re-order the patches as suggested by Krzysztof Kozlowski:
1. DTS changes needed for aligning to schema.
2. all bindings
3. rest

- New DT consistency related patch:
  [PATCH 3] ARM: dts: at91: Add `atmel,usart-mode` required property to serial
    nodes

- [PATCH 6] dt-bindings: serial: atmel,at91-usart: convert to json-schema:
  - Check value of `atmel,usart-mode` instead of the node regex
  - Define all properties top level and disallow them explicitly for other type,
  since additionalProperties:false conflicts with referencing other schemas
  - Remove useless else if: after else:

- [PATCH 7] dt-bindings: serial: atmel,at91-usart: add SAM9260 compatibles to
  SAM9X60:
  - Use the commit message suggested by Krzysztof Kozlowski

- [PATCH 8] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref
  binding
  - Compare devices based on the compatible instead of the clock

- [PATCH 12] tty: serial: atmel: Only divide Clock Divisor if the IP is USART
  - Use ATMEL_US_CD instead of 65535

- [PATCH 14] tty: serial: atmel: Make the driver aware of the existence of GCLK
  - add `gclk_fail` goto
  - replace `goto err` with `goto err_clk_disable_unprepare;`


v3 -> v4:
- Remove the first 4 patches as they have already been applied
https://lore.kernel.org/linux-arm-kernel/b537bbcf-cb0f-551d-6dd0-cf50864bafa3@microchip.com/
https://lore.kernel.org/linux-arm-kernel/53e72e5d-47fc-403d-c969-61b267a9ff15@microchip.com/
https://lore.kernel.org/linux-arm-kernel/1ae89854-74fa-6194-304f-db31d56d3674@microchip.com/
https://lore.kernel.org/linux-arm-kernel/3234cd79-65db-1210-50c1-e880ec6d87a0@microchip.com/
- Remove the addition of gclk's to sama5d2 clock driver as it has already been applied
https://lore.kernel.org/linux-arm-kernel/4b23db7d-d6b2-6c93-01f7-6a3b86f403d1@microchip.com/
- [PATCH 2] -> [PATCH 5]
  - add Acked-by/Reviewed-by tags to DT bindings
- [PATCH 8]
  - replace & with min_t



v4 -> v5:
- squash previous
`[PATCH v4 7/9] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register`
into a newly added
`[PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART`
whose role is mainly of cleanup and to make a clear separation between the
clearing of the mode for UART vs USART and make BRSRCCK into a bitfield
instead of a bitmask as it is only a bit.
- squash previous
`[PATCH v4 6/9] tty: serial: atmel: Define GCLK as USART baudrate source clock`
into the current
`[PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK`
- new bitfield conversions to FIELD_PREP/FIELD_GET PATCH
`[PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET`


Sergiu Moga (9):
  dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref
    binding
  dt-bindings: serial: atmel,at91-usart: convert to json-schema
  dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to
    SAM9X60
  dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref
    binding
  dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART
    clock
  tty: serial: atmel: Separate mode clearing between UART and USART
  tty: serial: atmel: Only divide Clock Divisor if the IP is USART
  tty: serial: atmel: Make the driver aware of the existence of GCLK
  tty: serial: atmel: Use FIELD_PREP/FIELD_GET

 .../bindings/mfd/atmel,sama5d2-flexcom.yaml   |  19 +-
 .../devicetree/bindings/mfd/atmel-usart.txt   |  98 ---------
 .../bindings/serial/atmel,at91-usart.yaml     | 190 ++++++++++++++++++
 drivers/tty/serial/atmel_serial.c             |  82 +++++++-
 drivers/tty/serial/atmel_serial.h             |  75 +++----
 5 files changed, 321 insertions(+), 143 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-usart.txt
 create mode 100644 Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml

-- 
2.34.1


^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-28 15:03   ` Lee Jones
  2022-09-22 11:33 ` [PATCH v5 2/9] dt-bindings: serial: atmel,at91-usart: convert to json-schema Sergiu Moga
                   ` (7 subsequent siblings)
  8 siblings, 1 reply; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga, Krzysztof Kozlowski

Another functionality of FLEXCOM is that of SPI. In order for
the proper validation of the SPI children nodes through the binding
to occur, the proper binding for SPI must be referenced.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---


v1 -> v2:
- use full schema paths


v2 -> v3:
- Added Reviewed-by tag, previously this was [PATCH 3]


v3 -> v4:
- Nothing, previously this was [PATCH 5]


v4 -> v5:
- Nothing



 .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml       | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
index 0c80f4e98c54..f283cfd84b2d 100644
--- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
+++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
@@ -78,10 +78,9 @@ patternProperties:
       of USART bindings.
 
   "^spi@[0-9a-f]+$":
-    type: object
+    $ref: /schemas/spi/atmel,at91rm9200-spi.yaml
     description:
-      Child node describing SPI. See ../spi/spi_atmel.txt for details
-      of SPI bindings.
+      Child node describing SPI.
 
   "^i2c@[0-9a-f]+$":
     $ref: /schemas/i2c/atmel,at91sam-i2c.yaml
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v5 2/9] dt-bindings: serial: atmel,at91-usart: convert to json-schema
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 3/9] dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to SAM9X60 Sergiu Moga
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga, Krzysztof Kozlowski

Convert at91 USART DT Binding for Atmel/Microchip SoCs to
json-schema format. Furthermore, move this binding to the
serial directory, since binding directories match hardware,
unlike the driver subsystems which match Linux convention.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---


v1 -> v2:
- only do what the commit says, split the addition of other compatibles and
properties in other patches
- remove unnecessary "|"'s
- mention header in `atmel,usart-mode`'s description
- place `if:` under `allOf:`
- respect order of spi0's DT properties: compatible, then reg then the reset of properties

v2 -> v3:
- Previously [PATCH 5]
- Check value of `atmel,usart-mode` instead of the node regex
- Define all properties top level and disallow them explicitly for other type,
since additionalProperties:false conflicts with referencing other schemas
- Remove useless else if: after else:


v3 -> v4:
- add R-b tag, this was previously [PATCH 6]


v4 -> v5:
- Nothing



 .../devicetree/bindings/mfd/atmel-usart.txt   |  98 ----------
 .../bindings/serial/atmel,at91-usart.yaml     | 182 ++++++++++++++++++
 2 files changed, 182 insertions(+), 98 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-usart.txt
 create mode 100644 Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml

diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt
deleted file mode 100644
index a09133066aff..000000000000
--- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
-
-Required properties for USART:
-- compatible: Should be one of the following:
-	- "atmel,at91rm9200-usart"
-	- "atmel,at91sam9260-usart"
-	- "microchip,sam9x60-usart"
-	- "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"
-	- "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
-	- "microchip,sam9x60-dbgu", "microchip,sam9x60-usart"
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt
-- clock-names: tuple listing input clock names.
-	Required elements: "usart"
-- clocks: phandles to input clocks.
-
-Required properties for USART in SPI mode:
-- #size-cells      : Must be <0>
-- #address-cells   : Must be <1>
-- cs-gpios: chipselects (internal cs not supported)
-- atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h)
-
-Optional properties in serial and SPI mode:
-- dma bindings for dma transfer:
-	- dmas: DMA specifier, consisting of a phandle to DMA controller node,
-		memory peripheral interface and USART DMA channel ID, FIFO configuration.
-		The order of DMA channels is fixed. The first DMA channel must be TX
-		associated channel and the second one must be RX associated channel.
-		Refer to dma.txt and atmel-dma.txt for details.
-	- dma-names: "tx" for TX channel.
-		     "rx" for RX channel.
-		     The order of dma-names is also fixed. The first name must be "tx"
-		     and the second one must be "rx" as in the examples below.
-
-Optional properties in serial mode:
-- atmel,use-dma-rx: use of PDC or DMA for receiving data
-- atmel,use-dma-tx: use of PDC or DMA for transmitting data
-- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively.
-  It will use specified PIO instead of the peripheral function pin for the USART feature.
-  If unsure, don't specify this property.
-- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
-  capable USARTs.
-- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt
-
-<chip> compatible description:
-- at91rm9200:  legacy USART support
-- at91sam9260: generic USART implementation for SAM9 SoCs
-
-Example:
-- use PDC:
-	usart0: serial@fff8c000 {
-		compatible = "atmel,at91sam9260-usart";
-		reg = <0xfff8c000 0x4000>;
-		interrupts = <7>;
-		clocks = <&usart0_clk>;
-		clock-names = "usart";
-		atmel,use-dma-rx;
-		atmel,use-dma-tx;
-		rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
-		cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
-		dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>;
-		dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
-		dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>;
-		rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>;
-	};
-
-- use DMA:
-	usart0: serial@f001c000 {
-		compatible = "atmel,at91sam9260-usart";
-		reg = <0xf001c000 0x100>;
-		interrupts = <12 4 5>;
-		clocks = <&usart0_clk>;
-		clock-names = "usart";
-		atmel,use-dma-rx;
-		atmel,use-dma-tx;
-		dmas = <&dma0 2 0x3>,
-		       <&dma0 2 0x204>;
-		dma-names = "tx", "rx";
-		atmel,fifo-size = <32>;
-	};
-
-- SPI mode:
-	#include <dt-bindings/mfd/at91-usart.h>
-
-	spi0: spi@f001c000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart";
-		atmel,usart-mode = <AT91_USART_MODE_SPI>;
-		reg = <0xf001c000 0x100>;
-		interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
-		clocks = <&usart0_clk>;
-		clock-names = "usart";
-		dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
-		       <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
-		dma-names = "tx", "rx";
-		cs-gpios = <&pioB 3 0>;
-	};
diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
new file mode 100644
index 000000000000..bb1b5ed431f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
+
+maintainers:
+  - Richard Genoud <richard.genoud@gmail.com>
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - atmel,at91rm9200-usart
+          - atmel,at91sam9260-usart
+          - microchip,sam9x60-usart
+      - items:
+          - const: atmel,at91rm9200-dbgu
+          - const: atmel,at91rm9200-usart
+      - items:
+          - const: atmel,at91sam9260-dbgu
+          - const: atmel,at91sam9260-usart
+      - items:
+          - const: microchip,sam9x60-dbgu
+          - const: microchip,sam9x60-usart
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clock-names:
+    const: usart
+
+  clocks:
+    maxItems: 1
+
+  dmas:
+    items:
+      - description: TX DMA Channel
+      - description: RX DMA Channel
+
+  dma-names:
+    items:
+      - const: tx
+      - const: rx
+
+  atmel,usart-mode:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Must be either <AT91_USART_MODE_SPI> for SPI or
+      <AT91_USART_MODE_SERIAL> for USART (found in dt-bindings/mfd/at91-usart.h).
+    enum: [ 0, 1 ]
+
+  atmel,use-dma-rx:
+    type: boolean
+    description: use of PDC or DMA for receiving data
+
+  atmel,use-dma-tx:
+    type: boolean
+    description: use of PDC or DMA for transmitting data
+
+  atmel,fifo-size:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Maximum number of data the RX and TX FIFOs can store for FIFO
+      capable USARTS.
+    enum: [ 16, 32 ]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clock-names
+  - clocks
+  - atmel,usart-mode
+
+allOf:
+  - if:
+      properties:
+        atmel,usart-mode:
+          const: 1
+    then:
+      allOf:
+        - $ref: /schemas/spi/spi-controller.yaml#
+
+      properties:
+        atmel,use-dma-rx: false
+
+        atmel,use-dma-tx: false
+
+        atmel,fifo-size: false
+
+        "#size-cells":
+          const: 0
+
+        "#address-cells":
+          const: 1
+
+      required:
+        - "#size-cells"
+        - "#address-cells"
+
+    else:
+      allOf:
+        - $ref: /schemas/serial/serial.yaml#
+        - $ref: /schemas/serial/rs485.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/mfd/at91-usart.h>
+    #include <dt-bindings/dma/at91.h>
+
+    /* use PDC */
+    usart0: serial@fff8c000 {
+        compatible = "atmel,at91sam9260-usart";
+        reg = <0xfff8c000 0x4000>;
+        atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+        interrupts = <7>;
+        clocks = <&usart0_clk>;
+        clock-names = "usart";
+        atmel,use-dma-rx;
+        atmel,use-dma-tx;
+        rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
+        cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
+        dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>;
+        dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
+        dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>;
+        rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>;
+    };
+
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/mfd/at91-usart.h>
+    #include <dt-bindings/dma/at91.h>
+
+    /* use DMA */
+    usart1: serial@f001c000 {
+        compatible = "atmel,at91sam9260-usart";
+        reg = <0xf001c000 0x100>;
+        atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+        interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
+        clocks = <&usart0_clk>;
+        clock-names = "usart";
+        atmel,use-dma-rx;
+        atmel,use-dma-tx;
+        dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
+               <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+        dma-names = "tx", "rx";
+        atmel,fifo-size = <32>;
+    };
+
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/mfd/at91-usart.h>
+    #include <dt-bindings/dma/at91.h>
+
+    /* SPI mode */
+    spi0: spi@f001c000 {
+        compatible = "atmel,at91sam9260-usart";
+        reg = <0xf001c000 0x100>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        atmel,usart-mode = <AT91_USART_MODE_SPI>;
+        interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
+        clocks = <&usart0_clk>;
+        clock-names = "usart";
+        dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
+               <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
+        dma-names = "tx", "rx";
+        cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
+    };
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v5 3/9] dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to SAM9X60
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 2/9] dt-bindings: serial: atmel,at91-usart: convert to json-schema Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 4/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding Sergiu Moga
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga, Krzysztof Kozlowski

Require SAM9260 fallback compatible for SAM9X60, because SAM9X60 is
fully compatible with SAM9260 and Linux driver requires the latter.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---



v1 -> v2:
- Nothing, this patch was not here before


v2 -> v3:
- Use the commit message suggested by Krzysztof Kozlowski



v3 -> v4:
- add A-b tag, this was previously [PATCH 7]



v4 -> v5:
- Nothing



 Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
index bb1b5ed431f7..4da642763bef 100644
--- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
+++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
@@ -26,6 +26,8 @@ properties:
       - items:
           - const: microchip,sam9x60-dbgu
           - const: microchip,sam9x60-usart
+          - const: atmel,at91sam9260-dbgu
+          - const: atmel,at91sam9260-usart
 
   reg:
     maxItems: 1
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v5 4/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
                   ` (2 preceding siblings ...)
  2022-09-22 11:33 ` [PATCH v5 3/9] dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to SAM9X60 Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 5/9] dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART clock Sergiu Moga
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga, Krzysztof Kozlowski

FLEXCOM, among other functionalities, has the ability to offer the USART
serial communication protocol. To have the FLEXCOM binding properly
validate its USART children nodes, we must reference the correct binding.
To differentiate between the SPI of FLEXCOM and the SPI of USART in SPI
mode, use the compatible string.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---


v1 -> v2:
- Nothing


v2 -> v3:
- Previously [PATCH 7]
- Compare devices based on the compatible instead of the clock


v3 -> v4:
- add A-b tag, this was previously [PATCH 8]



v4 -> v5:
- Nothing



 .../bindings/mfd/atmel,sama5d2-flexcom.yaml      | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
index f283cfd84b2d..0ebe624c2d32 100644
--- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
+++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
@@ -72,13 +72,21 @@ properties:
 
 patternProperties:
   "^serial@[0-9a-f]+$":
-    type: object
+    $ref: /schemas/serial/atmel,at91-usart.yaml
     description:
-      Child node describing USART. See atmel-usart.txt for details
-      of USART bindings.
+      Child node describing USART.
 
   "^spi@[0-9a-f]+$":
-    $ref: /schemas/spi/atmel,at91rm9200-spi.yaml
+    allOf:
+      - if:
+          properties:
+            compatible:
+              contains:
+                const: atmel,at91sam9260-usart
+        then:
+          $ref: /schemas/serial/atmel,at91-usart.yaml
+        else:
+          $ref: /schemas/spi/atmel,at91rm9200-spi.yaml
     description:
       Child node describing SPI.
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v5 5/9] dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART clock
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
                   ` (3 preceding siblings ...)
  2022-09-22 11:33 ` [PATCH v5 4/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART Sergiu Moga
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga, Krzysztof Kozlowski

The Devicetree nodes for FLEXCOM's USART can also have an alternative
clock source for the baudrate generator (other than the peripheral
clock), namely the Generick Clock. Thus make the binding aware of
this clock that someone may place in the clock related
properties of the USART node.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---



v1 -> v2:
- Nothing, this patch was not here before


v2 -> v3:
- Nothing, Previously this was [PATCH 13]


v3 -> v4:
- Add A-b tag, this was previously [PATCH 9]



v4 -> v5:
- Nothing



 .../devicetree/bindings/serial/atmel,at91-usart.yaml   | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
index 4da642763bef..30b2131b5860 100644
--- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
+++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
@@ -36,10 +36,16 @@ properties:
     maxItems: 1
 
   clock-names:
-    const: usart
+    minItems: 1
+    items:
+      - const: usart
+      - const: gclk
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: USART Peripheral Clock
+      - description: USART Generic Clock
 
   dmas:
     items:
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
                   ` (4 preceding siblings ...)
  2022-09-22 11:33 ` [PATCH v5 5/9] dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART clock Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-30  7:22   ` Claudiu.Beznea
  2022-09-22 11:33 ` [PATCH v5 7/9] tty: serial: atmel: Only divide Clock Divisor if the IP is USART Sergiu Moga
                   ` (2 subsequent siblings)
  8 siblings, 1 reply; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga

When clearing the mode of the serial IP inside the atmel_set_termios()
method, make sure that the difference between the bitfields placement
of the UART IP's and USART IP's is taken into account, as some of
them overlap with each other. For example, ATMEL_UA_BRSRCCK overlaps
with ATMEL_US_NBSTOP and ATMEL_US_USCLKS overlaps with ATMEL_UA_FILTER.

Furthermore, add definitions for the Baud Rate Source Clock and the
Filter bitfields of the Mode Register of UART IP's, since they were
missing.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---


v1 -> v5:
- This patch was not here before but it also includes the previous patch:
`[PATCH v4 7/9] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register`
squashed into it and define BRSRCCK as a bitfield instead of a bitmask,
since it is only 1 bit.



 drivers/tty/serial/atmel_serial.c | 7 +++++--
 drivers/tty/serial/atmel_serial.h | 2 ++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index ab4a9dfae07d..e3e14cb7668b 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -2134,8 +2134,11 @@ static void atmel_set_termios(struct uart_port *port,
 	mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
 
 	/* reset the mode, clock divisor, parity, stop bits and data size */
-	mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
-		  ATMEL_US_PAR | ATMEL_US_USMODE);
+	if (atmel_port->is_usart)
+		mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
+			  ATMEL_US_USCLKS | ATMEL_US_USMODE);
+	else
+		mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
 
 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
 
diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
index 0d8a0f9cc5c3..2a525b58e11a 100644
--- a/drivers/tty/serial/atmel_serial.h
+++ b/drivers/tty/serial/atmel_serial.h
@@ -50,6 +50,7 @@
 #define		ATMEL_US_USCLKS_MCK		(0 <<  4)
 #define		ATMEL_US_USCLKS_MCK_DIV8	(1 <<  4)
 #define		ATMEL_US_USCLKS_SCK		(3 <<  4)
+#define	ATMEL_UA_FILTER		BIT(4)
 #define	ATMEL_US_CHRL		GENMASK(7, 6)	/* Character Length */
 #define		ATMEL_US_CHRL_5			(0 <<  6)
 #define		ATMEL_US_CHRL_6			(1 <<  6)
@@ -67,6 +68,7 @@
 #define		ATMEL_US_NBSTOP_1		(0 << 12)
 #define		ATMEL_US_NBSTOP_1_5		(1 << 12)
 #define		ATMEL_US_NBSTOP_2		(2 << 12)
+#define	ATMEL_UA_BRSRCCK	BIT(12)	/* Clock Selection for UART */
 #define	ATMEL_US_CHMODE		GENMASK(15, 14)	/* Channel Mode */
 #define		ATMEL_US_CHMODE_NORMAL		(0 << 14)
 #define		ATMEL_US_CHMODE_ECHO		(1 << 14)
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v5 7/9] tty: serial: atmel: Only divide Clock Divisor if the IP is USART
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
                   ` (5 preceding siblings ...)
  2022-09-22 11:33 ` [PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-30  7:22   ` Claudiu.Beznea
  2022-09-22 11:33 ` [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK Sergiu Moga
  2022-09-22 11:33 ` [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET Sergiu Moga
  8 siblings, 1 reply; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga, Ilpo Järvinen

Make sure that the driver only divides the clock divisor if the
IP handled at that point is USART, since UART IP's do not support
implicit peripheral clock division. Instead, in the case of UART,
go with the highest possible clock divisor.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---


v1 -> v2:
- Nothing, this patch was not here before and is mainly meant as both cleanup
and as a way to introduce a new field into struct atmel_uart_port that will be
used by the last patch to diferentiate between USART and UART regarding the
location of the Baudrate Clock Source bitmask.



v2 -> v3:
- Use ATMEL_US_CD instead of 65535
- Previously [PATCH 10]



v3 -> v4:
- Use min_t instead of &
- Previously [PATCH 12]


v4 -> v5:
- Added R-b tag



 drivers/tty/serial/atmel_serial.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index e3e14cb7668b..acbf6b82d687 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -150,6 +150,7 @@ struct atmel_uart_port {
 	u32			rts_low;
 	bool			ms_irq_enabled;
 	u32			rtor;	/* address of receiver timeout register if it exists */
+	bool			is_usart;
 	bool			has_frac_baudrate;
 	bool			has_hw_timer;
 	struct timer_list	uart_timer;
@@ -1825,6 +1826,7 @@ static void atmel_get_ip_name(struct uart_port *port)
 	 */
 	atmel_port->has_frac_baudrate = false;
 	atmel_port->has_hw_timer = false;
+	atmel_port->is_usart = false;
 
 	if (name == new_uart) {
 		dev_dbg(port->dev, "Uart with hw timer");
@@ -1834,6 +1836,7 @@ static void atmel_get_ip_name(struct uart_port *port)
 		dev_dbg(port->dev, "Usart\n");
 		atmel_port->has_frac_baudrate = true;
 		atmel_port->has_hw_timer = true;
+		atmel_port->is_usart = true;
 		atmel_port->rtor = ATMEL_US_RTOR;
 		version = atmel_uart_readl(port, ATMEL_US_VERSION);
 		switch (version) {
@@ -1863,6 +1866,7 @@ static void atmel_get_ip_name(struct uart_port *port)
 			dev_dbg(port->dev, "This version is usart\n");
 			atmel_port->has_frac_baudrate = true;
 			atmel_port->has_hw_timer = true;
+			atmel_port->is_usart = true;
 			atmel_port->rtor = ATMEL_US_RTOR;
 			break;
 		case 0x203:
@@ -2286,10 +2290,21 @@ static void atmel_set_termios(struct uart_port *port,
 		cd = uart_get_divisor(port, baud);
 	}
 
-	if (cd > 65535) {	/* BRGR is 16-bit, so switch to slower clock */
+	/*
+	 * If the current value of the Clock Divisor surpasses the 16 bit
+	 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
+	 * Clock implicitly divided by 8.
+	 * If the IP is UART however, keep the highest possible value for
+	 * the CD and avoid needless division of CD, since UART IP's do not
+	 * support implicit division of the Peripheral Clock.
+	 */
+	if (atmel_port->is_usart && cd > ATMEL_US_CD) {
 		cd /= 8;
 		mode |= ATMEL_US_USCLKS_MCK_DIV8;
+	} else {
+		cd = min_t(unsigned int, cd, ATMEL_US_CD);
 	}
+
 	quot = cd | fp << ATMEL_US_FP_OFFSET;
 
 	if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
                   ` (6 preceding siblings ...)
  2022-09-22 11:33 ` [PATCH v5 7/9] tty: serial: atmel: Only divide Clock Divisor if the IP is USART Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-30  7:23   ` Claudiu.Beznea
  2022-09-22 11:33 ` [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET Sergiu Moga
  8 siblings, 1 reply; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga

Previously, the atmel serial driver did not take into account the
possibility of using the more customizable generic clock as its
baudrate generator. Unless there is a Fractional Part available to
increase accuracy, there is a high chance that we may be able to
generate a baudrate closer to the desired one by using the GCLK as the
clock source. Now, depending on the error rate between
the desired baudrate and the actual baudrate, the serial driver will
fallback on the generic clock. The generic clock must be provided
in the DT node of the serial that may need a more flexible clock source.

Furthermore, define the bit that represents the choice of having GCLK
as a baudrate source clock inside the USCLKS bitmask of the Mode Register
of USART IP's.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---




v1 -> v2:
- take into account the different placement of the baudrate clock source
into the IP's Mode Register (USART vs UART)
- don't check for atmel_port->gclk != NULL
- use clk_round_rate instead of clk_set_rate + clk_get_rate
- remove clk_disable_unprepare from the end of the probe method



v2 -> v3:
- add the error rate calculation function as an inline function instead of
a macro definition
- add `gclk_fail` goto
- replace `goto err` with `goto err_clk_disable_unprepare;`



v3 -> v4:
- Nothing, this was previously [PATCH 14]



v4 -> v5:
- Squashed the previous
`[PATCH v4 6/9] tty: serial: atmel: Define GCLK as USART baudrate source clock`
into this current commit
- No more BRSRCCK bitmask as it is only 1 bit



 drivers/tty/serial/atmel_serial.c | 58 ++++++++++++++++++++++++++++++-
 drivers/tty/serial/atmel_serial.h |  1 +
 2 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index acbf6b82d687..bd07f79a2df9 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/console.h>
 #include <linux/sysrq.h>
 #include <linux/tty_flip.h>
@@ -110,6 +111,7 @@ struct atmel_uart_char {
 struct atmel_uart_port {
 	struct uart_port	uart;		/* uart */
 	struct clk		*clk;		/* uart clock */
+	struct clk		*gclk;		/* uart generic clock */
 	int			may_wakeup;	/* cached value of device_may_wakeup for times we need to disable it */
 	u32			backup_imr;	/* IMR saved during suspend */
 	int			break_active;	/* break being received */
@@ -229,6 +231,11 @@ static inline int atmel_uart_is_half_duplex(struct uart_port *port)
 		(port->iso7816.flags & SER_ISO7816_ENABLED);
 }
 
+static inline int atmel_error_rate(int desired_value, int actual_value)
+{
+	return 100 - (desired_value * 100) / actual_value;
+}
+
 #ifdef CONFIG_SERIAL_ATMEL_PDC
 static bool atmel_use_pdc_rx(struct uart_port *port)
 {
@@ -2117,6 +2124,8 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state,
 		 * This is called on uart_close() or a suspend event.
 		 */
 		clk_disable_unprepare(atmel_port->clk);
+		if (__clk_is_enabled(atmel_port->gclk))
+			clk_disable_unprepare(atmel_port->gclk);
 		break;
 	default:
 		dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
@@ -2132,7 +2141,9 @@ static void atmel_set_termios(struct uart_port *port,
 {
 	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 	unsigned long flags;
-	unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
+	unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
+	unsigned int baud, actual_baud, gclk_rate;
+	int ret;
 
 	/* save the current mode register */
 	mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
@@ -2305,6 +2316,45 @@ static void atmel_set_termios(struct uart_port *port,
 		cd = min_t(unsigned int, cd, ATMEL_US_CD);
 	}
 
+	/*
+	 * If there is no Fractional Part, there is a high chance that
+	 * we may be able to generate a baudrate closer to the desired one
+	 * if we use the GCLK as the clock source driving the baudrate
+	 * generator.
+	 */
+	if (!atmel_port->has_frac_baudrate) {
+		if (__clk_is_enabled(atmel_port->gclk))
+			clk_disable_unprepare(atmel_port->gclk);
+		gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
+		actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
+		if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
+		    abs(atmel_error_rate(baud, gclk_rate / 16))) {
+			clk_set_rate(atmel_port->gclk, 16 * baud);
+			ret = clk_prepare_enable(atmel_port->gclk);
+			if (ret)
+				goto gclk_fail;
+
+			if (atmel_port->is_usart) {
+				mode &= ~ATMEL_US_USCLKS;
+				mode |= ATMEL_US_USCLKS_GCLK;
+			} else {
+				mode |= ATMEL_UA_BRSRCCK;
+			}
+
+			/*
+			 * Set the Clock Divisor for GCLK to 1.
+			 * Since we were able to generate the smallest
+			 * multiple of the desired baudrate times 16,
+			 * then we surely can generate a bigger multiple
+			 * with the exact error rate for an equally increased
+			 * CD. Thus no need to take into account
+			 * a higher value for CD.
+			 */
+			cd = 1;
+		}
+	}
+
+gclk_fail:
 	quot = cd | fp << ATMEL_US_FP_OFFSET;
 
 	if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
@@ -2900,6 +2950,12 @@ static int atmel_serial_probe(struct platform_device *pdev)
 	if (ret)
 		goto err;
 
+	atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
+	if (IS_ERR(atmel_port->gclk)) {
+		ret = PTR_ERR(atmel_port->gclk);
+		goto err_clk_disable_unprepare;
+	}
+
 	ret = atmel_init_port(atmel_port, pdev);
 	if (ret)
 		goto err_clk_disable_unprepare;
diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
index 2a525b58e11a..0fcadbeabc6c 100644
--- a/drivers/tty/serial/atmel_serial.h
+++ b/drivers/tty/serial/atmel_serial.h
@@ -49,6 +49,7 @@
 #define	ATMEL_US_USCLKS		GENMASK(5, 4)	/* Clock Selection */
 #define		ATMEL_US_USCLKS_MCK		(0 <<  4)
 #define		ATMEL_US_USCLKS_MCK_DIV8	(1 <<  4)
+#define		ATMEL_US_USCLKS_GCLK		(2 <<  4)
 #define		ATMEL_US_USCLKS_SCK		(3 <<  4)
 #define	ATMEL_UA_FILTER		BIT(4)
 #define	ATMEL_US_CHRL		GENMASK(7, 6)	/* Character Length */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET
  2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
                   ` (7 preceding siblings ...)
  2022-09-22 11:33 ` [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK Sergiu Moga
@ 2022-09-22 11:33 ` Sergiu Moga
  2022-09-22 12:12   ` Ilpo Järvinen
  2022-09-30  7:23   ` Claudiu.Beznea
  8 siblings, 2 replies; 20+ messages in thread
From: Sergiu Moga @ 2022-09-22 11:33 UTC (permalink / raw)
  To: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Sergiu Moga

Convert all open-coded instances of bitfields retrieval/setting
to FIELD_PREP/FIELD_GET where possible.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
---


v1 -> v5:
- Nothing, this patch was not here before



 drivers/tty/serial/atmel_serial.h | 74 ++++++++++++++++---------------
 1 file changed, 38 insertions(+), 36 deletions(-)

diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
index 0fcadbeabc6c..87f8f7996307 100644
--- a/drivers/tty/serial/atmel_serial.h
+++ b/drivers/tty/serial/atmel_serial.h
@@ -9,6 +9,8 @@
  * Based on AT91RM9200 datasheet revision E.
  */
 
+#include <linux/bitfield.h>
+
 #ifndef ATMEL_SERIAL_H
 #define ATMEL_SERIAL_H
 
@@ -39,42 +41,42 @@
 
 #define ATMEL_US_MR		0x04	/* Mode Register */
 #define	ATMEL_US_USMODE		GENMASK(3, 0)	/* Mode of the USART */
-#define		ATMEL_US_USMODE_NORMAL		0
-#define		ATMEL_US_USMODE_RS485		1
-#define		ATMEL_US_USMODE_HWHS		2
-#define		ATMEL_US_USMODE_MODEM		3
-#define		ATMEL_US_USMODE_ISO7816_T0	4
-#define		ATMEL_US_USMODE_ISO7816_T1	6
-#define		ATMEL_US_USMODE_IRDA		8
+#define		ATMEL_US_USMODE_NORMAL		FIELD_PREP(ATMEL_US_USMODE, 0)
+#define		ATMEL_US_USMODE_RS485		FIELD_PREP(ATMEL_US_USMODE, 1)
+#define		ATMEL_US_USMODE_HWHS		FIELD_PREP(ATMEL_US_USMODE, 2)
+#define		ATMEL_US_USMODE_MODEM		FIELD_PREP(ATMEL_US_USMODE, 3)
+#define		ATMEL_US_USMODE_ISO7816_T0	FIELD_PREP(ATMEL_US_USMODE, 4)
+#define		ATMEL_US_USMODE_ISO7816_T1	FIELD_PREP(ATMEL_US_USMODE, 6)
+#define		ATMEL_US_USMODE_IRDA		FIELD_PREP(ATMEL_US_USMODE, 8)
 #define	ATMEL_US_USCLKS		GENMASK(5, 4)	/* Clock Selection */
-#define		ATMEL_US_USCLKS_MCK		(0 <<  4)
-#define		ATMEL_US_USCLKS_MCK_DIV8	(1 <<  4)
-#define		ATMEL_US_USCLKS_GCLK		(2 <<  4)
-#define		ATMEL_US_USCLKS_SCK		(3 <<  4)
+#define		ATMEL_US_USCLKS_MCK		FIELD_PREP(ATMEL_US_USCLKS, 0)
+#define		ATMEL_US_USCLKS_MCK_DIV8	FIELD_PREP(ATMEL_US_USCLKS, 1)
+#define		ATMEL_US_USCLKS_GCLK		FIELD_PREP(ATMEL_US_USCLKS, 2)
+#define		ATMEL_US_USCLKS_SCK		FIELD_PREP(ATMEL_US_USCLKS, 3)
 #define	ATMEL_UA_FILTER		BIT(4)
 #define	ATMEL_US_CHRL		GENMASK(7, 6)	/* Character Length */
-#define		ATMEL_US_CHRL_5			(0 <<  6)
-#define		ATMEL_US_CHRL_6			(1 <<  6)
-#define		ATMEL_US_CHRL_7			(2 <<  6)
-#define		ATMEL_US_CHRL_8			(3 <<  6)
+#define		ATMEL_US_CHRL_5			FIELD_PREP(ATMEL_US_CHRL, 0)
+#define		ATMEL_US_CHRL_6			FIELD_PREP(ATMEL_US_CHRL, 1)
+#define		ATMEL_US_CHRL_7			FIELD_PREP(ATMEL_US_CHRL, 2)
+#define		ATMEL_US_CHRL_8			FIELD_PREP(ATMEL_US_CHRL, 3)
 #define	ATMEL_US_SYNC		BIT(8)		/* Synchronous Mode Select */
 #define	ATMEL_US_PAR		GENMASK(11, 9)	/* Parity Type */
-#define		ATMEL_US_PAR_EVEN		(0 <<  9)
-#define		ATMEL_US_PAR_ODD		(1 <<  9)
-#define		ATMEL_US_PAR_SPACE		(2 <<  9)
-#define		ATMEL_US_PAR_MARK		(3 <<  9)
-#define		ATMEL_US_PAR_NONE		(4 <<  9)
-#define		ATMEL_US_PAR_MULTI_DROP		(6 <<  9)
+#define		ATMEL_US_PAR_EVEN		FIELD_PREP(ATMEL_US_PAR, 0)
+#define		ATMEL_US_PAR_ODD		FIELD_PREP(ATMEL_US_PAR, 1)
+#define		ATMEL_US_PAR_SPACE		FIELD_PREP(ATMEL_US_PAR, 2)
+#define		ATMEL_US_PAR_MARK		FIELD_PREP(ATMEL_US_PAR, 3)
+#define		ATMEL_US_PAR_NONE		FIELD_PREP(ATMEL_US_PAR, 4)
+#define		ATMEL_US_PAR_MULTI_DROP		FIELD_PREP(ATMEL_US_PAR, 6)
 #define	ATMEL_US_NBSTOP		GENMASK(13, 12)	/* Number of Stop Bits */
-#define		ATMEL_US_NBSTOP_1		(0 << 12)
-#define		ATMEL_US_NBSTOP_1_5		(1 << 12)
-#define		ATMEL_US_NBSTOP_2		(2 << 12)
+#define		ATMEL_US_NBSTOP_1		FIELD_PREP(ATMEL_US_NBSTOP, 0)
+#define		ATMEL_US_NBSTOP_1_5		FIELD_PREP(ATMEL_US_NBSTOP, 1)
+#define		ATMEL_US_NBSTOP_2		FIELD_PREP(ATMEL_US_NBSTOP, 2)
 #define	ATMEL_UA_BRSRCCK	BIT(12)	/* Clock Selection for UART */
 #define	ATMEL_US_CHMODE		GENMASK(15, 14)	/* Channel Mode */
-#define		ATMEL_US_CHMODE_NORMAL		(0 << 14)
-#define		ATMEL_US_CHMODE_ECHO		(1 << 14)
-#define		ATMEL_US_CHMODE_LOC_LOOP	(2 << 14)
-#define		ATMEL_US_CHMODE_REM_LOOP	(3 << 14)
+#define		ATMEL_US_CHMODE_NORMAL		FIELD_PREP(ATMEL_US_CHMODE, 0)
+#define		ATMEL_US_CHMODE_ECHO		FIELD_PREP(ATMEL_US_CHMODE, 1)
+#define		ATMEL_US_CHMODE_LOC_LOOP	FIELD_PREP(ATMEL_US_CHMODE, 2)
+#define		ATMEL_US_CHMODE_REM_LOOP	FIELD_PREP(ATMEL_US_CHMODE, 3)
 #define	ATMEL_US_MSBF		BIT(16)	/* Bit Order */
 #define	ATMEL_US_MODE9		BIT(17)	/* 9-bit Character Length */
 #define	ATMEL_US_CLKO		BIT(18)	/* Clock Output Select */
@@ -82,7 +84,7 @@
 #define	ATMEL_US_INACK		BIT(20)	/* Inhibit Non Acknowledge */
 #define	ATMEL_US_DSNACK		BIT(21)	/* Disable Successive NACK */
 #define	ATMEL_US_MAX_ITER_MASK	GENMASK(26, 24)	/* Max Iterations */
-#define	ATMEL_US_MAX_ITER(n)	(((n) << 24) & ATMEL_US_MAX_ITER_MASK)
+#define	ATMEL_US_MAX_ITER(n)	FIELD_PREP(ATMEL_US_MAX_ITER_MASK, (n))
 #define	ATMEL_US_FILTER		BIT(28)	/* Infrared Receive Line Filter */
 
 #define ATMEL_US_IER		0x08	/* Interrupt Enable Register */
@@ -134,19 +136,19 @@
 
 #define ATMEL_US_CMPR		0x90	/* Comparaison Register */
 #define ATMEL_US_FMR		0xa0	/* FIFO Mode Register */
-#define	ATMEL_US_TXRDYM(data)	(((data) & 0x3) << 0)	/* TX Ready Mode */
-#define	ATMEL_US_RXRDYM(data)	(((data) & 0x3) << 4)	/* RX Ready Mode */
+#define	ATMEL_US_TXRDYM(data)	FIELD_PREP(GENMASK(1, 0), (data))	/* TX Ready Mode */
+#define	ATMEL_US_RXRDYM(data)	FIELD_PREP(GENMASK(5, 4), (data))	/* RX Ready Mode */
 #define		ATMEL_US_ONE_DATA	0x0
 #define		ATMEL_US_TWO_DATA	0x1
 #define		ATMEL_US_FOUR_DATA	0x2
 #define	ATMEL_US_FRTSC		BIT(7)	/* FIFO RTS pin Control */
-#define	ATMEL_US_TXFTHRES(thr)	(((thr) & 0x3f) << 8)	/* TX FIFO Threshold */
-#define	ATMEL_US_RXFTHRES(thr)	(((thr) & 0x3f) << 16)	/* RX FIFO Threshold */
-#define	ATMEL_US_RXFTHRES2(thr)	(((thr) & 0x3f) << 24)	/* RX FIFO Threshold2 */
+#define	ATMEL_US_TXFTHRES(thr)	FIELD_PREP(GENMASK(13, 8), (thr))	/* TX FIFO Threshold */
+#define	ATMEL_US_RXFTHRES(thr)	FIELD_PREP(GENMASK(21, 16), (thr))	/* RX FIFO Threshold */
+#define	ATMEL_US_RXFTHRES2(thr)	FIELD_PREP(GENMASK(29, 24), (thr))	/* RX FIFO Threshold2 */
 
 #define ATMEL_US_FLR		0xa4	/* FIFO Level Register */
-#define	ATMEL_US_TXFL(reg)	(((reg) >> 0) & 0x3f)	/* TX FIFO Level */
-#define	ATMEL_US_RXFL(reg)	(((reg) >> 16) & 0x3f)	/* RX FIFO Level */
+#define	ATMEL_US_TXFL(reg)	FIELD_GET(GENMASK(5, 0), (reg))		/* TX FIFO Level */
+#define	ATMEL_US_RXFL(reg)	FIELD_GET(GENMASK(21, 16), (reg))	/* RX FIFO Level */
 
 #define ATMEL_US_FIER		0xa8	/* FIFO Interrupt Enable Register */
 #define ATMEL_US_FIDR		0xac	/* FIFO Interrupt Disable Register */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET
  2022-09-22 11:33 ` [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET Sergiu Moga
@ 2022-09-22 12:12   ` Ilpo Järvinen
  2022-09-30  7:23   ` Claudiu.Beznea
  1 sibling, 0 replies; 20+ messages in thread
From: Ilpo Järvinen @ 2022-09-22 12:12 UTC (permalink / raw)
  To: Sergiu Moga
  Cc: lee, robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, Greg Kroah-Hartman, Jiri Slaby,
	kavyasree.kotagiri, devicetree, linux-arm-kernel, LKML,
	linux-spi, linux-serial

[-- Attachment #1: Type: text/plain, Size: 2775 bytes --]

On Thu, 22 Sep 2022, Sergiu Moga wrote:

> Convert all open-coded instances of bitfields retrieval/setting
> to FIELD_PREP/FIELD_GET where possible.
> 
> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

With one caveat below which I leave up to you to decide as it might be
more a matter of taste thing.

> @@ -82,7 +84,7 @@
>  #define	ATMEL_US_INACK		BIT(20)	/* Inhibit Non Acknowledge */
>  #define	ATMEL_US_DSNACK		BIT(21)	/* Disable Successive NACK */
>  #define	ATMEL_US_MAX_ITER_MASK	GENMASK(26, 24)	/* Max Iterations */
> -#define	ATMEL_US_MAX_ITER(n)	(((n) << 24) & ATMEL_US_MAX_ITER_MASK)
> +#define	ATMEL_US_MAX_ITER(n)	FIELD_PREP(ATMEL_US_MAX_ITER_MASK, (n))
>  #define	ATMEL_US_FILTER		BIT(28)	/* Infrared Receive Line Filter */
>  
>  #define ATMEL_US_IER		0x08	/* Interrupt Enable Register */
> @@ -134,19 +136,19 @@
>  
>  #define ATMEL_US_CMPR		0x90	/* Comparaison Register */
>  #define ATMEL_US_FMR		0xa0	/* FIFO Mode Register */
> -#define	ATMEL_US_TXRDYM(data)	(((data) & 0x3) << 0)	/* TX Ready Mode */
> -#define	ATMEL_US_RXRDYM(data)	(((data) & 0x3) << 4)	/* RX Ready Mode */
> +#define	ATMEL_US_TXRDYM(data)	FIELD_PREP(GENMASK(1, 0), (data))	/* TX Ready Mode */
> +#define	ATMEL_US_RXRDYM(data)	FIELD_PREP(GENMASK(5, 4), (data))	/* RX Ready Mode */
>  #define		ATMEL_US_ONE_DATA	0x0
>  #define		ATMEL_US_TWO_DATA	0x1
>  #define		ATMEL_US_FOUR_DATA	0x2
>  #define	ATMEL_US_FRTSC		BIT(7)	/* FIFO RTS pin Control */
> -#define	ATMEL_US_TXFTHRES(thr)	(((thr) & 0x3f) << 8)	/* TX FIFO Threshold */
> -#define	ATMEL_US_RXFTHRES(thr)	(((thr) & 0x3f) << 16)	/* RX FIFO Threshold */
> -#define	ATMEL_US_RXFTHRES2(thr)	(((thr) & 0x3f) << 24)	/* RX FIFO Threshold2 */
> +#define	ATMEL_US_TXFTHRES(thr)	FIELD_PREP(GENMASK(13, 8), (thr))	/* TX FIFO Threshold */
> +#define	ATMEL_US_RXFTHRES(thr)	FIELD_PREP(GENMASK(21, 16), (thr))	/* RX FIFO Threshold */
> +#define	ATMEL_US_RXFTHRES2(thr)	FIELD_PREP(GENMASK(29, 24), (thr))	/* RX FIFO Threshold2 */
>  
>  #define ATMEL_US_FLR		0xa4	/* FIFO Level Register */
> -#define	ATMEL_US_TXFL(reg)	(((reg) >> 0) & 0x3f)	/* TX FIFO Level */
> -#define	ATMEL_US_RXFL(reg)	(((reg) >> 16) & 0x3f)	/* RX FIFO Level */
> +#define	ATMEL_US_TXFL(reg)	FIELD_GET(GENMASK(5, 0), (reg))		/* TX FIFO Level */
> +#define	ATMEL_US_RXFL(reg)	FIELD_GET(GENMASK(21, 16), (reg))	/* RX FIFO Level */

I don't particularly like this kind of constructs. IMHO, all these would 
be nice after removing the macro argument and moving the FIELD_PREP() to 
.c file. That is,

.h:
#define ATMEL_US_RXFL	GENMASK(21, 16)

.c:
	... FIELD_PREP(ATMEL_US_RXFL, arg) ...

But I guess there might be differing opinions on it (and both are 
correct from purely technical perspective).

-- 
 i.

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding
  2022-09-22 11:33 ` [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Sergiu Moga
@ 2022-09-28 15:03   ` Lee Jones
  2022-09-28 15:07     ` Sergiu.Moga
  0 siblings, 1 reply; 20+ messages in thread
From: Lee Jones @ 2022-09-28 15:03 UTC (permalink / raw)
  To: Sergiu Moga
  Cc: robh+dt, krzysztof.kozlowski+dt, nicolas.ferre,
	alexandre.belloni, claudiu.beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, kavyasree.kotagiri,
	devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, Krzysztof Kozlowski

On Thu, 22 Sep 2022, Sergiu Moga wrote:

> Another functionality of FLEXCOM is that of SPI. In order for
> the proper validation of the SPI children nodes through the binding
> to occur, the proper binding for SPI must be referenced.
> 
> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> 
> 
> v1 -> v2:
> - use full schema paths
> 
> 
> v2 -> v3:
> - Added Reviewed-by tag, previously this was [PATCH 3]
> 
> 
> v3 -> v4:
> - Nothing, previously this was [PATCH 5]
> 
> 
> v4 -> v5:
> - Nothing
> 
> 
> 
>  .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml       | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)

Not sure how these can be handled.

I guess I cannot take these until the other patches are applied.

NB: The patch doesn't apply cleanly anyway, so will need to be rebased.

> diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
> index 0c80f4e98c54..f283cfd84b2d 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
> +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
> @@ -78,10 +78,9 @@ patternProperties:
>        of USART bindings.
>  
>    "^spi@[0-9a-f]+$":
> -    type: object
> +    $ref: /schemas/spi/atmel,at91rm9200-spi.yaml
>      description:
> -      Child node describing SPI. See ../spi/spi_atmel.txt for details
> -      of SPI bindings.
> +      Child node describing SPI.
>  
>    "^i2c@[0-9a-f]+$":
>      $ref: /schemas/i2c/atmel,at91sam-i2c.yaml

-- 
Lee Jones [李琼斯]

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding
  2022-09-28 15:03   ` Lee Jones
@ 2022-09-28 15:07     ` Sergiu.Moga
  2022-09-28 15:23       ` Lee Jones
  0 siblings, 1 reply; 20+ messages in thread
From: Sergiu.Moga @ 2022-09-28 15:07 UTC (permalink / raw)
  To: lee
  Cc: robh+dt, krzysztof.kozlowski+dt, Nicolas.Ferre,
	alexandre.belloni, Claudiu.Beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, Kavyasree.Kotagiri,
	devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, krzysztof.kozlowski

On 28.09.2022 18:03, Lee Jones wrote:
> On Thu, 22 Sep 2022, Sergiu Moga wrote:
> 
>> Another functionality of FLEXCOM is that of SPI. In order for
>> the proper validation of the SPI children nodes through the binding
>> to occur, the proper binding for SPI must be referenced.
>>
>> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>>
>>
>> v1 -> v2:
>> - use full schema paths
>>
>>
>> v2 -> v3:
>> - Added Reviewed-by tag, previously this was [PATCH 3]
>>
>>
>> v3 -> v4:
>> - Nothing, previously this was [PATCH 5]
>>
>>
>> v4 -> v5:
>> - Nothing
>>
>>
>>
>>   .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml       | 5 ++---
>>   1 file changed, 2 insertions(+), 3 deletions(-)
> 
> Not sure how these can be handled.
> 
> I guess I cannot take these until the other patches are applied.
> 
> NB: The patch doesn't apply cleanly anyway, so will need to be rebased.
> 


Hello,

The sama5d2-flexcom binding related patches are dependent on:
https://lore.kernel.org/linux-arm-kernel/20220916075744.1879428-1-kavyasree.kotagiri@microchip.com/

as specified in the cover letter.

Regards,
	Sergiu


>> diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
>> index 0c80f4e98c54..f283cfd84b2d 100644
>> --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
>> +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml
>> @@ -78,10 +78,9 @@ patternProperties:
>>         of USART bindings.
>>
>>     "^spi@[0-9a-f]+$":
>> -    type: object
>> +    $ref: /schemas/spi/atmel,at91rm9200-spi.yaml
>>       description:
>> -      Child node describing SPI. See ../spi/spi_atmel.txt for details
>> -      of SPI bindings.
>> +      Child node describing SPI.
>>
>>     "^i2c@[0-9a-f]+$":
>>       $ref: /schemas/i2c/atmel,at91sam-i2c.yaml
> 
> --
> Lee Jones [李琼斯]


^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding
  2022-09-28 15:07     ` Sergiu.Moga
@ 2022-09-28 15:23       ` Lee Jones
  2022-09-28 15:35         ` Sergiu.Moga
  0 siblings, 1 reply; 20+ messages in thread
From: Lee Jones @ 2022-09-28 15:23 UTC (permalink / raw)
  To: Sergiu.Moga
  Cc: robh+dt, krzysztof.kozlowski+dt, Nicolas.Ferre,
	alexandre.belloni, Claudiu.Beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, Kavyasree.Kotagiri,
	devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, krzysztof.kozlowski

On Wed, 28 Sep 2022, Sergiu.Moga@microchip.com wrote:

> On 28.09.2022 18:03, Lee Jones wrote:
> > On Thu, 22 Sep 2022, Sergiu Moga wrote:
> > 
> >> Another functionality of FLEXCOM is that of SPI. In order for
> >> the proper validation of the SPI children nodes through the binding
> >> to occur, the proper binding for SPI must be referenced.
> >>
> >> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >> ---
> >>
> >>
> >> v1 -> v2:
> >> - use full schema paths
> >>
> >>
> >> v2 -> v3:
> >> - Added Reviewed-by tag, previously this was [PATCH 3]
> >>
> >>
> >> v3 -> v4:
> >> - Nothing, previously this was [PATCH 5]
> >>
> >>
> >> v4 -> v5:
> >> - Nothing
> >>
> >>
> >>
> >>   .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml       | 5 ++---
> >>   1 file changed, 2 insertions(+), 3 deletions(-)
> > 
> > Not sure how these can be handled.
> > 
> > I guess I cannot take these until the other patches are applied.
> > 
> > NB: The patch doesn't apply cleanly anyway, so will need to be rebased.
> > 
> 
> 
> Hello,
> 
> The sama5d2-flexcom binding related patches are dependent on:
> https://lore.kernel.org/linux-arm-kernel/20220916075744.1879428-1-kavyasree.kotagiri@microchip.com/

I would be very cautious about relying on comments made in the
cover-letter.  Better to make this a hard requirement and place them
in the same patch-set.

-- 
Lee Jones [李琼斯]

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding
  2022-09-28 15:23       ` Lee Jones
@ 2022-09-28 15:35         ` Sergiu.Moga
  2022-10-24 12:25           ` Lee Jones
  0 siblings, 1 reply; 20+ messages in thread
From: Sergiu.Moga @ 2022-09-28 15:35 UTC (permalink / raw)
  To: lee
  Cc: robh+dt, krzysztof.kozlowski+dt, Nicolas.Ferre,
	alexandre.belloni, Claudiu.Beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, Kavyasree.Kotagiri,
	devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, krzysztof.kozlowski

On 28.09.2022 18:23, Lee Jones wrote:
> On Wed, 28 Sep 2022, Sergiu.Moga@microchip.com wrote:
> 
>> On 28.09.2022 18:03, Lee Jones wrote:
>>> On Thu, 22 Sep 2022, Sergiu Moga wrote:
>>>
>>>> Another functionality of FLEXCOM is that of SPI. In order for
>>>> the proper validation of the SPI children nodes through the binding
>>>> to occur, the proper binding for SPI must be referenced.
>>>>
>>>> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> ---
>>>>
>>>>
>>>> v1 -> v2:
>>>> - use full schema paths
>>>>
>>>>
>>>> v2 -> v3:
>>>> - Added Reviewed-by tag, previously this was [PATCH 3]
>>>>
>>>>
>>>> v3 -> v4:
>>>> - Nothing, previously this was [PATCH 5]
>>>>
>>>>
>>>> v4 -> v5:
>>>> - Nothing
>>>>
>>>>
>>>>
>>>>    .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml       | 5 ++---
>>>>    1 file changed, 2 insertions(+), 3 deletions(-)
>>>
>>> Not sure how these can be handled.
>>>
>>> I guess I cannot take these until the other patches are applied.
>>>
>>> NB: The patch doesn't apply cleanly anyway, so will need to be rebased.
>>>
>>
>>
>> Hello,
>>
>> The sama5d2-flexcom binding related patches are dependent on:
>> https://lore.kernel.org/linux-arm-kernel/20220916075744.1879428-1-kavyasree.kotagiri@microchip.com/
> 
> I would be very cautious about relying on comments made in the
> cover-letter.  Better to make this a hard requirement and place them
> in the same patch-set.
> 
> --
> Lee Jones [李琼斯]



Understood, my apologies, I will keep this in mind the next time this 
happens :).

Otherwise, by applying the patch series linked above, my sama5d2-flexcom 
patches should apply cleanly afterwards.

Thanks,
	Sergiu

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART
  2022-09-22 11:33 ` [PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART Sergiu Moga
@ 2022-09-30  7:22   ` Claudiu.Beznea
  0 siblings, 0 replies; 20+ messages in thread
From: Claudiu.Beznea @ 2022-09-30  7:22 UTC (permalink / raw)
  To: Sergiu.Moga, lee, robh+dt, krzysztof.kozlowski+dt, Nicolas.Ferre,
	alexandre.belloni, radu_nicolae.pirea, richard.genoud, gregkh,
	jirislaby, Kavyasree.Kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi, linux-serial

On 22.09.2022 14:33, Sergiu Moga wrote:
> When clearing the mode of the serial IP inside the atmel_set_termios()
> method, make sure that the difference between the bitfields placement
> of the UART IP's and USART IP's is taken into account, as some of
> them overlap with each other. For example, ATMEL_UA_BRSRCCK overlaps
> with ATMEL_US_NBSTOP and ATMEL_US_USCLKS overlaps with ATMEL_UA_FILTER.
> 
> Furthermore, add definitions for the Baud Rate Source Clock and the
> Filter bitfields of the Mode Register of UART IP's, since they were
> missing.
> 
> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
> 
> 
> v1 -> v5:
> - This patch was not here before but it also includes the previous patch:
> `[PATCH v4 7/9] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register`
> squashed into it and define BRSRCCK as a bitfield instead of a bitmask,
> since it is only 1 bit.
> 
> 
> 
>  drivers/tty/serial/atmel_serial.c | 7 +++++--
>  drivers/tty/serial/atmel_serial.h | 2 ++
>  2 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> index ab4a9dfae07d..e3e14cb7668b 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -2134,8 +2134,11 @@ static void atmel_set_termios(struct uart_port *port,
>  	mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
>  
>  	/* reset the mode, clock divisor, parity, stop bits and data size */
> -	mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
> -		  ATMEL_US_PAR | ATMEL_US_USMODE);
> +	if (atmel_port->is_usart)
> +		mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL |
> +			  ATMEL_US_USCLKS | ATMEL_US_USMODE);
> +	else
> +		mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER);
>  
>  	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
>  
> diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
> index 0d8a0f9cc5c3..2a525b58e11a 100644
> --- a/drivers/tty/serial/atmel_serial.h
> +++ b/drivers/tty/serial/atmel_serial.h
> @@ -50,6 +50,7 @@
>  #define		ATMEL_US_USCLKS_MCK		(0 <<  4)
>  #define		ATMEL_US_USCLKS_MCK_DIV8	(1 <<  4)
>  #define		ATMEL_US_USCLKS_SCK		(3 <<  4)
> +#define	ATMEL_UA_FILTER		BIT(4)
>  #define	ATMEL_US_CHRL		GENMASK(7, 6)	/* Character Length */
>  #define		ATMEL_US_CHRL_5			(0 <<  6)
>  #define		ATMEL_US_CHRL_6			(1 <<  6)
> @@ -67,6 +68,7 @@
>  #define		ATMEL_US_NBSTOP_1		(0 << 12)
>  #define		ATMEL_US_NBSTOP_1_5		(1 << 12)
>  #define		ATMEL_US_NBSTOP_2		(2 << 12)
> +#define	ATMEL_UA_BRSRCCK	BIT(12)	/* Clock Selection for UART */
>  #define	ATMEL_US_CHMODE		GENMASK(15, 14)	/* Channel Mode */
>  #define		ATMEL_US_CHMODE_NORMAL		(0 << 14)
>  #define		ATMEL_US_CHMODE_ECHO		(1 << 14)


^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 7/9] tty: serial: atmel: Only divide Clock Divisor if the IP is USART
  2022-09-22 11:33 ` [PATCH v5 7/9] tty: serial: atmel: Only divide Clock Divisor if the IP is USART Sergiu Moga
@ 2022-09-30  7:22   ` Claudiu.Beznea
  0 siblings, 0 replies; 20+ messages in thread
From: Claudiu.Beznea @ 2022-09-30  7:22 UTC (permalink / raw)
  To: Sergiu.Moga, lee, robh+dt, krzysztof.kozlowski+dt, Nicolas.Ferre,
	alexandre.belloni, radu_nicolae.pirea, richard.genoud, gregkh,
	jirislaby, Kavyasree.Kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, ilpo.jarvinen

On 22.09.2022 14:33, Sergiu Moga wrote:
> Make sure that the driver only divides the clock divisor if the
> IP handled at that point is USART, since UART IP's do not support
> implicit peripheral clock division. Instead, in the case of UART,
> go with the highest possible clock divisor.
> 
> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
> 
> 
> v1 -> v2:
> - Nothing, this patch was not here before and is mainly meant as both cleanup
> and as a way to introduce a new field into struct atmel_uart_port that will be
> used by the last patch to diferentiate between USART and UART regarding the
> location of the Baudrate Clock Source bitmask.
> 
> 
> 
> v2 -> v3:
> - Use ATMEL_US_CD instead of 65535
> - Previously [PATCH 10]
> 
> 
> 
> v3 -> v4:
> - Use min_t instead of &
> - Previously [PATCH 12]
> 
> 
> v4 -> v5:
> - Added R-b tag
> 
> 
> 
>  drivers/tty/serial/atmel_serial.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> index e3e14cb7668b..acbf6b82d687 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -150,6 +150,7 @@ struct atmel_uart_port {
>  	u32			rts_low;
>  	bool			ms_irq_enabled;
>  	u32			rtor;	/* address of receiver timeout register if it exists */
> +	bool			is_usart;
>  	bool			has_frac_baudrate;
>  	bool			has_hw_timer;
>  	struct timer_list	uart_timer;
> @@ -1825,6 +1826,7 @@ static void atmel_get_ip_name(struct uart_port *port)
>  	 */
>  	atmel_port->has_frac_baudrate = false;
>  	atmel_port->has_hw_timer = false;
> +	atmel_port->is_usart = false;
>  
>  	if (name == new_uart) {
>  		dev_dbg(port->dev, "Uart with hw timer");
> @@ -1834,6 +1836,7 @@ static void atmel_get_ip_name(struct uart_port *port)
>  		dev_dbg(port->dev, "Usart\n");
>  		atmel_port->has_frac_baudrate = true;
>  		atmel_port->has_hw_timer = true;
> +		atmel_port->is_usart = true;
>  		atmel_port->rtor = ATMEL_US_RTOR;
>  		version = atmel_uart_readl(port, ATMEL_US_VERSION);
>  		switch (version) {
> @@ -1863,6 +1866,7 @@ static void atmel_get_ip_name(struct uart_port *port)
>  			dev_dbg(port->dev, "This version is usart\n");
>  			atmel_port->has_frac_baudrate = true;
>  			atmel_port->has_hw_timer = true;
> +			atmel_port->is_usart = true;
>  			atmel_port->rtor = ATMEL_US_RTOR;
>  			break;
>  		case 0x203:
> @@ -2286,10 +2290,21 @@ static void atmel_set_termios(struct uart_port *port,
>  		cd = uart_get_divisor(port, baud);
>  	}
>  
> -	if (cd > 65535) {	/* BRGR is 16-bit, so switch to slower clock */
> +	/*
> +	 * If the current value of the Clock Divisor surpasses the 16 bit
> +	 * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral
> +	 * Clock implicitly divided by 8.
> +	 * If the IP is UART however, keep the highest possible value for
> +	 * the CD and avoid needless division of CD, since UART IP's do not
> +	 * support implicit division of the Peripheral Clock.
> +	 */
> +	if (atmel_port->is_usart && cd > ATMEL_US_CD) {
>  		cd /= 8;
>  		mode |= ATMEL_US_USCLKS_MCK_DIV8;
> +	} else {
> +		cd = min_t(unsigned int, cd, ATMEL_US_CD);
>  	}
> +
>  	quot = cd | fp << ATMEL_US_FP_OFFSET;
>  
>  	if (!(port->iso7816.flags & SER_ISO7816_ENABLED))


^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK
  2022-09-22 11:33 ` [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK Sergiu Moga
@ 2022-09-30  7:23   ` Claudiu.Beznea
  0 siblings, 0 replies; 20+ messages in thread
From: Claudiu.Beznea @ 2022-09-30  7:23 UTC (permalink / raw)
  To: Sergiu.Moga, lee, robh+dt, krzysztof.kozlowski+dt, Nicolas.Ferre,
	alexandre.belloni, radu_nicolae.pirea, richard.genoud, gregkh,
	jirislaby, Kavyasree.Kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi, linux-serial

On 22.09.2022 14:33, Sergiu Moga wrote:
> Previously, the atmel serial driver did not take into account the
> possibility of using the more customizable generic clock as its
> baudrate generator. Unless there is a Fractional Part available to
> increase accuracy, there is a high chance that we may be able to
> generate a baudrate closer to the desired one by using the GCLK as the
> clock source. Now, depending on the error rate between
> the desired baudrate and the actual baudrate, the serial driver will
> fallback on the generic clock. The generic clock must be provided
> in the DT node of the serial that may need a more flexible clock source.
> 
> Furthermore, define the bit that represents the choice of having GCLK
> as a baudrate source clock inside the USCLKS bitmask of the Mode Register
> of USART IP's.
> 
> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
> 
> 
> 
> 
> v1 -> v2:
> - take into account the different placement of the baudrate clock source
> into the IP's Mode Register (USART vs UART)
> - don't check for atmel_port->gclk != NULL
> - use clk_round_rate instead of clk_set_rate + clk_get_rate
> - remove clk_disable_unprepare from the end of the probe method
> 
> 
> 
> v2 -> v3:
> - add the error rate calculation function as an inline function instead of
> a macro definition
> - add `gclk_fail` goto
> - replace `goto err` with `goto err_clk_disable_unprepare;`
> 
> 
> 
> v3 -> v4:
> - Nothing, this was previously [PATCH 14]
> 
> 
> 
> v4 -> v5:
> - Squashed the previous
> `[PATCH v4 6/9] tty: serial: atmel: Define GCLK as USART baudrate source clock`
> into this current commit
> - No more BRSRCCK bitmask as it is only 1 bit
> 
> 
> 
>  drivers/tty/serial/atmel_serial.c | 58 ++++++++++++++++++++++++++++++-
>  drivers/tty/serial/atmel_serial.h |  1 +
>  2 files changed, 58 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> index acbf6b82d687..bd07f79a2df9 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -15,6 +15,7 @@
>  #include <linux/init.h>
>  #include <linux/serial.h>
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>  #include <linux/console.h>
>  #include <linux/sysrq.h>
>  #include <linux/tty_flip.h>
> @@ -110,6 +111,7 @@ struct atmel_uart_char {
>  struct atmel_uart_port {
>  	struct uart_port	uart;		/* uart */
>  	struct clk		*clk;		/* uart clock */
> +	struct clk		*gclk;		/* uart generic clock */
>  	int			may_wakeup;	/* cached value of device_may_wakeup for times we need to disable it */
>  	u32			backup_imr;	/* IMR saved during suspend */
>  	int			break_active;	/* break being received */
> @@ -229,6 +231,11 @@ static inline int atmel_uart_is_half_duplex(struct uart_port *port)
>  		(port->iso7816.flags & SER_ISO7816_ENABLED);
>  }
>  
> +static inline int atmel_error_rate(int desired_value, int actual_value)
> +{
> +	return 100 - (desired_value * 100) / actual_value;
> +}
> +
>  #ifdef CONFIG_SERIAL_ATMEL_PDC
>  static bool atmel_use_pdc_rx(struct uart_port *port)
>  {
> @@ -2117,6 +2124,8 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state,
>  		 * This is called on uart_close() or a suspend event.
>  		 */
>  		clk_disable_unprepare(atmel_port->clk);
> +		if (__clk_is_enabled(atmel_port->gclk))
> +			clk_disable_unprepare(atmel_port->gclk);
>  		break;
>  	default:
>  		dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
> @@ -2132,7 +2141,9 @@ static void atmel_set_termios(struct uart_port *port,
>  {
>  	struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
>  	unsigned long flags;
> -	unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
> +	unsigned int old_mode, mode, imr, quot, div, cd, fp = 0;
> +	unsigned int baud, actual_baud, gclk_rate;
> +	int ret;
>  
>  	/* save the current mode register */
>  	mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
> @@ -2305,6 +2316,45 @@ static void atmel_set_termios(struct uart_port *port,
>  		cd = min_t(unsigned int, cd, ATMEL_US_CD);
>  	}
>  
> +	/*
> +	 * If there is no Fractional Part, there is a high chance that
> +	 * we may be able to generate a baudrate closer to the desired one
> +	 * if we use the GCLK as the clock source driving the baudrate
> +	 * generator.
> +	 */
> +	if (!atmel_port->has_frac_baudrate) {
> +		if (__clk_is_enabled(atmel_port->gclk))
> +			clk_disable_unprepare(atmel_port->gclk);
> +		gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud);
> +		actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd);
> +		if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) >
> +		    abs(atmel_error_rate(baud, gclk_rate / 16))) {
> +			clk_set_rate(atmel_port->gclk, 16 * baud);
> +			ret = clk_prepare_enable(atmel_port->gclk);
> +			if (ret)
> +				goto gclk_fail;
> +
> +			if (atmel_port->is_usart) {
> +				mode &= ~ATMEL_US_USCLKS;
> +				mode |= ATMEL_US_USCLKS_GCLK;
> +			} else {
> +				mode |= ATMEL_UA_BRSRCCK;
> +			}
> +
> +			/*
> +			 * Set the Clock Divisor for GCLK to 1.
> +			 * Since we were able to generate the smallest
> +			 * multiple of the desired baudrate times 16,
> +			 * then we surely can generate a bigger multiple
> +			 * with the exact error rate for an equally increased
> +			 * CD. Thus no need to take into account
> +			 * a higher value for CD.
> +			 */
> +			cd = 1;
> +		}
> +	}
> +
> +gclk_fail:
>  	quot = cd | fp << ATMEL_US_FP_OFFSET;
>  
>  	if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
> @@ -2900,6 +2950,12 @@ static int atmel_serial_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err;
>  
> +	atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk");
> +	if (IS_ERR(atmel_port->gclk)) {
> +		ret = PTR_ERR(atmel_port->gclk);
> +		goto err_clk_disable_unprepare;
> +	}
> +
>  	ret = atmel_init_port(atmel_port, pdev);
>  	if (ret)
>  		goto err_clk_disable_unprepare;
> diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
> index 2a525b58e11a..0fcadbeabc6c 100644
> --- a/drivers/tty/serial/atmel_serial.h
> +++ b/drivers/tty/serial/atmel_serial.h
> @@ -49,6 +49,7 @@
>  #define	ATMEL_US_USCLKS		GENMASK(5, 4)	/* Clock Selection */
>  #define		ATMEL_US_USCLKS_MCK		(0 <<  4)
>  #define		ATMEL_US_USCLKS_MCK_DIV8	(1 <<  4)
> +#define		ATMEL_US_USCLKS_GCLK		(2 <<  4)
>  #define		ATMEL_US_USCLKS_SCK		(3 <<  4)
>  #define	ATMEL_UA_FILTER		BIT(4)
>  #define	ATMEL_US_CHRL		GENMASK(7, 6)	/* Character Length */


^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET
  2022-09-22 11:33 ` [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET Sergiu Moga
  2022-09-22 12:12   ` Ilpo Järvinen
@ 2022-09-30  7:23   ` Claudiu.Beznea
  1 sibling, 0 replies; 20+ messages in thread
From: Claudiu.Beznea @ 2022-09-30  7:23 UTC (permalink / raw)
  To: Sergiu.Moga, lee, robh+dt, krzysztof.kozlowski+dt, Nicolas.Ferre,
	alexandre.belloni, radu_nicolae.pirea, richard.genoud, gregkh,
	jirislaby, Kavyasree.Kotagiri
  Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi, linux-serial

On 22.09.2022 14:33, Sergiu Moga wrote:
> Convert all open-coded instances of bitfields retrieval/setting
> to FIELD_PREP/FIELD_GET where possible.
> 
> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
> 
> 
> v1 -> v5:
> - Nothing, this patch was not here before
> 
> 
> 
>  drivers/tty/serial/atmel_serial.h | 74 ++++++++++++++++---------------
>  1 file changed, 38 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h
> index 0fcadbeabc6c..87f8f7996307 100644
> --- a/drivers/tty/serial/atmel_serial.h
> +++ b/drivers/tty/serial/atmel_serial.h
> @@ -9,6 +9,8 @@
>   * Based on AT91RM9200 datasheet revision E.
>   */
>  
> +#include <linux/bitfield.h>
> +
>  #ifndef ATMEL_SERIAL_H
>  #define ATMEL_SERIAL_H
>  
> @@ -39,42 +41,42 @@
>  
>  #define ATMEL_US_MR		0x04	/* Mode Register */
>  #define	ATMEL_US_USMODE		GENMASK(3, 0)	/* Mode of the USART */
> -#define		ATMEL_US_USMODE_NORMAL		0
> -#define		ATMEL_US_USMODE_RS485		1
> -#define		ATMEL_US_USMODE_HWHS		2
> -#define		ATMEL_US_USMODE_MODEM		3
> -#define		ATMEL_US_USMODE_ISO7816_T0	4
> -#define		ATMEL_US_USMODE_ISO7816_T1	6
> -#define		ATMEL_US_USMODE_IRDA		8
> +#define		ATMEL_US_USMODE_NORMAL		FIELD_PREP(ATMEL_US_USMODE, 0)
> +#define		ATMEL_US_USMODE_RS485		FIELD_PREP(ATMEL_US_USMODE, 1)
> +#define		ATMEL_US_USMODE_HWHS		FIELD_PREP(ATMEL_US_USMODE, 2)
> +#define		ATMEL_US_USMODE_MODEM		FIELD_PREP(ATMEL_US_USMODE, 3)
> +#define		ATMEL_US_USMODE_ISO7816_T0	FIELD_PREP(ATMEL_US_USMODE, 4)
> +#define		ATMEL_US_USMODE_ISO7816_T1	FIELD_PREP(ATMEL_US_USMODE, 6)
> +#define		ATMEL_US_USMODE_IRDA		FIELD_PREP(ATMEL_US_USMODE, 8)
>  #define	ATMEL_US_USCLKS		GENMASK(5, 4)	/* Clock Selection */
> -#define		ATMEL_US_USCLKS_MCK		(0 <<  4)
> -#define		ATMEL_US_USCLKS_MCK_DIV8	(1 <<  4)
> -#define		ATMEL_US_USCLKS_GCLK		(2 <<  4)
> -#define		ATMEL_US_USCLKS_SCK		(3 <<  4)
> +#define		ATMEL_US_USCLKS_MCK		FIELD_PREP(ATMEL_US_USCLKS, 0)
> +#define		ATMEL_US_USCLKS_MCK_DIV8	FIELD_PREP(ATMEL_US_USCLKS, 1)
> +#define		ATMEL_US_USCLKS_GCLK		FIELD_PREP(ATMEL_US_USCLKS, 2)
> +#define		ATMEL_US_USCLKS_SCK		FIELD_PREP(ATMEL_US_USCLKS, 3)
>  #define	ATMEL_UA_FILTER		BIT(4)
>  #define	ATMEL_US_CHRL		GENMASK(7, 6)	/* Character Length */
> -#define		ATMEL_US_CHRL_5			(0 <<  6)
> -#define		ATMEL_US_CHRL_6			(1 <<  6)
> -#define		ATMEL_US_CHRL_7			(2 <<  6)
> -#define		ATMEL_US_CHRL_8			(3 <<  6)
> +#define		ATMEL_US_CHRL_5			FIELD_PREP(ATMEL_US_CHRL, 0)
> +#define		ATMEL_US_CHRL_6			FIELD_PREP(ATMEL_US_CHRL, 1)
> +#define		ATMEL_US_CHRL_7			FIELD_PREP(ATMEL_US_CHRL, 2)
> +#define		ATMEL_US_CHRL_8			FIELD_PREP(ATMEL_US_CHRL, 3)
>  #define	ATMEL_US_SYNC		BIT(8)		/* Synchronous Mode Select */
>  #define	ATMEL_US_PAR		GENMASK(11, 9)	/* Parity Type */
> -#define		ATMEL_US_PAR_EVEN		(0 <<  9)
> -#define		ATMEL_US_PAR_ODD		(1 <<  9)
> -#define		ATMEL_US_PAR_SPACE		(2 <<  9)
> -#define		ATMEL_US_PAR_MARK		(3 <<  9)
> -#define		ATMEL_US_PAR_NONE		(4 <<  9)
> -#define		ATMEL_US_PAR_MULTI_DROP		(6 <<  9)
> +#define		ATMEL_US_PAR_EVEN		FIELD_PREP(ATMEL_US_PAR, 0)
> +#define		ATMEL_US_PAR_ODD		FIELD_PREP(ATMEL_US_PAR, 1)
> +#define		ATMEL_US_PAR_SPACE		FIELD_PREP(ATMEL_US_PAR, 2)
> +#define		ATMEL_US_PAR_MARK		FIELD_PREP(ATMEL_US_PAR, 3)
> +#define		ATMEL_US_PAR_NONE		FIELD_PREP(ATMEL_US_PAR, 4)
> +#define		ATMEL_US_PAR_MULTI_DROP		FIELD_PREP(ATMEL_US_PAR, 6)
>  #define	ATMEL_US_NBSTOP		GENMASK(13, 12)	/* Number of Stop Bits */
> -#define		ATMEL_US_NBSTOP_1		(0 << 12)
> -#define		ATMEL_US_NBSTOP_1_5		(1 << 12)
> -#define		ATMEL_US_NBSTOP_2		(2 << 12)
> +#define		ATMEL_US_NBSTOP_1		FIELD_PREP(ATMEL_US_NBSTOP, 0)
> +#define		ATMEL_US_NBSTOP_1_5		FIELD_PREP(ATMEL_US_NBSTOP, 1)
> +#define		ATMEL_US_NBSTOP_2		FIELD_PREP(ATMEL_US_NBSTOP, 2)
>  #define	ATMEL_UA_BRSRCCK	BIT(12)	/* Clock Selection for UART */
>  #define	ATMEL_US_CHMODE		GENMASK(15, 14)	/* Channel Mode */
> -#define		ATMEL_US_CHMODE_NORMAL		(0 << 14)
> -#define		ATMEL_US_CHMODE_ECHO		(1 << 14)
> -#define		ATMEL_US_CHMODE_LOC_LOOP	(2 << 14)
> -#define		ATMEL_US_CHMODE_REM_LOOP	(3 << 14)
> +#define		ATMEL_US_CHMODE_NORMAL		FIELD_PREP(ATMEL_US_CHMODE, 0)
> +#define		ATMEL_US_CHMODE_ECHO		FIELD_PREP(ATMEL_US_CHMODE, 1)
> +#define		ATMEL_US_CHMODE_LOC_LOOP	FIELD_PREP(ATMEL_US_CHMODE, 2)
> +#define		ATMEL_US_CHMODE_REM_LOOP	FIELD_PREP(ATMEL_US_CHMODE, 3)
>  #define	ATMEL_US_MSBF		BIT(16)	/* Bit Order */
>  #define	ATMEL_US_MODE9		BIT(17)	/* 9-bit Character Length */
>  #define	ATMEL_US_CLKO		BIT(18)	/* Clock Output Select */
> @@ -82,7 +84,7 @@
>  #define	ATMEL_US_INACK		BIT(20)	/* Inhibit Non Acknowledge */
>  #define	ATMEL_US_DSNACK		BIT(21)	/* Disable Successive NACK */
>  #define	ATMEL_US_MAX_ITER_MASK	GENMASK(26, 24)	/* Max Iterations */
> -#define	ATMEL_US_MAX_ITER(n)	(((n) << 24) & ATMEL_US_MAX_ITER_MASK)
> +#define	ATMEL_US_MAX_ITER(n)	FIELD_PREP(ATMEL_US_MAX_ITER_MASK, (n))
>  #define	ATMEL_US_FILTER		BIT(28)	/* Infrared Receive Line Filter */
>  
>  #define ATMEL_US_IER		0x08	/* Interrupt Enable Register */
> @@ -134,19 +136,19 @@
>  
>  #define ATMEL_US_CMPR		0x90	/* Comparaison Register */
>  #define ATMEL_US_FMR		0xa0	/* FIFO Mode Register */
> -#define	ATMEL_US_TXRDYM(data)	(((data) & 0x3) << 0)	/* TX Ready Mode */
> -#define	ATMEL_US_RXRDYM(data)	(((data) & 0x3) << 4)	/* RX Ready Mode */
> +#define	ATMEL_US_TXRDYM(data)	FIELD_PREP(GENMASK(1, 0), (data))	/* TX Ready Mode */
> +#define	ATMEL_US_RXRDYM(data)	FIELD_PREP(GENMASK(5, 4), (data))	/* RX Ready Mode */
>  #define		ATMEL_US_ONE_DATA	0x0
>  #define		ATMEL_US_TWO_DATA	0x1
>  #define		ATMEL_US_FOUR_DATA	0x2
>  #define	ATMEL_US_FRTSC		BIT(7)	/* FIFO RTS pin Control */
> -#define	ATMEL_US_TXFTHRES(thr)	(((thr) & 0x3f) << 8)	/* TX FIFO Threshold */
> -#define	ATMEL_US_RXFTHRES(thr)	(((thr) & 0x3f) << 16)	/* RX FIFO Threshold */
> -#define	ATMEL_US_RXFTHRES2(thr)	(((thr) & 0x3f) << 24)	/* RX FIFO Threshold2 */
> +#define	ATMEL_US_TXFTHRES(thr)	FIELD_PREP(GENMASK(13, 8), (thr))	/* TX FIFO Threshold */
> +#define	ATMEL_US_RXFTHRES(thr)	FIELD_PREP(GENMASK(21, 16), (thr))	/* RX FIFO Threshold */
> +#define	ATMEL_US_RXFTHRES2(thr)	FIELD_PREP(GENMASK(29, 24), (thr))	/* RX FIFO Threshold2 */
>  
>  #define ATMEL_US_FLR		0xa4	/* FIFO Level Register */
> -#define	ATMEL_US_TXFL(reg)	(((reg) >> 0) & 0x3f)	/* TX FIFO Level */
> -#define	ATMEL_US_RXFL(reg)	(((reg) >> 16) & 0x3f)	/* RX FIFO Level */
> +#define	ATMEL_US_TXFL(reg)	FIELD_GET(GENMASK(5, 0), (reg))		/* TX FIFO Level */
> +#define	ATMEL_US_RXFL(reg)	FIELD_GET(GENMASK(21, 16), (reg))	/* RX FIFO Level */
>  
>  #define ATMEL_US_FIER		0xa8	/* FIFO Interrupt Enable Register */
>  #define ATMEL_US_FIDR		0xac	/* FIFO Interrupt Disable Register */


^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding
  2022-09-28 15:35         ` Sergiu.Moga
@ 2022-10-24 12:25           ` Lee Jones
  0 siblings, 0 replies; 20+ messages in thread
From: Lee Jones @ 2022-10-24 12:25 UTC (permalink / raw)
  To: Sergiu.Moga
  Cc: robh+dt, krzysztof.kozlowski+dt, Nicolas.Ferre,
	alexandre.belloni, Claudiu.Beznea, radu_nicolae.pirea,
	richard.genoud, gregkh, jirislaby, Kavyasree.Kotagiri,
	devicetree, linux-arm-kernel, linux-kernel, linux-spi,
	linux-serial, krzysztof.kozlowski

On Wed, 28 Sep 2022, Sergiu.Moga@microchip.com wrote:

> On 28.09.2022 18:23, Lee Jones wrote:
> > On Wed, 28 Sep 2022, Sergiu.Moga@microchip.com wrote:
> > 
> >> On 28.09.2022 18:03, Lee Jones wrote:
> >>> On Thu, 22 Sep 2022, Sergiu Moga wrote:
> >>>
> >>>> Another functionality of FLEXCOM is that of SPI. In order for
> >>>> the proper validation of the SPI children nodes through the binding
> >>>> to occur, the proper binding for SPI must be referenced.
> >>>>
> >>>> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
> >>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> >>>> ---
> >>>>
> >>>>
> >>>> v1 -> v2:
> >>>> - use full schema paths
> >>>>
> >>>>
> >>>> v2 -> v3:
> >>>> - Added Reviewed-by tag, previously this was [PATCH 3]
> >>>>
> >>>>
> >>>> v3 -> v4:
> >>>> - Nothing, previously this was [PATCH 5]
> >>>>
> >>>>
> >>>> v4 -> v5:
> >>>> - Nothing
> >>>>
> >>>>
> >>>>
> >>>>    .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml       | 5 ++---
> >>>>    1 file changed, 2 insertions(+), 3 deletions(-)
> >>>
> >>> Not sure how these can be handled.
> >>>
> >>> I guess I cannot take these until the other patches are applied.
> >>>
> >>> NB: The patch doesn't apply cleanly anyway, so will need to be rebased.
> >>>
> >>
> >>
> >> Hello,
> >>
> >> The sama5d2-flexcom binding related patches are dependent on:
> >> https://lore.kernel.org/linux-arm-kernel/20220916075744.1879428-1-kavyasree.kotagiri@microchip.com/
> > 
> > I would be very cautious about relying on comments made in the
> > cover-letter.  Better to make this a hard requirement and place them
> > in the same patch-set.
> > 
> 
> 
> 
> Understood, my apologies, I will keep this in mind the next time this 
> happens :).
> 
> Otherwise, by applying the patch series linked above, my sama5d2-flexcom 
> patches should apply cleanly afterwards.

Please re-send this once the other set has been applied.

-- 
Lee Jones [李琼斯]

^ permalink raw reply	[flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-10-24 13:17 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-22 11:33 [PATCH v5 0/9] Make atmel serial driver aware of GCLK Sergiu Moga
2022-09-22 11:33 ` [PATCH v5 1/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Sergiu Moga
2022-09-28 15:03   ` Lee Jones
2022-09-28 15:07     ` Sergiu.Moga
2022-09-28 15:23       ` Lee Jones
2022-09-28 15:35         ` Sergiu.Moga
2022-10-24 12:25           ` Lee Jones
2022-09-22 11:33 ` [PATCH v5 2/9] dt-bindings: serial: atmel,at91-usart: convert to json-schema Sergiu Moga
2022-09-22 11:33 ` [PATCH v5 3/9] dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to SAM9X60 Sergiu Moga
2022-09-22 11:33 ` [PATCH v5 4/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding Sergiu Moga
2022-09-22 11:33 ` [PATCH v5 5/9] dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART clock Sergiu Moga
2022-09-22 11:33 ` [PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART Sergiu Moga
2022-09-30  7:22   ` Claudiu.Beznea
2022-09-22 11:33 ` [PATCH v5 7/9] tty: serial: atmel: Only divide Clock Divisor if the IP is USART Sergiu Moga
2022-09-30  7:22   ` Claudiu.Beznea
2022-09-22 11:33 ` [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK Sergiu Moga
2022-09-30  7:23   ` Claudiu.Beznea
2022-09-22 11:33 ` [PATCH v5 9/9] tty: serial: atmel: Use FIELD_PREP/FIELD_GET Sergiu Moga
2022-09-22 12:12   ` Ilpo Järvinen
2022-09-30  7:23   ` Claudiu.Beznea

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