From: Boris Brezillon <boris.brezillon@bootlin.com>
To: David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Boris Brezillon <boris.brezillon@bootlin.com>,
Marek Vasut <marek.vasut@gmail.com>,
Richard Weinberger <richard@nod.at>,
linux-mtd@lists.infradead.org,
Yogesh Gaur <yogeshnarayan.gaur@nxp.com>,
Vignesh R <vigneshr@ti.com>,
Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Cc: Julien Su <juliensu@mxic.com.tw>, Mark Brown <broonie@kernel.org>,
Mason Yang <masonccyang@mxic.com.tw>,
linux-spi@vger.kernel.org, zhengxunli@mxic.com.tw
Subject: [PATCH RFC 14/18] mtd: spi-nor: Clarify where DTR mode applies
Date: Fri, 12 Oct 2018 10:48:21 +0200 [thread overview]
Message-ID: <20181012084825.23697-15-boris.brezillon@bootlin.com> (raw)
In-Reply-To: <20181012084825.23697-1-boris.brezillon@bootlin.com>
In its current state, '_DTR' means 'send everything except the
instruction in DTR mode'. Clarify that by renaming the macros into
_1_xD_xD so that we can later support full DTR modes (where the
instruction byte is also sent in DTR mode).
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
drivers/mtd/spi-nor/spi-nor.c | 22 ++++++++--------
include/linux/mtd/spi-nor.h | 61 ++++++++++++++++++++++++++-----------------
2 files changed, 48 insertions(+), 35 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 9cd8677b8cb2..98dab7f6938e 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -58,25 +58,25 @@ struct spi_nor_pp_command {
enum spi_nor_read_command_index {
SNOR_CMD_READ,
SNOR_CMD_READ_FAST,
- SNOR_CMD_READ_1_1_1_DTR,
+ SNOR_CMD_READ_1_1D_1D,
/* Dual SPI */
SNOR_CMD_READ_1_1_2,
SNOR_CMD_READ_1_2_2,
SNOR_CMD_READ_2_2_2,
- SNOR_CMD_READ_1_2_2_DTR,
+ SNOR_CMD_READ_1_2D_2D,
/* Quad SPI */
SNOR_CMD_READ_1_1_4,
SNOR_CMD_READ_1_4_4,
SNOR_CMD_READ_4_4_4,
- SNOR_CMD_READ_1_4_4_DTR,
+ SNOR_CMD_READ_1_4D_4D,
/* Octo SPI */
SNOR_CMD_READ_1_1_8,
SNOR_CMD_READ_1_8_8,
SNOR_CMD_READ_8_8_8,
- SNOR_CMD_READ_1_8_8_DTR,
+ SNOR_CMD_READ_1_8D_8D,
SNOR_CMD_READ_MAX
};
@@ -613,9 +613,9 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
- { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
- { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
- { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
+ { SPINOR_OP_READ_1_1D_1D, SPINOR_OP_READ_1_1D_1D_4B },
+ { SPINOR_OP_READ_1_2D_2D, SPINOR_OP_READ_1_2D_2D_4B },
+ { SPINOR_OP_READ_1_4D_4D, SPINOR_OP_READ_1_4D_4D_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
@@ -2999,19 +2999,19 @@ static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
static const int hwcaps_read2cmd[][2] = {
{ SNOR_HWCAPS_READ, SNOR_CMD_READ },
{ SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
- { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
+ { SNOR_HWCAPS_READ_1_1D_1D, SNOR_CMD_READ_1_1D_1D },
{ SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
{ SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
{ SNOR_HWCAPS_DPI, SNOR_CMD_READ_2_2_2 },
- { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
+ { SNOR_HWCAPS_READ_1_2D_2D, SNOR_CMD_READ_1_2D_2D },
{ SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
{ SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
{ SNOR_HWCAPS_QPI, SNOR_CMD_READ_4_4_4 },
- { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
+ { SNOR_HWCAPS_READ_1_4D_4D, SNOR_CMD_READ_1_4D_4D },
{ SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
{ SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
{ SNOR_HWCAPS_OPI, SNOR_CMD_READ_8_8_8 },
- { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
+ { SNOR_HWCAPS_READ_1_8D_8D, SNOR_CMD_READ_1_8D_8D },
};
return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index e497f3b93a74..1035706bc6db 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -81,13 +81,13 @@
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
-#define SPINOR_OP_READ_1_1_1_DTR 0x0d
-#define SPINOR_OP_READ_1_2_2_DTR 0xbd
-#define SPINOR_OP_READ_1_4_4_DTR 0xed
+#define SPINOR_OP_READ_1_1D_1D 0x0d
+#define SPINOR_OP_READ_1_2D_2D 0xbd
+#define SPINOR_OP_READ_1_4D_4D 0xed
-#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
-#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
-#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
+#define SPINOR_OP_READ_1_1D_1D_4B 0x0e
+#define SPINOR_OP_READ_1_2D_2D_4B 0xbe
+#define SPINOR_OP_READ_1_4D_4D_4B 0xee
/* Used for SST flashes only. */
#define SPINOR_OP_BP 0x02 /* Byte program */
@@ -174,7 +174,10 @@
((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
SNOR_PROTO_DATA_MASK)
-#define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
+/* Double Transfer Rate flags */
+#define SNOR_PROTO_INST_IS_DTR BIT(26)
+#define SNOR_PROTO_ADDR_IS_DTR BIT(25)
+#define SNOR_PROTO_DATA_IS_DTR BIT(24)
#define SNOR_PROTO_INST_2BYTE BIT(31)
@@ -182,9 +185,9 @@
(SNOR_PROTO_INST(_inst_nbits) | \
SNOR_PROTO_ADDR(_addr_nbits) | \
SNOR_PROTO_DATA(_data_nbits))
-#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
- (SNOR_PROTO_IS_DTR | \
- SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
+#define SNOR_PROTO_1_XD_XD(_nbits) \
+ (SNOR_PROTO_DATA_IS_DTR | SNOR_PROTO_ADDR_IS_DTR | \
+ SNOR_PROTO_STR(1, _nbits, _nbits))
enum spi_nor_protocol {
SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
@@ -198,15 +201,25 @@ enum spi_nor_protocol {
SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
- SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
- SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
- SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
- SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
+ SNOR_PROTO_1_1D_1D = SNOR_PROTO_1_XD_XD(1),
+ SNOR_PROTO_1_2D_2D = SNOR_PROTO_1_XD_XD(2),
+ SNOR_PROTO_1_4D_4D = SNOR_PROTO_1_XD_XD(4),
+ SNOR_PROTO_1_8D_8D = SNOR_PROTO_1_XD_XD(8),
};
-static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
+static inline bool spi_nor_protocol_inst_is_dtr(enum spi_nor_protocol proto)
{
- return !!(proto & SNOR_PROTO_IS_DTR);
+ return !!(proto & SNOR_PROTO_INST_IS_DTR);
+}
+
+static inline bool spi_nor_protocol_addr_is_dtr(enum spi_nor_protocol proto)
+{
+ return !!(proto & SNOR_PROTO_ADDR_IS_DTR);
+}
+
+static inline bool spi_nor_protocol_data_is_dtr(enum spi_nor_protocol proto)
+{
+ return !!(proto & SNOR_PROTO_DATA_IS_DTR);
}
static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
@@ -499,22 +512,22 @@ struct spi_nor_hwcaps {
#define SNOR_HWCAPS_READ_MASK GENMASK(11, 0)
#define SNOR_HWCAPS_READ BIT(0)
#define SNOR_HWCAPS_READ_FAST BIT(1)
-#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
+#define SNOR_HWCAPS_READ_1_1D_1D BIT(2)
#define SNOR_HWCAPS_READ_DUAL GENMASK(5, 3)
#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
-#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(5)
+#define SNOR_HWCAPS_READ_1_2D_2D BIT(5)
#define SNOR_HWCAPS_READ_QUAD GENMASK(8, 6)
#define SNOR_HWCAPS_READ_1_1_4 BIT(6)
#define SNOR_HWCAPS_READ_1_4_4 BIT(7)
-#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(8)
+#define SNOR_HWCAPS_READ_1_4D_4D BIT(8)
#define SNOR_HWCPAS_READ_OCTO GENMASK(11, 9)
#define SNOR_HWCAPS_READ_1_1_8 BIT(9)
#define SNOR_HWCAPS_READ_1_8_8 BIT(10)
-#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(11)
+#define SNOR_HWCAPS_READ_1_8D_8D BIT(11)
/*
* Page Program capabilities.
@@ -553,10 +566,10 @@ struct spi_nor_hwcaps {
SNOR_HWCAPS_QPI | \
SNOR_HWCAPS_OPI)
-#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
- SNOR_HWCAPS_READ_1_2_2_DTR | \
- SNOR_HWCAPS_READ_1_4_4_DTR | \
- SNOR_HWCAPS_READ_1_8_8_DTR)
+#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1D_1D | \
+ SNOR_HWCAPS_READ_1_2D_2D | \
+ SNOR_HWCAPS_READ_1_4D_4D | \
+ SNOR_HWCAPS_READ_1_8D_8D)
#define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
SNOR_HWCAPS_PP_MASK | \
--
2.14.1
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next prev parent reply other threads:[~2018-10-12 8:48 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-12 8:48 [PATCH RFC 00/18] mtd: spi-nor: Proposal for 8-8-8 mode support Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 01/18] mtd: spi-nor: Add a flash_info entry for Macronix mx25uw51245g Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 02/18] spi: Prepare things for octo mode support Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 03/18] spi: spi-mem: Prepare things for DTR " Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 04/18] spi: spi-mem: Prepare things for dual bytes opcodes support Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 05/18] spi: spi-mem: mxic: Add support for DTR and Octo mode Boris Brezillon
2018-11-18 17:21 ` Miquel Raynal
2018-11-18 17:32 ` Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 06/18] mtd: spi-nor: Move m25p80 code in spi-nor.c Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 07/18] mtd: spi-nor: Rework hwcaps selection for the spi-mem case Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 08/18] mtd: spi-nor: Define the DPI, QPI and OPI hwcaps Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 09/18] mtd: spi-nor: Add spi_nor_{read, write}_reg() helpers Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 10/18] mtd: spi-nor: Add support for X-X-X modes Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 11/18] mtd: spi-nor: Prepare things for 2byte opcodes Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 12/18] mtd: spi-nor: Provide a hook to tweak flash parameters Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 13/18] mtd: spi-nor: Add 8-8-8 mode support to Macronix mx25uw51245g Boris Brezillon
2018-10-12 8:48 ` Boris Brezillon [this message]
2018-10-12 8:48 ` [PATCH RFC 15/18] mtd: spi-nor: Add DTR support to the spi-mem logic Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 16/18] mtd: spi-nor: Add the concept of full DTR modes Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 17/18] mtd: spi-nor: Add 8D-8D-8D mode Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 18/18] mtd: spi-nor: Make sure the 8D-8D-8D can be selected on mx25uw51245g Boris Brezillon
[not found] ` <OF300145A1.D60E7B33-ON48258376.002EDC4B-48258376.0031A14C@LocalDomain>
[not found] ` <OF3005248A.454B9B59-ON48258382.002767AE-48258382.00293E8D@mxic.com.tw>
2019-01-14 8:39 ` Boris Brezillon
2018-10-19 12:25 ` [PATCH RFC 00/18] mtd: spi-nor: Proposal for 8-8-8 mode support Mark Brown
2018-10-19 12:59 ` Boris Brezillon
2018-10-21 13:36 ` Mark Brown
2018-10-22 8:21 ` Boris Brezillon
2018-10-22 12:01 ` Mark Brown
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