From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>,
Vignesh R <vigneshr@ti.com>, Julien Su <juliensu@mxic.com.tw>,
Richard Weinberger <richard@nod.at>,
linux-spi@vger.kernel.org, Marek Vasut <marek.vasut@gmail.com>,
Mark Brown <broonie@kernel.org>,
linux-mtd@lists.infradead.org,
Mason Yang <masonccyang@mxic.com.tw>,
Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>,
Brian Norris <computersforpeace@gmail.com>,
David Woodhouse <dwmw2@infradead.org>,
zhengxunli@mxic.com.tw
Subject: Re: [PATCH RFC 05/18] spi: spi-mem: mxic: Add support for DTR and Octo mode
Date: Sun, 18 Nov 2018 18:32:48 +0100 [thread overview]
Message-ID: <20181118183248.5ef63c04@bbrezillon> (raw)
In-Reply-To: <20181118182111.3c199434@xps13>
On Sun, 18 Nov 2018 18:21:11 +0100
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> Hi Boris,
>
> Boris Brezillon <boris.brezillon@bootlin.com> wrote on Fri, 12 Oct 2018
> 10:48:12 +0200:
>
> > Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
> > ---
> > drivers/spi/spi-mxic.c | 27 +++++++++++++++++++++------
> > 1 file changed, 21 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> > index ce59ea2ecfe2..70e6bc9a099e 100644
> > --- a/drivers/spi/spi-mxic.c
> > +++ b/drivers/spi/spi-mxic.c
> > @@ -281,10 +281,11 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
> > static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
> > const struct spi_mem_op *op)
> > {
> > - if (op->data.buswidth > 4 || op->addr.buswidth > 4 ||
> > - op->dummy.buswidth > 4 || op->cmd.buswidth > 4)
> > + if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
> > + op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
> > return false;
> >
> > +
>
> Extra space here
>
> > if (op->data.nbytes && op->dummy.nbytes &&
> > op->data.buswidth != op->dummy.buswidth)
> > return false;
> > @@ -302,6 +303,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> > int nio = 1, i, ret;
> > u32 ss_ctrl;
> > u8 addr[8];
> > + u8 cmd[2];
> >
> > ret = mxic_spi_clk_setup(mem->spi);
> > if (ret)
> > @@ -311,6 +313,8 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> > if (ret)
> > return ret;
> >
> > + if (mem->spi->mode & (SPI_RX_OCTO | SPI_TX_OCTO))
> > + nio = 8;
> > if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
> > nio = 4;
> > else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
> > @@ -323,17 +327,21 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> > mxic->regs + HC_CFG);
> > writel(HC_EN_BIT, mxic->regs + HC_EN);
> >
> > - ss_ctrl = OP_CMD_BYTES(1) | OP_CMD_BUSW(fls(op->cmd.buswidth) - 1);
> > + ss_ctrl = OP_CMD_BYTES(op->cmd.nbytes) |
> > + OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
> > + (op->cmd.dtr ? OP_CMD_DDR : 0);
> >
> > if (op->addr.nbytes)
> > ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
> > - OP_ADDR_BUSW(fls(op->addr.buswidth) - 1);
> > + OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
> > + (op->addr.dtr ? OP_ADDR_DDR : 0);
> >
> > if (op->dummy.nbytes)
> > ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
> >
> > if (op->data.nbytes) {
> > - ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1);
> > + ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
> > + (op->data.dtr ? OP_DATA_DDR : 0);
> > if (op->data.dir == SPI_MEM_DATA_IN)
> > ss_ctrl |= OP_READ;
> > }
> > @@ -343,7 +351,14 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> > writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
> > mxic->regs + HC_CFG);
> >
> > - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1);
> > + if (op->cmd.nbytes == 2) {
> > + cmd[0] = op->cmd.opcode >> 8;
> > + cmd[1] = op->cmd.opcode;
> > + } else {
> > + cmd[0] = op->cmd.opcode;
> > + }
>
> I haven't played with this code yet and maybe I'll regret this but
> wouldn't be easier for developers to have this in patch 4:
>
> struct spi_mem_op {
> struct {
> + u8 nbytes;
> u8 buswidth;
> bool dtr;
> - u8 opcode;
> + u8 opcode[2]; /* <- an array of opcodes instead of an u16? */
Just wanted to stay consistent with what we have for the address
cycles, but maybe I should clarify how the opcode should be
transmitted on the wire (MSB first).
> } cmd;
>
> This way I think we would avoid endianness considerations and reading
> would be eased.
>
> > +
> > + ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes);
> > if (ret)
> > goto out;
> >
>
>
> Thanks,
> Miquèl
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next prev parent reply other threads:[~2018-11-18 17:32 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-12 8:48 [PATCH RFC 00/18] mtd: spi-nor: Proposal for 8-8-8 mode support Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 01/18] mtd: spi-nor: Add a flash_info entry for Macronix mx25uw51245g Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 02/18] spi: Prepare things for octo mode support Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 03/18] spi: spi-mem: Prepare things for DTR " Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 04/18] spi: spi-mem: Prepare things for dual bytes opcodes support Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 05/18] spi: spi-mem: mxic: Add support for DTR and Octo mode Boris Brezillon
2018-11-18 17:21 ` Miquel Raynal
2018-11-18 17:32 ` Boris Brezillon [this message]
2018-10-12 8:48 ` [PATCH RFC 06/18] mtd: spi-nor: Move m25p80 code in spi-nor.c Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 07/18] mtd: spi-nor: Rework hwcaps selection for the spi-mem case Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 08/18] mtd: spi-nor: Define the DPI, QPI and OPI hwcaps Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 09/18] mtd: spi-nor: Add spi_nor_{read, write}_reg() helpers Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 10/18] mtd: spi-nor: Add support for X-X-X modes Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 11/18] mtd: spi-nor: Prepare things for 2byte opcodes Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 12/18] mtd: spi-nor: Provide a hook to tweak flash parameters Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 13/18] mtd: spi-nor: Add 8-8-8 mode support to Macronix mx25uw51245g Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 14/18] mtd: spi-nor: Clarify where DTR mode applies Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 15/18] mtd: spi-nor: Add DTR support to the spi-mem logic Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 16/18] mtd: spi-nor: Add the concept of full DTR modes Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 17/18] mtd: spi-nor: Add 8D-8D-8D mode Boris Brezillon
2018-10-12 8:48 ` [PATCH RFC 18/18] mtd: spi-nor: Make sure the 8D-8D-8D can be selected on mx25uw51245g Boris Brezillon
[not found] ` <OF300145A1.D60E7B33-ON48258376.002EDC4B-48258376.0031A14C@LocalDomain>
[not found] ` <OF3005248A.454B9B59-ON48258382.002767AE-48258382.00293E8D@mxic.com.tw>
2019-01-14 8:39 ` Boris Brezillon
2018-10-19 12:25 ` [PATCH RFC 00/18] mtd: spi-nor: Proposal for 8-8-8 mode support Mark Brown
2018-10-19 12:59 ` Boris Brezillon
2018-10-21 13:36 ` Mark Brown
2018-10-22 8:21 ` Boris Brezillon
2018-10-22 12:01 ` Mark Brown
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