[PATCH 0/7] spi: zynq-qspi: Clarify and fix the chip selection

From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>,
	Michal Simek <michal.simek@xilinx.com>,
	Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>,
	linux-arm-kernel@lists.infradead.org,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	linux-spi@vger.kernel.org
Subject: [PATCH 0/7] spi: zynq-qspi: Clarify and fix the chip selection
Date: Fri,  8 Nov 2019 11:59:13 +0100	[thread overview]
Message-ID: <20191108105920.19014-1-miquel.raynal@bootlin.com> (raw)

Hello,

While working on SPI-NOR support I figured the chip select handling of
the Zynq 7000 QSPI driver was not behaving as I would have
expected. While cheking out what was wrong I decided to clarify things
around so I did a bit of cleaning. The step-by-step changes are the
reason for patches [1-6]. This way, the last patch actually adding
support for both CS is much more understandable.

Thanks,
Miquèl

Miquel Raynal (7):
  spi: zynq-qspi: Anything else than CS0 is not supported yet
  spi: zynq-qspi: Keep the naming consistent across the driver
  spi: zynq-qspi: Keep the bitfields naming consistent
  spi: zynq-qspi: Enhance the Linear CFG bit definitions
  spi: zynq-qspi: Clarify the select chip function
  spi: zynq-qspi: Do the actual hardware initialization later in the
    probe
  spi: zynq-qspi: Support two chip selects

 drivers/spi/spi-zynq-qspi.c | 84 ++++++++++++++++++++++---------------
 1 file changed, 51 insertions(+), 33 deletions(-)

-- 
2.20.1

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