From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
linux-arm-kernel@lists.infradead.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
linux-spi@vger.kernel.org
Subject: [PATCH 4/7] spi: zynq-qspi: Enhance the Linear CFG bit definitions
Date: Fri, 8 Nov 2019 11:59:17 +0100 [thread overview]
Message-ID: <20191108105920.19014-5-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20191108105920.19014-1-miquel.raynal@bootlin.com>
Using masks makes sense when manipulating fields of several bits. When
only one bit is involved, let's just use the BIT() macro to define the
actual bit instead of the needed shift to obtain it and use a better
naming.
These definitions will be used in a following change.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/spi/spi-zynq-qspi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
index 11a484aa3186..34c24b2ad3cf 100644
--- a/drivers/spi/spi-zynq-qspi.c
+++ b/drivers/spi/spi-zynq-qspi.c
@@ -99,9 +99,9 @@
* It is named Linear Configuration but it controls other modes when not in
* linear mode also.
*/
-#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK 0x40000000 /* LQSPI Two memories Mask */
-#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK 0x20000000 /* LQSPI Separate bus Mask */
-#define ZYNQ_QSPI_LCFG_U_PAGE_MASK 0x10000000 /* LQSPI Upper Page Mask */
+#define ZYNQ_QSPI_LCFG_TWO_MEM BIT(30) /* LQSPI Two memories */
+#define ZYNQ_QSPI_LCFG_SEP_BUS BIT(29) /* LQSPI Separate bus */
+#define ZYNQ_QSPI_LCFG_U_PAGE BIT(28) /* LQSPI Upper Page */
#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8
--
2.20.1
next prev parent reply other threads:[~2019-11-08 10:59 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-08 10:59 [PATCH 0/7] spi: zynq-qspi: Clarify and fix the chip selection Miquel Raynal
2019-11-08 10:59 ` [PATCH 1/7] spi: zynq-qspi: Anything else than CS0 is not supported yet Miquel Raynal
2019-11-08 12:07 ` Mark Brown
2019-11-08 13:31 ` Miquel Raynal
2019-11-08 10:59 ` [PATCH 2/7] spi: zynq-qspi: Keep the naming consistent across the driver Miquel Raynal
2019-11-08 12:08 ` Applied "spi: zynq-qspi: Keep the naming consistent across the driver" to the spi tree Mark Brown
2019-11-08 10:59 ` [PATCH 3/7] spi: zynq-qspi: Keep the bitfields naming consistent Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal [this message]
2019-11-08 10:59 ` [PATCH 5/7] spi: zynq-qspi: Clarify the select chip function Miquel Raynal
2019-11-08 10:59 ` [PATCH 6/7] spi: zynq-qspi: Do the actual hardware initialization later in the probe Miquel Raynal
2019-11-08 10:59 ` [PATCH 7/7] spi: zynq-qspi: Support two chip selects Miquel Raynal
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