* [PATCH v2 1/6] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
2020-10-21 2:55 [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
@ 2020-10-21 2:55 ` Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
` (4 subsequent siblings)
5 siblings, 0 replies; 15+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-21 2:55 UTC (permalink / raw)
To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add QSPI controller support for Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
drivers/spi/Kconfig | 2 +-
drivers/spi/spi-cadence-quadspi.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d2c976e55b8b..926da61eee5a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -203,7 +203,7 @@ config SPI_CADENCE
config SPI_CADENCE_QUADSPI
tristate "Cadence Quad SPI controller"
- depends on OF && (ARM || ARM64 || COMPILE_TEST)
+ depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
help
Enable support for the Cadence Quad SPI Flash controller.
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 40938cf3806d..d7b10c46fa70 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1401,6 +1401,9 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "ti,am654-ospi",
.data = &am654_ospi,
},
+ {
+ .compatible = "intel,lgm-qspi",
+ },
{ /* end of table */ }
};
--
2.11.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
2020-10-21 2:55 [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 1/6] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
@ 2020-10-21 2:55 ` Ramuthevar,Vadivel MuruganX
2020-10-21 15:17 ` Pratyush Yadav
2020-10-21 2:55 ` [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
` (3 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-21 2:55 UTC (permalink / raw)
To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).
This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfer.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index d7b10c46fa70..3d017b484114 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1106,6 +1106,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ /* Disable direct access controller */
+ if (!cqspi->use_direct_mode) {
+ reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+ reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+ writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ }
+
cqspi_controller_enable(cqspi, 1);
}
@@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
.quirks = CQSPI_NEEDS_WR_DELAY,
};
+static const struct cqspi_driver_platdata intel_lgm_qspi = {
+ .quirks = CQSPI_DISABLE_DAC_MODE,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
},
{
.compatible = "intel,lgm-qspi",
+ .data = &intel_lgm_qspi,
},
{ /* end of table */ }
};
--
2.11.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
2020-10-21 2:55 ` [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
@ 2020-10-21 15:17 ` Pratyush Yadav
2020-10-22 2:17 ` Ramuthevar, Vadivel MuruganX
0 siblings, 1 reply; 15+ messages in thread
From: Pratyush Yadav @ 2020-10-21 15:17 UTC (permalink / raw)
To: Ramuthevar,Vadivel MuruganX
Cc: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi,
robh+dt, devicetree, miquel.raynal, simon.k.r.goldschmidt,
dinguyen, richard, cheol.yong.kim, qi-ming.wu
Hi,
On 21/10/20 10:55AM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>
> On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
> Direct Access Controller(DAC).
>
> This patch adds a quirk to disable the Direct Access Controller
> for data transfer instead it uses indirect data transfer.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
> drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
> index d7b10c46fa70..3d017b484114 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -1106,6 +1106,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
> reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
>
> + /* Disable direct access controller */
> + if (!cqspi->use_direct_mode) {
> + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
> + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
> + }
> +
Do you really need to disable the DAC controller? cqspi_read() and
cqspi_write() already check for cqspi->use_direct_mode and avoid using
direct mode if it is false. While I don't think it would do any harm I'm
curious what prompted you to do this instead of just setting the quirk
like cdns_qspi does.
Anyway, if you do insist on doing it, it does not make any sense to set
a bit and then unset it immediately after. The datasheet I have says
this bit resets to 1 so the block above the code you added should be
removed.
> cqspi_controller_enable(cqspi, 1);
> }
>
> @@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
> .quirks = CQSPI_NEEDS_WR_DELAY,
> };
>
> +static const struct cqspi_driver_platdata intel_lgm_qspi = {
> + .quirks = CQSPI_DISABLE_DAC_MODE,
> +};
> +
> static const struct of_device_id cqspi_dt_ids[] = {
> {
> .compatible = "cdns,qspi-nor",
> @@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
> },
> {
> .compatible = "intel,lgm-qspi",
> + .data = &intel_lgm_qspi,
> },
> { /* end of table */ }
> };
--
Regards,
Pratyush Yadav
Texas Instruments India
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
2020-10-21 15:17 ` Pratyush Yadav
@ 2020-10-22 2:17 ` Ramuthevar, Vadivel MuruganX
2020-10-22 9:01 ` Pratyush Yadav
0 siblings, 1 reply; 15+ messages in thread
From: Ramuthevar, Vadivel MuruganX @ 2020-10-22 2:17 UTC (permalink / raw)
To: Pratyush Yadav
Cc: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi,
robh+dt, devicetree, miquel.raynal, simon.k.r.goldschmidt,
dinguyen, richard, cheol.yong.kim, qi-ming.wu
Hi Pratyush,
On 21/10/2020 11:17 pm, Pratyush Yadav wrote:
> Hi,
>
> On 21/10/20 10:55AM, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
>> Direct Access Controller(DAC).
>>
>> This patch adds a quirk to disable the Direct Access Controller
>> for data transfer instead it uses indirect data transfer.
>>
>> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>> ---
>> drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
>> index d7b10c46fa70..3d017b484114 100644
>> --- a/drivers/spi/spi-cadence-quadspi.c
>> +++ b/drivers/spi/spi-cadence-quadspi.c
>> @@ -1106,6 +1106,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
>> reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
>> writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
>>
>> + /* Disable direct access controller */
>> + if (!cqspi->use_direct_mode) {
>> + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
>> + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
>> + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
>> + }
>> +
>
> Do you really need to disable the DAC controller? cqspi_read() and
> cqspi_write() already check for cqspi->use_direct_mode and avoid using
> direct mode if it is false. While I don't think it would do any harm I'm
> curious what prompted you to do this instead of just setting the quirk
> like cdns_qspi does.
>
> Anyway, if you do insist on doing it, it does not make any sense to set
> a bit and then unset it immediately after. The datasheet I have says
> this bit resets to 1 so the block above the code you added should be
> removed.
Thank you for your review comments..
yes, we need this patch to disable DAC for our SoC to avoid any
conflicts in future as well since Intel LGM SoC doesn't support DAC at all.
Regards
Vadivel
>
>> cqspi_controller_enable(cqspi, 1);
>> }
>>
>> @@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
>> .quirks = CQSPI_NEEDS_WR_DELAY,
>> };
>>
>> +static const struct cqspi_driver_platdata intel_lgm_qspi = {
>> + .quirks = CQSPI_DISABLE_DAC_MODE,
>> +};
>> +
>> static const struct of_device_id cqspi_dt_ids[] = {
>> {
>> .compatible = "cdns,qspi-nor",
>> @@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
>> },
>> {
>> .compatible = "intel,lgm-qspi",
>> + .data = &intel_lgm_qspi,
>> },
>> { /* end of table */ }
>> };
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
2020-10-22 2:17 ` Ramuthevar, Vadivel MuruganX
@ 2020-10-22 9:01 ` Pratyush Yadav
2020-10-22 9:14 ` Ramuthevar, Vadivel MuruganX
0 siblings, 1 reply; 15+ messages in thread
From: Pratyush Yadav @ 2020-10-22 9:01 UTC (permalink / raw)
To: Ramuthevar, Vadivel MuruganX
Cc: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi,
robh+dt, devicetree, miquel.raynal, simon.k.r.goldschmidt,
dinguyen, richard, cheol.yong.kim, qi-ming.wu
On 22/10/20 10:17AM, Ramuthevar, Vadivel MuruganX wrote:
> Hi Pratyush,
>
> On 21/10/2020 11:17 pm, Pratyush Yadav wrote:
> > Hi,
> >
> > On 21/10/20 10:55AM, Ramuthevar,Vadivel MuruganX wrote:
> > > From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> > >
> > > On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
> > > Direct Access Controller(DAC).
> > >
> > > This patch adds a quirk to disable the Direct Access Controller
> > > for data transfer instead it uses indirect data transfer.
> > >
> > > Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> > > ---
> > > drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
> > > 1 file changed, 12 insertions(+)
> > >
> > > diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
> > > index d7b10c46fa70..3d017b484114 100644
> > > --- a/drivers/spi/spi-cadence-quadspi.c
> > > +++ b/drivers/spi/spi-cadence-quadspi.c
> > > @@ -1106,6 +1106,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
> > > reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> > > writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
> > > + /* Disable direct access controller */
> > > + if (!cqspi->use_direct_mode) {
> > > + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
> > > + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> > > + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
> > > + }
> > > +
> >
> > Do you really need to disable the DAC controller? cqspi_read() and
> > cqspi_write() already check for cqspi->use_direct_mode and avoid using
> > direct mode if it is false. While I don't think it would do any harm I'm
> > curious what prompted you to do this instead of just setting the quirk
> > like cdns_qspi does.
> >
> > Anyway, if you do insist on doing it, it does not make any sense to set
> > a bit and then unset it immediately after. The datasheet I have says
> > this bit resets to 1 so the block above the code you added should be
> > removed.
> Thank you for your review comments..
> yes, we need this patch to disable DAC for our SoC to avoid any conflicts in
> future as well since Intel LGM SoC doesn't support DAC at all.
I'm not sure you got my point here. I understand that LGM SoCs don't
support DAC. I'm not arguing if this _patch_ is needed. I'm arguing if
this _hunk_ is needed. Does DAC mode need to be explicitly disabled
here? Why will the check in cqspi_read() and cqspi_write() not be
enough?
My other point is that if you absolutely need to disable DAC mode, then
instead of the code you have added, it would make more sense to do
something like below in cqspi_controller_init(). Because the bit resets
to 1 so the block of code to enable it is useless [0].
--- 8< ---
diff --git a/drivers/spi/spi-cadence-quadspi.c
b/drivers/spi/spi-cadence-quadspi.c
index d7ad8b198a11..d2c5d448a944 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -2156,10 +2156,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
- /* Enable Direct Access Controller */
- reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
- reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
- writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ /* Disable Direct Access Controller */
+ if (!cqspi->use_dac_mode) {
+ reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+ reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+ writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ }
cqspi_controller_enable(cqspi, 1);
}
--- >8 ---
Disclaimer: not tested at all.
[0] Git blames Vignesh for that block of code added in a27f2eaf2b27.
Vignesh, was this simply an oversight or was there any real reason to
set the bit?
> Regards
> Vadivel
> >
> > > cqspi_controller_enable(cqspi, 1);
> > > }
> > > @@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
> > > .quirks = CQSPI_NEEDS_WR_DELAY,
> > > };
> > > +static const struct cqspi_driver_platdata intel_lgm_qspi = {
> > > + .quirks = CQSPI_DISABLE_DAC_MODE,
> > > +};
> > > +
> > > static const struct of_device_id cqspi_dt_ids[] = {
> > > {
> > > .compatible = "cdns,qspi-nor",
> > > @@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
> > > },
> > > {
> > > .compatible = "intel,lgm-qspi",
> > > + .data = &intel_lgm_qspi,
> > > },
> > > { /* end of table */ }
> > > };
> >
--
Regards,
Pratyush Yadav
Texas Instruments India
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
2020-10-22 9:01 ` Pratyush Yadav
@ 2020-10-22 9:14 ` Ramuthevar, Vadivel MuruganX
0 siblings, 0 replies; 15+ messages in thread
From: Ramuthevar, Vadivel MuruganX @ 2020-10-22 9:14 UTC (permalink / raw)
To: Pratyush Yadav
Cc: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi,
robh+dt, devicetree, miquel.raynal, simon.k.r.goldschmidt,
dinguyen, richard, cheol.yong.kim, qi-ming.wu
Hi,
On 22/10/2020 5:01 pm, Pratyush Yadav wrote:
> On 22/10/20 10:17AM, Ramuthevar, Vadivel MuruganX wrote:
>> Hi Pratyush,
>>
>> On 21/10/2020 11:17 pm, Pratyush Yadav wrote:
>>> Hi,
>>>
>>> On 21/10/20 10:55AM, Ramuthevar,Vadivel MuruganX wrote:
>>>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>>>
>>>> On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
>>>> Direct Access Controller(DAC).
>>>>
>>>> This patch adds a quirk to disable the Direct Access Controller
>>>> for data transfer instead it uses indirect data transfer.
>>>>
>>>> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>>> ---
>>>> drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
>>>> 1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
>>>> index d7b10c46fa70..3d017b484114 100644
>>>> --- a/drivers/spi/spi-cadence-quadspi.c
>>>> +++ b/drivers/spi/spi-cadence-quadspi.c
>>>> @@ -1106,6 +1106,13 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
>>>> reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
>>>> writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
>>>> + /* Disable direct access controller */
>>>> + if (!cqspi->use_direct_mode) {
>>>> + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
>>>> + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
>>>> + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
>>>> + }
>>>> +
>>>
>>> Do you really need to disable the DAC controller? cqspi_read() and
>>> cqspi_write() already check for cqspi->use_direct_mode and avoid using
>>> direct mode if it is false. While I don't think it would do any harm I'm
>>> curious what prompted you to do this instead of just setting the quirk
>>> like cdns_qspi does.
>>>
>>> Anyway, if you do insist on doing it, it does not make any sense to set
>>> a bit and then unset it immediately after. The datasheet I have says
>>> this bit resets to 1 so the block above the code you added should be
>>> removed.
>> Thank you for your review comments..
>> yes, we need this patch to disable DAC for our SoC to avoid any conflicts in
>> future as well since Intel LGM SoC doesn't support DAC at all.
>
> I'm not sure you got my point here.
Got your point, thanks!
I understand that LGM SoCs don't
> support DAC. I'm not arguing if this _patch_ is needed. I'm arguing if
> this _hunk_ is needed.
Needed, my previous patches added DAC disabled in cqspi_read() and
cqspi_write() function then Vignesh suggested me to move
cqspi_controller_init() function part so I have add it now.
you are saying that add hunk at the end of cqspi_controller_init().
that's also okay for me, anyhow DAC should be disabled at any case.
Regards
Vadivel
Does DAC mode need to be explicitly disabled
> here? Why will the check in cqspi_read() and cqspi_write() not be
> enough?
>
> My other point is that if you absolutely need to disable DAC mode, then
> instead of the code you have added, it would make more sense to do
> something like below in cqspi_controller_init(). Because the bit resets
> to 1 so the block of code to enable it is useless [0].
>
> --- 8< ---
> diff --git a/drivers/spi/spi-cadence-quadspi.c
> b/drivers/spi/spi-cadence-quadspi.c
> index d7ad8b198a11..d2c5d448a944 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -2156,10 +2156,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
> writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
> cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
>
> - /* Enable Direct Access Controller */
> - reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
> - reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> - writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
> + /* Disable Direct Access Controller */
> + if (!cqspi->use_dac_mode) {
> + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
> + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
> + }
>
> cqspi_controller_enable(cqspi, 1);
> }
> --- >8 ---
>
> Disclaimer: not tested at all.
>
> [0] Git blames Vignesh for that block of code added in a27f2eaf2b27.
> Vignesh, was this simply an oversight or was there any real reason to
> set the bit?
>
>> Regards
>> Vadivel
>>>
>>>> cqspi_controller_enable(cqspi, 1);
>>>> }
>>>> @@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi = {
>>>> .quirks = CQSPI_NEEDS_WR_DELAY,
>>>> };
>>>> +static const struct cqspi_driver_platdata intel_lgm_qspi = {
>>>> + .quirks = CQSPI_DISABLE_DAC_MODE,
>>>> +};
>>>> +
>>>> static const struct of_device_id cqspi_dt_ids[] = {
>>>> {
>>>> .compatible = "cdns,qspi-nor",
>>>> @@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
>>>> },
>>>> {
>>>> .compatible = "intel,lgm-qspi",
>>>> + .data = &intel_lgm_qspi,
>>>> },
>>>> { /* end of table */ }
>>>> };
>>>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
2020-10-21 2:55 [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 1/6] spi: cadence-quadspi: Add QSPI " Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 2/6] spi: cadence-quadspi: Disable the DAC " Ramuthevar,Vadivel MuruganX
@ 2020-10-21 2:55 ` Ramuthevar,Vadivel MuruganX
2020-10-21 14:46 ` Mark Brown
2020-10-21 15:13 ` Pratyush Yadav
2020-10-21 2:55 ` [PATCH v2 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
` (2 subsequent siblings)
5 siblings, 2 replies; 15+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-21 2:55 UTC (permalink / raw)
To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add multiple chipselect support for Intel LGM SoCs,
currently QSPI-NOR and QSPI-NAND supported.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
drivers/spi/spi-cadence-quadspi.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 3d017b484114..3bf6d3697631 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -38,6 +38,7 @@
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
+#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
struct cqspi_st;
@@ -75,6 +76,7 @@ struct cqspi_st {
bool is_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
+ u32 num_chipselect;
bool rclk_en;
u32 trigger_address;
u32 wr_delay;
@@ -1070,6 +1072,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
return -ENXIO;
}
+ if (!cqspi->use_direct_mode) {
+ if (of_property_read_u32(np, "num-chipselect",
+ &cqspi->num_chipselect)) {
+ dev_err(dev, "couldn't determine number of cs\n");
+ return -ENXIO;
+ }
+ }
+
cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
return 0;
@@ -1307,6 +1317,9 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->current_cs = -1;
cqspi->sclk = 0;
+ if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
+ master->num_chipselect = cqspi->num_chipselect;
+
ret = cqspi_setup_flash(cqspi);
if (ret) {
dev_err(dev, "failed to setup flash parameters %d\n", ret);
@@ -1396,6 +1409,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
};
static const struct cqspi_driver_platdata intel_lgm_qspi = {
+ .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
.quirks = CQSPI_DISABLE_DAC_MODE,
};
--
2.11.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
2020-10-21 2:55 ` [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
@ 2020-10-21 14:46 ` Mark Brown
2020-10-21 15:13 ` Pratyush Yadav
1 sibling, 0 replies; 15+ messages in thread
From: Mark Brown @ 2020-10-21 14:46 UTC (permalink / raw)
To: Ramuthevar,Vadivel MuruganX
Cc: vigneshr, tudor.ambarus, linux-kernel, linux-spi, robh+dt,
devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
richard, cheol.yong.kim, qi-ming.wu
[-- Attachment #1: Type: text/plain, Size: 755 bytes --]
On Wed, Oct 21, 2020 at 10:55:04AM +0800, Ramuthevar,Vadivel MuruganX wrote:
> Add multiple chipselect support for Intel LGM SoCs,
> currently QSPI-NOR and QSPI-NAND supported.
> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
> + master->num_chipselect = cqspi->num_chipselect;
I'm not seeing anywhere else where we reference num_chipselect in this
patch - we parse the value, set it in the SPI controller and then never
otherwise use it? This makes me wonder if the property is really
mandatory. If it is then there should be something in the binding
document saying that it's required when the compatible is your new
compatible string, that way the validation can verify that the property
is present in DTs including this controller.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
2020-10-21 2:55 ` [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
2020-10-21 14:46 ` Mark Brown
@ 2020-10-21 15:13 ` Pratyush Yadav
2020-10-22 2:07 ` Ramuthevar, Vadivel MuruganX
1 sibling, 1 reply; 15+ messages in thread
From: Pratyush Yadav @ 2020-10-21 15:13 UTC (permalink / raw)
To: Ramuthevar,Vadivel MuruganX
Cc: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi,
robh+dt, devicetree, miquel.raynal, simon.k.r.goldschmidt,
dinguyen, richard, cheol.yong.kim, qi-ming.wu
Hi,
On 21/10/20 10:55AM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>
> Add multiple chipselect support for Intel LGM SoCs,
> currently QSPI-NOR and QSPI-NAND supported.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
> drivers/spi/spi-cadence-quadspi.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
> index 3d017b484114..3bf6d3697631 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -38,6 +38,7 @@
>
> /* Capabilities */
> #define CQSPI_SUPPORTS_OCTAL BIT(0)
> +#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
>
> struct cqspi_st;
>
> @@ -75,6 +76,7 @@ struct cqspi_st {
> bool is_decoded_cs;
> u32 fifo_depth;
> u32 fifo_width;
> + u32 num_chipselect;
> bool rclk_en;
> u32 trigger_address;
> u32 wr_delay;
> @@ -1070,6 +1072,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
> return -ENXIO;
> }
>
> + if (!cqspi->use_direct_mode) {
Shouldn't this be guarded by CQSPI_SUPPORTS_MULTI_CHIPSELECT instead of
cqspi->use_direct_mode?
Also, cqspi->use_direct_mode would always be false here because
cqspi_of_get_pdata() is called before we set it...
> + if (of_property_read_u32(np, "num-chipselect",
> + &cqspi->num_chipselect)) {
> + dev_err(dev, "couldn't determine number of cs\n");
> + return -ENXIO;
... so even if someone doesn't want to use multiple chip selects they
would have to specify this property or the probe will fail, which is the
case on J721E EVM for example.
> + }
> + }
> +
> cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
>
> return 0;
> @@ -1307,6 +1317,9 @@ static int cqspi_probe(struct platform_device *pdev)
> cqspi->current_cs = -1;
> cqspi->sclk = 0;
>
> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
> + master->num_chipselect = cqspi->num_chipselect;
> +
> ret = cqspi_setup_flash(cqspi);
> if (ret) {
> dev_err(dev, "failed to setup flash parameters %d\n", ret);
> @@ -1396,6 +1409,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
> };
>
> static const struct cqspi_driver_platdata intel_lgm_qspi = {
> + .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
> .quirks = CQSPI_DISABLE_DAC_MODE,
> };
>
> --
> 2.11.0
>
--
Regards,
Pratyush Yadav
Texas Instruments India
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
2020-10-21 15:13 ` Pratyush Yadav
@ 2020-10-22 2:07 ` Ramuthevar, Vadivel MuruganX
0 siblings, 0 replies; 15+ messages in thread
From: Ramuthevar, Vadivel MuruganX @ 2020-10-22 2:07 UTC (permalink / raw)
To: Pratyush Yadav
Cc: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi,
robh+dt, devicetree, miquel.raynal, simon.k.r.goldschmidt,
dinguyen, richard, cheol.yong.kim, qi-ming.wu
Hi Pratyush,
On 21/10/2020 11:13 pm, Pratyush Yadav wrote:
> Hi,
>
> On 21/10/20 10:55AM, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> Add multiple chipselect support for Intel LGM SoCs,
>> currently QSPI-NOR and QSPI-NAND supported.
>>
>> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>> ---
>> drivers/spi/spi-cadence-quadspi.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
>> index 3d017b484114..3bf6d3697631 100644
>> --- a/drivers/spi/spi-cadence-quadspi.c
>> +++ b/drivers/spi/spi-cadence-quadspi.c
>> @@ -38,6 +38,7 @@
>>
>> /* Capabilities */
>> #define CQSPI_SUPPORTS_OCTAL BIT(0)
>> +#define CQSPI_SUPPORTS_MULTI_CHIPSELECT BIT(1)
>>
>> struct cqspi_st;
>>
>> @@ -75,6 +76,7 @@ struct cqspi_st {
>> bool is_decoded_cs;
>> u32 fifo_depth;
>> u32 fifo_width;
>> + u32 num_chipselect;
>> bool rclk_en;
>> u32 trigger_address;
>> u32 wr_delay;
>> @@ -1070,6 +1072,14 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
>> return -ENXIO;
>> }
>>
>> + if (!cqspi->use_direct_mode) {
>
> Shouldn't this be guarded by CQSPI_SUPPORTS_MULTI_CHIPSELECT instead of
> cqspi->use_direct_mode?
Yes, we can use CQSPI_SUPPORTS_MULTI_CHIPSELECT instead of
cqspi->use_direct_mode
>
> Also, cqspi->use_direct_mode would always be false here because
> cqspi_of_get_pdata() is called before we set it...
Good catch, thanks!
Regards
Vadivel
>
>> + if (of_property_read_u32(np, "num-chipselect",
>> + &cqspi->num_chipselect)) {
>> + dev_err(dev, "couldn't determine number of cs\n");
>> + return -ENXIO;
>
> ... so even if someone doesn't want to use multiple chip selects they
> would have to specify this property or the probe will fail, which is the
> case on J721E EVM for example.
>
>> + }
>> + }
>> +
>> cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
>>
>> return 0;
>> @@ -1307,6 +1317,9 @@ static int cqspi_probe(struct platform_device *pdev)
>> cqspi->current_cs = -1;
>> cqspi->sclk = 0;
>>
>> + if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
>> + master->num_chipselect = cqspi->num_chipselect;
>> +
>> ret = cqspi_setup_flash(cqspi);
>> if (ret) {
>> dev_err(dev, "failed to setup flash parameters %d\n", ret);
>> @@ -1396,6 +1409,7 @@ static const struct cqspi_driver_platdata am654_ospi = {
>> };
>>
>> static const struct cqspi_driver_platdata intel_lgm_qspi = {
>> + .hwcaps_mask = CQSPI_SUPPORTS_MULTI_CHIPSELECT,
>> .quirks = CQSPI_DISABLE_DAC_MODE,
>> };
>>
>> --
>> 2.11.0
>>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
2020-10-21 2:55 [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
` (2 preceding siblings ...)
2020-10-21 2:55 ` [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support " Ramuthevar,Vadivel MuruganX
@ 2020-10-21 2:55 ` Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
2020-10-21 2:55 ` [PATCH v2 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
5 siblings, 0 replies; 15+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-21 2:55 UTC (permalink / raw)
To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to
Documentation/devicetree/bindings/spi/
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (100%)
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
similarity index 100%
rename from Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
rename to Documentation/devicetree/bindings/spi/cadence-quadspi.txt
--
2.11.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
2020-10-21 2:55 [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
` (3 preceding siblings ...)
2020-10-21 2:55 ` [PATCH v2 4/6] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi Ramuthevar,Vadivel MuruganX
@ 2020-10-21 2:55 ` Ramuthevar,Vadivel MuruganX
2020-10-21 12:40 ` Mark Brown
2020-10-21 2:55 ` [PATCH v2 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC Ramuthevar,Vadivel MuruganX
5 siblings, 1 reply; 15+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-21 2:55 UTC (permalink / raw)
To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
.../devicetree/bindings/spi/cadence-quadspi.txt | 67 ----------
.../devicetree/bindings/spi/cadence-quadspi.yaml | 148 +++++++++++++++++++++
2 files changed, 148 insertions(+), 67 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
deleted file mode 100644
index 945be7d5b236..000000000000
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Cadence Quad SPI controller
-
-Required properties:
-- compatible : should be one of the following:
- Generic default - "cdns,qspi-nor".
- For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
- For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
-- reg : Contains two entries, each of which is a tuple consisting of a
- physical address and length. The first entry is the address and
- length of the controller register set. The second entry is the
- address and length of the QSPI Controller data area.
-- interrupts : Unit interrupt specifier for the controller interrupt.
-- clocks : phandle to the Quad SPI clock.
-- cdns,fifo-depth : Size of the data FIFO in words.
-- cdns,fifo-width : Bus width of the data FIFO in bytes.
-- cdns,trigger-address : 32-bit indirect AHB trigger address.
-
-Optional properties:
-- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
-- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
- the read data rather than the QSPI clock. Make sure that QSPI return
- clock is populated on the board before using this property.
-
-Optional subnodes:
-Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
-custom properties:
-- cdns,read-delay : Delay for read capture logic, in clock cycles
-- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
- mode chip select outputs are de-asserted between
- transactions.
-- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
- de-activated and the activation of another.
-- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
- transaction and deasserting the device chip select
- (qspi_n_ss_out).
-- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
- and first bit transfer.
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include either "qspi" and/or "qspi-ocp".
-
-Example:
-
- qspi: spi@ff705000 {
- compatible = "cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xff705000 0x1000>,
- <0xffa00000 0x1000>;
- interrupts = <0 151 4>;
- clocks = <&qspi_clk>;
- cdns,is-decoded-cs;
- cdns,fifo-depth = <128>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x00000000>;
- resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
- reset-names = "qspi", "qspi-ocp";
-
- flash0: n25q00@0 {
- ...
- cdns,read-delay = <4>;
- cdns,tshsl-ns = <50>;
- cdns,tsd2d-ns = <50>;
- cdns,tchsh-ns = <4>;
- cdns,tslch-ns = <4>;
- };
- };
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
new file mode 100644
index 000000000000..57be1a730e7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence Quad SPI controller
+
+maintainers:
+ - Vadivel Murugan <vadivel.muruganx.ramuthevar@intel.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: cdns,qspi-nor
+ - const: ti,k2g-qspi, cdns,qspi-nor
+ - const: ti,am654-ospi, cdns,qspi-nor
+
+ reg:
+ items:
+ - description: the controller register set
+ - description: the controller data area
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ cdns,fifo-depth:
+ description:
+ Size of the data FIFO in words.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 128, 256 ]
+ default: 128
+
+ cdns,fifo-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Bus width of the data FIFO in bytes.
+ default: 4
+
+ cdns,trigger-address:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ 32-bit indirect AHB trigger address.
+
+ cdns,is-decoded-cs:
+ type: boolean
+ description:
+ Flag to indicate whether decoder is used or not.
+
+ cdns,rclk-en:
+ type: boolean
+ description:
+ Flag to indicate that QSPI return clock is used to latch the read
+ data rather than the QSPI clock. Make sure that QSPI return clock
+ is populated on the board before using this property.
+
+ resets:
+ maxItems : 2
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum: [ qspi, qspi-ocp ]
+
+# subnode's properties
+patternProperties:
+ "@[0-9a-f]+$":
+ type: object
+ description:
+ flash device uses the subnodes below defined properties.
+
+ cdns,read-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Delay for read capture logic, in clock cycles.
+
+ cdns,tshsl-ns:
+ description: |
+ Delay in nanoseconds for the length that the master mode chip select
+ outputs are de-asserted between transactions.
+
+ cdns,tsd2d-ns:
+ description: |
+ Delay in nanoseconds between one chip select being de-activated
+ and the activation of another.
+
+ cdns,tchsh-ns:
+ description: |
+ Delay in nanoseconds between last bit of current transaction and
+ deasserting the device chip select (qspi_n_ss_out).
+
+ cdns,tslch-ns:
+ description: |
+ Delay in nanoseconds between setting qspi_n_ss_out low and
+ first bit transfer.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - cdns,fifo-depth
+ - cdns,fifo-width
+ - cdns,trigger-address
+ - cdns,is-decoded-cs
+ - cdns,rclk-en
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ qspi: spi@ff705000 {
+ compatible = "cadence,qspi","cdns,qpsi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ resets = <&rst 0x1>, <&rst 0x2>;
+ reset-names = "qspi", "qspi-ocp";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+
+ };
+
+...
--
2.11.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml
2020-10-21 2:55 ` [PATCH v2 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
@ 2020-10-21 12:40 ` Mark Brown
0 siblings, 0 replies; 15+ messages in thread
From: Mark Brown @ 2020-10-21 12:40 UTC (permalink / raw)
To: Ramuthevar,Vadivel MuruganX
Cc: vigneshr, tudor.ambarus, linux-kernel, linux-spi, robh+dt,
devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
richard, cheol.yong.kim, qi-ming.wu
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On Wed, Oct 21, 2020 at 10:55:06AM +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>
> Convert the cadence-quadspi.txt documentation to cadence-quadspi.yaml
> remove the cadence-quadspi.txt from Documentation/devicetree/bindings/spi/
This is patch 5/6, not patch 6/6 as I suggested :/
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 6/6] dt-bindings: spi: Add compatible for Intel LGM SoC
2020-10-21 2:55 [PATCH v2 0/6] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC Ramuthevar,Vadivel MuruganX
` (4 preceding siblings ...)
2020-10-21 2:55 ` [PATCH v2 5/6] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Ramuthevar,Vadivel MuruganX
@ 2020-10-21 2:55 ` Ramuthevar,Vadivel MuruganX
5 siblings, 0 replies; 15+ messages in thread
From: Ramuthevar,Vadivel MuruganX @ 2020-10-21 2:55 UTC (permalink / raw)
To: vigneshr, tudor.ambarus, broonie, linux-kernel, linux-spi, robh+dt
Cc: devicetree, miquel.raynal, simon.k.r.goldschmidt, dinguyen,
richard, cheol.yong.kim, qi-ming.wu, Ramuthevar Vadivel Murugan
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add compatible string for Intel LGM SoC.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
Documentation/devicetree/bindings/spi/cadence-quadspi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
index 57be1a730e7b..44378d2d2b9e 100644
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
@@ -19,6 +19,7 @@ properties:
- const: cdns,qspi-nor
- const: ti,k2g-qspi, cdns,qspi-nor
- const: ti,am654-ospi, cdns,qspi-nor
+ - const: intel,lgm-qspi, cdns,qspi-nor
reg:
items:
--
2.11.0
^ permalink raw reply related [flat|nested] 15+ messages in thread