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From: Serge Semin <fancer.lancer@gmail.com>
To: Damien Le Moal <damien.lemoal@wdc.com>
Cc: Mark Brown <broonie@kernel.org>,
	linux-spi@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org, Sean Anderson <seanga2@gmail.com>
Subject: Re: [PATCH 2/3] spi: dw: Add support for the Canaan K210 SoC SPI
Date: Wed, 25 Nov 2020 15:52:52 +0300	[thread overview]
Message-ID: <20201125125252.s4ui5x2xxt2djdtp@mobilestation> (raw)
In-Reply-To: <20201119120253.390883-3-damien.lemoal@wdc.com>

On Thu, Nov 19, 2020 at 09:02:52PM +0900, Damien Le Moal wrote:
> The Canaan Kendryte K210 RISC-V SoC includes a DW apb_ssi v4 controller
> which is documented to have a 32 words deep TX and RX FIFO. The FIFO
> length detection in spi_hw_init() correctly detects this value.
> However, when the controller RX FIFO is filled up to 32 entries
> (RXFLR = 32), an RX FIFO overrun error occurs. This likely due to a
> hardware bug which can be avoided by force setting the fifo_len field of
> struct dw_spi to 31.
> 
> Define the dw_spi_canaan_k210_init() function to force set fifo_len to
> 31 when the device node compatible string is "canaan,k210-spi".

Looking good. Thanks.
Acked-by: Serge Semin <fancer.lancer@gmail.com>

> 
> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
> ---
>  drivers/spi/spi-dw-mmio.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
> index d0cc5bf4fa4e..17c06039a74d 100644
> --- a/drivers/spi/spi-dw-mmio.c
> +++ b/drivers/spi/spi-dw-mmio.c
> @@ -222,6 +222,21 @@ static int dw_spi_keembay_init(struct platform_device *pdev,
>  	return 0;
>  }
>  
> +static int dw_spi_canaan_k210_init(struct platform_device *pdev,
> +				   struct dw_spi_mmio *dwsmmio)
> +{
> +	/*
> +	 * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
> +	 * documented to have a 32 word deep TX and RX FIFO, which
> +	 * spi_hw_init() detects. However, when the RX FIFO is filled up to
> +	 * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this
> +	 * problem by force setting fifo_len to 31.
> +	 */
> +	dwsmmio->dws.fifo_len = 31;
> +
> +	return 0;
> +}
> +
>  static int dw_spi_mmio_probe(struct platform_device *pdev)
>  {
>  	int (*init_func)(struct platform_device *pdev,
> @@ -335,6 +350,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
>  	{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
>  	{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
>  	{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
> +	{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
>  	{ /* end of table */}
>  };
>  MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
> -- 
> 2.28.0
> 

  reply	other threads:[~2020-11-25 12:53 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-19 12:02 [PATCH 0/3] DW apb_ssi V4 support for Kendryte K210 RISC-V SoC Damien Le Moal
2020-11-19 12:02 ` [PATCH 1/3] spi: dw: Add support for 32-bits max xfer size Damien Le Moal
2020-11-25 19:52   ` Serge Semin
2020-11-26  4:55     ` Sean Anderson
2020-11-26  7:23       ` Damien Le Moal
2020-11-19 12:02 ` [PATCH 2/3] spi: dw: Add support for the Canaan K210 SoC SPI Damien Le Moal
2020-11-25 12:52   ` Serge Semin [this message]
2020-11-19 12:02 ` [PATCH 3/3] dt-bindings: Update Synopsis DW apb ssi bindings Damien Le Moal
2020-11-25 12:50   ` Serge Semin

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