From: Damien Le Moal <Damien.LeMoal@wdc.com>
To: Sean Anderson <seanga2@gmail.com>, Serge Semin <fancer.lancer@gmail.com>
Cc: Mark Brown <broonie@kernel.org>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 1/3] spi: dw: Add support for 32-bits max xfer size
Date: Thu, 26 Nov 2020 07:23:48 +0000 [thread overview]
Message-ID: <CH2PR04MB65223BD289204982B3A676C7E7F90@CH2PR04MB6522.namprd04.prod.outlook.com> (raw)
In-Reply-To: 82628758-d7a0-299c-51d1-4960dcea2809@gmail.com
On 2020/11/26 13:55, Sean Anderson wrote:
> On 11/25/20 2:52 PM, Serge Semin wrote:
[...]
>>> + if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) {
>>> + u32 cr0;
>>> +
>>> + /*
>>> + * Detect APB SSI CTRLR0 size by looking at the data
>>> + * frame size field.
>>> + */
>>
>>> + dw_writel(dws, DW_SPI_CTRLR0, 0xffffffff);
>>
>> This isn't going to work because you need to disable the SSI controller
>> first. Then please revert the change or cleanup the register and disable
>> the controller back after finishing the detection.
>
> In U-Boot at least, ctrlr0 is written before every transfer, so there is
> no need to restore it afterward. Same for enr. I don't know whether this
> holds true for Linux.
Same in Linux too. The base value for cr0 is prepared and saved in chip->cr0
field when the controller is scanned/reset and that saved base value is used for
updating cr0 on every transfer. Serge point here was to have the DFS32 detection
not result in the initial cr0 value changing, as some older versions of the DW
controller may react to it. The cr0 save/restore in the detection does not
matter for the K210 though. Since this is only done on scan/reset and not in the
fast path, I think it is OK and definitely safer.
--
Damien Le Moal
Western Digital Research
next prev parent reply other threads:[~2020-11-26 7:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 12:02 [PATCH 0/3] DW apb_ssi V4 support for Kendryte K210 RISC-V SoC Damien Le Moal
2020-11-19 12:02 ` [PATCH 1/3] spi: dw: Add support for 32-bits max xfer size Damien Le Moal
2020-11-25 19:52 ` Serge Semin
2020-11-26 4:55 ` Sean Anderson
2020-11-26 7:23 ` Damien Le Moal [this message]
2020-11-19 12:02 ` [PATCH 2/3] spi: dw: Add support for the Canaan K210 SoC SPI Damien Le Moal
2020-11-25 12:52 ` Serge Semin
2020-11-19 12:02 ` [PATCH 3/3] dt-bindings: Update Synopsis DW apb ssi bindings Damien Le Moal
2020-11-25 12:50 ` Serge Semin
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