[PATCH] mpc52xx_psc_spi: enlarge clock range

[PATCH] mpc52xx_psc_spi: enlarge clock range

[Dragos Carp]

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allow spi clock values bellow 78kbps down to ca. 300bps

Signed-off-by: Dragos Carp <dragos.carp-+ybMorV4k0dBDgjK7y7TUQ@public.gmane.org>
---
 mpc52xx_psc_spi.c |   26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)


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diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c
index 1b74d5c..b15882a 100644
--- a/drivers/spi/mpc52xx_psc_spi.c
+++ b/drivers/spi/mpc52xx_psc_spi.c
@@ -78,7 +78,8 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
 	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 	struct mpc52xx_psc __iomem *psc = mps->psc;
 	u32 sicr;
-	u16 ccr;
+	u32 ccr;
+	u32 bitclkdiv;
 
 	sicr = in_be32(&psc->sicr);
 
@@ -98,17 +99,16 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
 		sicr &= ~0x10000000;
 	out_be32(&psc->sicr, sicr);
 
-	/* Set clock frequency and bits per word
-	 * Because psc->ccr is defined as 16bit register instead of 32bit
-	 * just set the lower byte of BitClkDiv
-	 */
-	ccr = in_be16((u16 __iomem *)&psc->ccr);
-	ccr &= 0xFF00;
-	if (cs->speed_hz)
-		ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
-	else /* by default SPI Clk 1MHz */
-		ccr |= (MCLK / 1000000 - 1) & 0xFF;
-	out_be16((u16 __iomem *)&psc->ccr, ccr);
+	/* Set clock frequency */
+	bitclkdiv = MCLK / (cs->speed_hz ? cs->speed_hz : 1000000) - 1;
+	bitclkdiv &= 0xFFFF;
+	bitclkdiv |= (bitclkdiv & 0xFF) << 16;	/* byte swapped */
+	bitclkdiv &= 0x00FFFF00;
+	ccr = in_be32(&psc->ccr);
+	ccr &= 0xFF0000FF;
+	ccr |= bitclkdiv;
+	out_be32(&psc->ccr, ccr);
+	
 	mps->bits_per_word = cs->bits_per_word;
 
 	if (mps->cs_control)
@@ -333,7 +333,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
 	/* Configure 8bit codec mode as a SPI master and use EOF flags */
 	/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
 	out_be32(&psc->sicr, 0x0180C800);
-	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
+	out_be32(&psc->ccr, 0x07130000); /* default SPI Clk 1MHz */
 
 	/* Set 2ms DTL delay */
 	out_8(&psc->ctur, 0x00);

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Re: [spi-devel-general] [PATCH] mpc52xx_psc_spi: enlarge clock range

[Wolfram Sang]

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Hi,

adding powerpc-list and Grant to cc.

On Wed, Sep 16, 2009 at 01:07:50PM +0200, Dragos Carp wrote:
> allow spi clock values bellow 78kbps down to ca. 300bps

Looks like your patch converts the driver from mpc5200 to mpc5200b? If this is
really all which is needed, it should support both versions, I think.

Regards,

   Wolfram

> 
> Signed-off-by: Dragos Carp <dragos.carp@toptica.com>
> ---
>  mpc52xx_psc_spi.c |   26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 

> diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c
> index 1b74d5c..b15882a 100644
> --- a/drivers/spi/mpc52xx_psc_spi.c
> +++ b/drivers/spi/mpc52xx_psc_spi.c
> @@ -78,7 +78,8 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
>  	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
>  	struct mpc52xx_psc __iomem *psc = mps->psc;
>  	u32 sicr;
> -	u16 ccr;
> +	u32 ccr;
> +	u32 bitclkdiv;
>  
>  	sicr = in_be32(&psc->sicr);
>  
> @@ -98,17 +99,16 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
>  		sicr &= ~0x10000000;
>  	out_be32(&psc->sicr, sicr);
>  
> -	/* Set clock frequency and bits per word
> -	 * Because psc->ccr is defined as 16bit register instead of 32bit
> -	 * just set the lower byte of BitClkDiv
> -	 */
> -	ccr = in_be16((u16 __iomem *)&psc->ccr);
> -	ccr &= 0xFF00;
> -	if (cs->speed_hz)
> -		ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
> -	else /* by default SPI Clk 1MHz */
> -		ccr |= (MCLK / 1000000 - 1) & 0xFF;
> -	out_be16((u16 __iomem *)&psc->ccr, ccr);
> +	/* Set clock frequency */
> +	bitclkdiv = MCLK / (cs->speed_hz ? cs->speed_hz : 1000000) - 1;
> +	bitclkdiv &= 0xFFFF;
> +	bitclkdiv |= (bitclkdiv & 0xFF) << 16;	/* byte swapped */
> +	bitclkdiv &= 0x00FFFF00;
> +	ccr = in_be32(&psc->ccr);
> +	ccr &= 0xFF0000FF;
> +	ccr |= bitclkdiv;
> +	out_be32(&psc->ccr, ccr);
> +	
>  	mps->bits_per_word = cs->bits_per_word;
>  
>  	if (mps->cs_control)
> @@ -333,7 +333,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
>  	/* Configure 8bit codec mode as a SPI master and use EOF flags */
>  	/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
>  	out_be32(&psc->sicr, 0x0180C800);
> -	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
> +	out_be32(&psc->ccr, 0x07130000); /* default SPI Clk 1MHz */
>  
>  	/* Set 2ms DTL delay */
>  	out_8(&psc->ctur, 0x00);

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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Re: [PATCH] mpc52xx_psc_spi: enlarge clock range

[Dragos Carp]

Hi,

I wasn't aware that MPC5200 differ from MPC5200B in this regard. I also
couldn't find any MPC5200 user manual on Freescale's webpage.
Is there a #define that I can use to distinguish between the two
processor variants? Querying the PVR register is not a nice solution
because the chip-select activate function is called in some scenarios
quite often.

Regards,
Dragos


On 09/16/2009 10:48 PM, Wolfram Sang wrote:
> Hi,
>
> adding powerpc-list and Grant to cc.
>
> On Wed, Sep 16, 2009 at 01:07:50PM +0200, Dragos Carp wrote:
>   
>> allow spi clock values bellow 78kbps down to ca. 300bps
>>     
> Looks like your patch converts the driver from mpc5200 to mpc5200b? If this is
> really all which is needed, it should support both versions, I think.
>
> Regards,
>
>    Wolfram
>
>   
>> Signed-off-by: Dragos Carp <dragos.carp-+ybMorV4k0dBDgjK7y7TUQ@public.gmane.org>
>> ---
>>  mpc52xx_psc_spi.c |   26 +++++++++++++-------------
>>  1 file changed, 13 insertions(+), 13 deletions(-)
>>
>>     
>   
>> diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c
>> index 1b74d5c..b15882a 100644
>> --- a/drivers/spi/mpc52xx_psc_spi.c
>> +++ b/drivers/spi/mpc52xx_psc_spi.c
>> @@ -78,7 +78,8 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
>>  	struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
>>  	struct mpc52xx_psc __iomem *psc = mps->psc;
>>  	u32 sicr;
>> -	u16 ccr;
>> +	u32 ccr;
>> +	u32 bitclkdiv;
>>  
>>  	sicr = in_be32(&psc->sicr);
>>  
>> @@ -98,17 +99,16 @@ static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
>>  		sicr &= ~0x10000000;
>>  	out_be32(&psc->sicr, sicr);
>>  
>> -	/* Set clock frequency and bits per word
>> -	 * Because psc->ccr is defined as 16bit register instead of 32bit
>> -	 * just set the lower byte of BitClkDiv
>> -	 */
>> -	ccr = in_be16((u16 __iomem *)&psc->ccr);
>> -	ccr &= 0xFF00;
>> -	if (cs->speed_hz)
>> -		ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
>> -	else /* by default SPI Clk 1MHz */
>> -		ccr |= (MCLK / 1000000 - 1) & 0xFF;
>> -	out_be16((u16 __iomem *)&psc->ccr, ccr);
>> +	/* Set clock frequency */
>> +	bitclkdiv = MCLK / (cs->speed_hz ? cs->speed_hz : 1000000) - 1;
>> +	bitclkdiv &= 0xFFFF;
>> +	bitclkdiv |= (bitclkdiv & 0xFF) << 16;	/* byte swapped */
>> +	bitclkdiv &= 0x00FFFF00;
>> +	ccr = in_be32(&psc->ccr);
>> +	ccr &= 0xFF0000FF;
>> +	ccr |= bitclkdiv;
>> +	out_be32(&psc->ccr, ccr);
>> +	
>>  	mps->bits_per_word = cs->bits_per_word;
>>  
>>  	if (mps->cs_control)
>> @@ -333,7 +333,7 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
>>  	/* Configure 8bit codec mode as a SPI master and use EOF flags */
>>  	/* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
>>  	out_be32(&psc->sicr, 0x0180C800);
>> -	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
>> +	out_be32(&psc->ccr, 0x07130000); /* default SPI Clk 1MHz */
>>  
>>  	/* Set 2ms DTL delay */
>>  	out_8(&psc->ctur, 0x00);
>>     
>   



------------------------------------------------------------------------------
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Re: [spi-devel-general] [PATCH] mpc52xx_psc_spi: enlarge clock range

[Grant Likely]

On Thu, Sep 17, 2009 at 8:04 AM, Dragos Carp <dragos.carp@toptica.com> wrote:
> Hi,
>
> I wasn't aware that MPC5200 differ from MPC5200B in this regard. I also
> couldn't find any MPC5200 user manual on Freescale's webpage.
> Is there a #define that I can use to distinguish between the two
> processor variants? Querying the PVR register is not a nice solution
> because the chip-select activate function is called in some scenarios
> quite often.

Use the compatible value.  That's what it is there for.  Only use the
extended register format if "fsl,mpc5200b-psc-spi" is present in the
compatible list.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH] mpc52xx_psc_spi: enlarge clock range

[Wolfram Sang]

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> I wasn't aware that MPC5200 differ from MPC5200B in this regard. I also
> couldn't find any MPC5200 user manual on Freescale's webpage.

Hmm, it was the first hit using a web search engine :)

http://www.freescale.com/files/microcontrollers/doc/user_guide/MPC5200UM.pdf?WT_TYPE=Users%20Guides&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation

> Is there a #define that I can use to distinguish between the two
> processor variants? Querying the PVR register is not a nice solution

I think you should have two different functions for calculation, one for 5200
and one for 5200B. During init query the device tree for 'fsl,mpc5200-psc-spi'
or 'fsl,mpc5200b-psc-spi' and make the driver use the proper function.

(BTW I haven't checked for further differences between 5200 and 5200B; there
may be more)

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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Come build with us! The BlackBerry® Developer Conference in SF, CA
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developing skills, take BlackBerry mobile applications to market and stay 
ahead of the curve. Join us from November 9-12, 2009. Register now!
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