Re: [PATCH] pwm: sun4i: Avoid waiting until the next period

From: Emil Lenngren <emil.lenngren@gmail.com>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: Roman Beranek <roman.beranek@prusa3d.cz>,
	Thierry Reding <thierry.reding@gmail.com>,
	 Lee Jones <lee.jones@linaro.org>,
	Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	 Jernej Skrabec <jernej.skrabec@siol.net>,
	linux-pwm@vger.kernel.org,  linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev,  linux-sunxi@googlegroups.com,
	Roman Beranek <roman.beranek@prusa3d.com>
Subject: Re: [PATCH] pwm: sun4i: Avoid waiting until the next period
Date: Wed, 12 May 2021 11:18:24 +0200	[thread overview]
Message-ID: <CAO1O6sfZ0O7JExw07UytBcNROc9TQsu9bBp-+zFF3824PxxvRA@mail.gmail.com> (raw)
In-Reply-To: <20210512044133.6yfwyluzdx6yfh4c@pengutronix.de>

Hi Uwe,

Den ons 12 maj 2021 kl 06:41 skrev Uwe Kleine-König
<u.kleine-koenig@pengutronix.de>:
>
> Hello Emil,
>
> On Wed, May 12, 2021 at 02:55:26AM +0200, Emil Lenngren wrote:
> > Well that's one way of "solving it" ;)
> >
> > But on what hardware do you really need to wait until one full pulse
> > cycle ends, before a disable command takes effect?
> >
> > On the hardware I've tested on (GR8 and V3s), it's enough to wait at
> > most two clock cycles in order for it to take effect before we can
> > close the gate. And with clock cycle I mean 24 MHz divided by the
> > prescaler. With prescaler 1, that's 84 nanoseconds. By closing the
> > gate when the pwm should be disabled, I guess we could save some
> > nanoampere or microampere (is this important?)
>
> If I understood correctly you really have to wait longer to achieve that
> the output is inactive in the disabled state. Do you talk about the same
> thing?

Exactly, i.e. after writing 0 to the EN bit, we don't have to wait
until the current period ends before we can observe that the output
signal goes to the inactive state.

Simple test:

1. Set pwm interval to a long time like 2 seconds, and duty to 50%.
2. Enable clock gating.
3. Enable the pwm by writing 1 to the EN bit.
4. Observe the LED blink once per second.
5. Now at a random time write 0 to the EN bit in order to disable the
pwm. Don't turn off the clock gating.
6. If you just look with the eye it appears the LED turns off
immediately, regardless of when in the pulse cycle we disabled it.

Just tested the above using "devmem" on a V3s.

By using a large prescaler and testing some different prescalers, I've
concluded that it takes at least 1 and at most 2 clock cycles before
we can safely turn off the gate and be certain that the output pin has
changed to disabled.

It would be good if people having other hardware could confirm this is
correct there as well.

Please take a look at some previous material I wrote:
https://lkml.org/lkml/2020/3/17/1158
https://linux-sunxi.org/PWM_Controller_Register_Guide (Observed
behaviour on GR8 from NextThing)
https://pastebin.com/GWrhWzPJ

/Emil