From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
<stefank@nvidia.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>
Cc: Jassi Brar <jassisinghbrar@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Joe Perches <joe@perches.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-tegra@vger.kernel.org>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v5 4/5] dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCs
Date: Mon, 29 May 2023 16:50:49 +0300 [thread overview]
Message-ID: <20230529135044.2746339-5-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <20230529135044.2746339-1-pdeschrijver@nvidia.com>
Add memory-region property to the tegra186-bpmp binding to support
DRAM MRQ GSCs.
Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
.../firmware/nvidia,tegra186-bpmp.yaml | 39 ++++++++++++++++---
1 file changed, 34 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
index 833c07f1685c..c43d17f6e96b 100644
--- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
+++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
@@ -57,8 +57,11 @@ description: |
"#address-cells" or "#size-cells" property.
The shared memory area for the IPC TX and RX between CPU and BPMP are
- predefined and work on top of sysram, which is an SRAM inside the
- chip. See ".../sram/sram.yaml" for the bindings.
+ predefined and work on top of either sysram, which is an SRAM inside the
+ chip, or in normal SDRAM.
+ See ".../sram/sram.yaml" for the bindings for the SRAM case.
+ See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
+ the SDRAM case.
properties:
compatible:
@@ -81,6 +84,11 @@ properties:
minItems: 2
maxItems: 2
+ memory-region:
+ description: phandle to reserved memory region used for IPC between
+ CPU-NS and BPMP.
+ maxItems: 1
+
"#clock-cells":
const: 1
@@ -115,10 +123,15 @@ properties:
additionalProperties: false
+oneOf:
+ - required:
+ - memory-region
+ - required:
+ - shmem
+
required:
- compatible
- mboxes
- - shmem
- "#clock-cells"
- "#power-domain-cells"
- "#reset-cells"
@@ -165,8 +178,7 @@ examples:
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
iommus = <&smmu TEGRA186_SID_BPMP>;
- mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
- TEGRA_HSP_DB_MASTER_BPMP>;
+ mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
#clock-cells = <1>;
#power-domain-cells = <1>;
@@ -184,3 +196,20 @@ examples:
#thermal-sensor-cells = <1>;
};
};
+
+ - |
+ #include <dt-bindings/mailbox/tegra186-hsp.h>
+
+ bpmp {
+ compatible = "nvidia,tegra186-bpmp";
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
+ interconnect-names = "read", "write", "dma-mem", "dma-write";
+ mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
+ memory-region = <&dram_cpu_bpmp_mail>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.34.1
next prev parent reply other threads:[~2023-05-29 14:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-29 13:50 [PATCH v5 0/5] firmware: tegra: Add MRQ support for Tegra264 Peter De Schrijver
2023-05-29 13:50 ` [PATCH v5 1/5] dt-bindings: mailbox: tegra: Document Tegra264 HSP Peter De Schrijver
2023-05-29 13:50 ` [PATCH v5 2/5] mailbox: tegra: add support for Tegra264 Peter De Schrijver
2023-06-20 13:12 ` Peter De Schrijver
2023-06-20 15:08 ` Jassi Brar
2023-06-21 12:06 ` Peter De Schrijver
2023-05-29 13:50 ` [PATCH v5 3/5] dt-bindings: reserved-memory: Add support for DRAM MRQ GSCs Peter De Schrijver
2023-05-29 13:50 ` Peter De Schrijver [this message]
2023-05-29 13:50 ` [PATCH v5 5/5] firmware: tegra: bpmp: " Peter De Schrijver
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230529135044.2746339-5-pdeschrijver@nvidia.com \
--to=pdeschrijver@nvidia.com \
--cc=conor+dt@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=jassisinghbrar@gmail.com \
--cc=joe@perches.com \
--cc=jonathanh@nvidia.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=stefank@nvidia.com \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).