Linux-Watchdog Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board
@ 2019-03-23 21:15 Fabien Parent
  2019-03-23 21:15 ` [PATCH 01/24] dt-bindings: regulator: add support for MT6392 Fabien Parent
                   ` (23 more replies)
  0 siblings, 24 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

The pumpkin board is designed by Gossamer Engineering and is
using a MediaTek SoC. The board currently comes in two available
version: MT8516 SoC and MT8167 SoC.

The board provides the following IOs: eMMC, NAND, SD card, USB 2 type-A,
Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in),
serial over USB, and an expansion header.

This patch series adds the basic board support to be able to boot
on the eMMC of the MT8516 based Pumpkin board.

The board is using a MT6392 PMIC.

Fabien Parent (24):
  dt-bindings: regulator: add support for MT6392
  regulator: mt6392: Add support for MT6392 regulator
  dt-bindings: pwrap: mediatek: add pwrap support for MT8516
  soc: mediatek: pwrap: add missing check on rstc
  soc: mediatek: pwrap: add support for MT8516 pwrap
  mfd: mt6397: Add support for MT6397 pmic
  arm64: dts: mt6392: Add PMIC mt6392 dtsi
  dt-bindings: mmc: mtk-sd: add mtk-sd support for MT8516
  mmc: mtk-sd: check for valid optional memory resource
  mmc: mtk-sd: add support for MT8516
  dt-bindings: mediatek: topckgen: add support for MT8516
  dt-bindings: mediatek: infracfg: add support for MT8516
  dt-bindings: mediatek: apmixedsys: add support for MT8516
  clk: mediatek: add clock driver for MT8516
  dt-bindings: pinctrl: pinctrl-mt65xx: add support for MT8516
  pinctrl: mediatek: Add MT8516 Pinctrl driver
  dt-bindings: wdog: mtk-wdt: add support for MT851
  dt-bindings: timer: mtk-timer: add support for MT8516
  dt-bindings: spi: spi-mt65xx: add support for MT8516
  dt-bindings: serial: mtk-uart: add support for MT8516
  dt-bindings: irq: mtk,sysirq: add support for MT8516
  dt-bindings: i2c: i2c-mtk: add support for MT8516
  arm64: dts: mediatek: add dtsi for MT8516
  arm64: dts: mediatek: add pumpkin board dts

 .../arm/mediatek/mediatek,apmixedsys.txt      |    1 +
 .../arm/mediatek/mediatek,infracfg.txt        |    1 +
 .../arm/mediatek/mediatek,topckgen.txt        |    1 +
 .../devicetree/bindings/i2c/i2c-mtk.txt       |    1 +
 .../interrupt-controller/mediatek,sysirq.txt  |    3 +-
 .../devicetree/bindings/mmc/mtk-sd.txt        |    1 +
 .../bindings/pinctrl/pinctrl-mt65xx.txt       |    1 +
 .../bindings/regulator/mt6392-regulator.txt   |  220 +++
 .../devicetree/bindings/serial/mtk-uart.txt   |    1 +
 .../bindings/soc/mediatek/pwrap.txt           |    1 +
 .../devicetree/bindings/spi/spi-mt65xx.txt    |    1 +
 .../bindings/timer/mediatek,mtk-timer.txt     |    1 +
 .../devicetree/bindings/watchdog/mtk-wdt.txt  |    1 +
 arch/arm64/boot/dts/mediatek/Makefile         |    1 +
 arch/arm64/boot/dts/mediatek/mt6392.dtsi      |  208 +++
 arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h |  663 +++++++++
 .../boot/dts/mediatek/mt8516-pumpkin.dts      |   19 +
 arch/arm64/boot/dts/mediatek/mt8516.dtsi      |  409 ++++++
 .../boot/dts/mediatek/pumpkin-common.dtsi     |  210 +++
 .../dts/mediatek/pumpkin-emmc-common.dtsi     |   75 ++
 drivers/clk/mediatek/Kconfig                  |    9 +
 drivers/clk/mediatek/Makefile                 |    1 +
 drivers/clk/mediatek/clk-mt8516.c             |  815 ++++++++++++
 drivers/mfd/mt6397-core.c                     |   96 ++
 drivers/mmc/host/mtk-sd.c                     |   19 +-
 drivers/pinctrl/mediatek/Kconfig              |    7 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt8516.c     |  384 ++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h | 1182 +++++++++++++++++
 drivers/regulator/Kconfig                     |    9 +
 drivers/regulator/Makefile                    |    1 +
 drivers/regulator/mt6392-regulator.c          |  490 +++++++
 drivers/soc/mediatek/mtk-pmic-wrap.c          |  109 +-
 include/dt-bindings/clock/mt8516-clk.h        |  211 +++
 include/linux/mfd/mt6392/core.h               |   42 +
 include/linux/mfd/mt6392/registers.h          |  487 +++++++
 include/linux/regulator/mt6392-regulator.h    |   40 +
 37 files changed, 5717 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
 create mode 100644 arch/arm64/boot/dts/mediatek/mt6392.dtsi
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8516.dtsi
 create mode 100644 arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
 create mode 100644 arch/arm64/boot/dts/mediatek/pumpkin-emmc-common.dtsi
 create mode 100644 drivers/clk/mediatek/clk-mt8516.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8516.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
 create mode 100644 drivers/regulator/mt6392-regulator.c
 create mode 100644 include/dt-bindings/clock/mt8516-clk.h
 create mode 100644 include/linux/mfd/mt6392/core.h
 create mode 100644 include/linux/mfd/mt6392/registers.h
 create mode 100644 include/linux/regulator/mt6392-regulator.h

-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 01/24] dt-bindings: regulator: add support for MT6392
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-03-28 19:17   ` Rob Herring
  2019-03-23 21:15 ` [PATCH 02/24] regulator: mt6392: Add support for MT6392 regulator Fabien Parent
                   ` (22 subsequent siblings)
  23 siblings, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of the regulator for MT6392 SoCs.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 .../bindings/regulator/mt6392-regulator.txt   | 220 ++++++++++++++++++
 1 file changed, 220 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/regulator/mt6392-regulator.txt

diff --git a/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
new file mode 100644
index 000000000000..edf207c838dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
@@ -0,0 +1,220 @@
+Mediatek MT6392 Regulator
+
+Required properties:
+- compatible: "mediatek,mt6392-regulator"
+- mt6392regulator: List of regulators provided by this controller. It is named
+  according to its regulator type, buck_<name> and ldo_<name>.
+  The definition for each of these nodes is defined using the standard binding
+  for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are::
+BUCK:
+  buck_vproc, buck_vsys, buck_vcore
+LDO:
+  ldo_vxo22, ldo_vaud22, ldo_vcama, ldo_vaud28, ldo_vadc18, ldo_vcn35,
+  ldo_vio28. ldo_vusb, ldo_vmc, ldo_vmch, ldo_vemc3v3, ldo_vgp1, ldo_vgp2,
+  ldo_vcn18, ldo_vcamaf, ldo_vm, ldo_vio18, ldo_vcamd, ldo_vcamio, ldo_vm25,
+  ldo_vefuse
+
+Example:
+	pmic: mt6392 {
+		compatible = "mediatek,mt6392", "mediatek,mt6323";
+		mediatek,system-power-controller;
+
+		mt6392_regulator: mt6392_regulator {
+			compatible = "mediatek,mt6392-regulator";
+
+			mt6392_vproc_reg: buck_vproc {
+				regulator-name = "buck_vproc";
+				regulator-min-microvolt = < 700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <12500>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vsys_reg: buck_vsys {
+				regulator-name = "buck_vsys";
+				regulator-min-microvolt = <1400000>;
+				regulator-max-microvolt = <2987500>;
+				regulator-ramp-delay = <25000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vcore_reg: buck_vcore {
+				regulator-name = "buck_vcore";
+				regulator-min-microvolt = < 700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <12500>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vxo22_reg: ldo_vxo22 {
+				regulator-name = "ldo_vxo22";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <2200000>;
+				regulator-enable-ramp-delay = <110>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vaud22_reg: ldo_vaud22 {
+				regulator-name = "ldo_vaud22";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <2200000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vcama_reg: ldo_vcama {
+				regulator-name = "ldo_vcama";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vaud28_reg: ldo_vaud28 {
+				regulator-name = "ldo_vaud28";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vadc18_reg: ldo_vadc18 {
+				regulator-name = "ldo_vadc18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vcn35_reg: ldo_vcn35 {
+				regulator-name = "ldo_vcn35";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vio28_reg: ldo_vio28 {
+				regulator-name = "ldo_vio28";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vusb_reg: ldo_vusb {
+				regulator-name = "ldo_vusb";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vmc_reg: ldo_vmc {
+				regulator-name = "ldo_vmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-boot-on;
+			};
+
+			mt6392_vmch_reg: ldo_vmch {
+				regulator-name = "ldo_vmch";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-boot-on;
+			};
+
+			mt6392_vemc3v3_reg: ldo_vemc3v3 {
+				regulator-name = "ldo_vemc3v3";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-boot-on;
+			};
+
+			mt6392_vgp1_reg: ldo_vgp1 {
+				regulator-name = "ldo_vgp1";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vgp2_reg: ldo_vgp2 {
+				regulator-name = "ldo_vgp2";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vcn18_reg: ldo_vcn18 {
+				regulator-name = "ldo_vcn18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vcamaf_reg: ldo_vcamaf {
+				regulator-name = "ldo_vcamaf";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vm_reg: ldo_vm {
+				regulator-name = "ldo_vm";
+				regulator-min-microvolt = <1240000>;
+				regulator-max-microvolt = <1390000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vio18_reg: ldo_vio18 {
+				regulator-name = "ldo_vio18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vcamd_reg: ldo_vcamd {
+				regulator-name = "ldo_vcamd";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vcamio_reg: ldo_vcamio {
+				regulator-name = "ldo_vcamio";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vm25_reg: ldo_vm25 {
+				regulator-name = "ldo_vm25";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vefuse_reg: ldo_vefuse {
+				regulator-name = "ldo_vefuse";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+		};
+	};
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 02/24] regulator: mt6392: Add support for MT6392 regulator
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
  2019-03-23 21:15 ` [PATCH 01/24] dt-bindings: regulator: add support for MT6392 Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-03-23 21:15 ` [PATCH 03/24] dt-bindings: pwrap: mediatek: add pwrap support for MT8516 Fabien Parent
                   ` (21 subsequent siblings)
  23 siblings, 0 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

The MT6392 is a regulator found on boards based on the MediaTek
MT8167, MT8516, and probably other SoCs. It is a so called PMIC and
connectcts as a slave to a SoC using SPI, wrapped inside PWRAP.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/regulator/Kconfig                  |   9 +
 drivers/regulator/Makefile                 |   1 +
 drivers/regulator/mt6392-regulator.c       | 490 +++++++++++++++++++++
 include/linux/regulator/mt6392-regulator.h |  40 ++
 4 files changed, 540 insertions(+)
 create mode 100644 drivers/regulator/mt6392-regulator.c
 create mode 100644 include/linux/regulator/mt6392-regulator.h

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index b7f249ee5e68..c0109005128c 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -624,6 +624,15 @@ config REGULATOR_MT6380
 	  This driver supports the control of different power rails of device
 	  through regulator interface.
 
+config REGULATOR_MT6392
+	tristate "MediaTek MT6392 PMIC"
+	depends on MFD_MT6397
+	help
+	  Say y here to select this option to enable the power regulator of
+	  MediaTek MT6392 PMIC.
+	  This driver supports the control of different power rails of device
+	  through regulator interface.
+
 config REGULATOR_MT6397
 	tristate "MediaTek MT6397 PMIC"
 	depends on MFD_MT6397
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 1169f8a27d91..5b8da206412e 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_REGULATOR_MCP16502) += mcp16502.o
 obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
 obj-$(CONFIG_REGULATOR_MT6323)	+= mt6323-regulator.o
 obj-$(CONFIG_REGULATOR_MT6380)	+= mt6380-regulator.o
+obj-$(CONFIG_REGULATOR_MT6392)	+= mt6392-regulator.o
 obj-$(CONFIG_REGULATOR_MT6397)	+= mt6397-regulator.o
 obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
 obj-$(CONFIG_REGULATOR_QCOM_RPMH) += qcom-rpmh-regulator.o
diff --git a/drivers/regulator/mt6392-regulator.c b/drivers/regulator/mt6392-regulator.c
new file mode 100644
index 000000000000..d3c0e94d4cd0
--- /dev/null
+++ b/drivers/regulator/mt6392-regulator.c
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mfd/mt6397/core.h>
+#include <linux/mfd/mt6392/registers.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/mt6392-regulator.h>
+#include <linux/regulator/of_regulator.h>
+
+#define MT6392_BUCK_MODE_AUTO	0
+#define MT6392_BUCK_MODE_FORCE_PWM	1
+#define MT6392_LDO_MODE_NORMAL	0
+#define MT6392_LDO_MODE_LP	1
+
+/*
+ * MT6392 regulators' information
+ *
+ * @desc: standard fields of regulator description.
+ * @qi: Mask for query enable signal status of regulators
+ * @vselon_reg: Register sections for hardware control mode of bucks
+ * @vselctrl_reg: Register for controlling the buck control mode.
+ * @vselctrl_mask: Mask for query buck's voltage control mode.
+ */
+struct mt6392_regulator_info {
+	struct regulator_desc desc;
+	u32 qi;
+	u32 vselon_reg;
+	u32 vselctrl_reg;
+	u32 vselctrl_mask;
+	u32 modeset_reg;
+	u32 modeset_mask;
+};
+
+#define MT6392_BUCK(match, vreg, min, max, step, volt_ranges, enreg,	\
+		vosel, vosel_mask, voselon, vosel_ctrl,			\
+		_modeset_reg, _modeset_mask)				\
+[MT6392_ID_##vreg] = {							\
+	.desc = {							\
+		.name = #vreg,						\
+		.of_match = of_match_ptr(match),			\
+		.ops = &mt6392_volt_range_ops,				\
+		.type = REGULATOR_VOLTAGE,				\
+		.id = MT6392_ID_##vreg,					\
+		.owner = THIS_MODULE,					\
+		.n_voltages = (max - min)/step + 1,			\
+		.linear_ranges = volt_ranges,				\
+		.n_linear_ranges = ARRAY_SIZE(volt_ranges),		\
+		.vsel_reg = vosel,					\
+		.vsel_mask = vosel_mask,				\
+		.enable_reg = enreg,					\
+		.enable_mask = BIT(0),					\
+	},								\
+	.qi = BIT(13),							\
+	.vselon_reg = voselon,						\
+	.vselctrl_reg = vosel_ctrl,					\
+	.vselctrl_mask = BIT(1),					\
+	.modeset_reg = _modeset_reg,					\
+	.modeset_mask = _modeset_mask,					\
+}
+
+#define MT6392_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel,	\
+		vosel_mask, _modeset_reg, _modeset_mask)		\
+[MT6392_ID_##vreg] = {							\
+	.desc = {							\
+		.name = #vreg,						\
+		.of_match = of_match_ptr(match),			\
+		.ops = &mt6392_volt_table_ops,				\
+		.type = REGULATOR_VOLTAGE,				\
+		.id = MT6392_ID_##vreg,					\
+		.owner = THIS_MODULE,					\
+		.n_voltages = ARRAY_SIZE(ldo_volt_table),		\
+		.volt_table = ldo_volt_table,				\
+		.vsel_reg = vosel,					\
+		.vsel_mask = vosel_mask,				\
+		.enable_reg = enreg,					\
+		.enable_mask = BIT(enbit),				\
+	},								\
+	.qi = BIT(15),							\
+	.modeset_reg = _modeset_reg,					\
+	.modeset_mask = _modeset_mask,					\
+}
+
+#define MT6392_REG_FIXED(match, vreg, enreg, enbit, volt,		\
+		_modeset_reg, _modeset_mask)				\
+[MT6392_ID_##vreg] = {							\
+	.desc = {							\
+		.name = #vreg,						\
+		.of_match = of_match_ptr(match),			\
+		.ops = &mt6392_volt_fixed_ops,				\
+		.type = REGULATOR_VOLTAGE,				\
+		.id = MT6392_ID_##vreg,					\
+		.owner = THIS_MODULE,					\
+		.n_voltages = 1,					\
+		.enable_reg = enreg,					\
+		.enable_mask = BIT(enbit),				\
+		.min_uV = volt,						\
+	},								\
+	.qi = BIT(15),							\
+	.modeset_reg = _modeset_reg,					\
+	.modeset_mask = _modeset_mask,					\
+}
+
+static const struct regulator_linear_range buck_volt_range1[] = {
+	REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
+};
+
+static const struct regulator_linear_range buck_volt_range2[] = {
+	REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500),
+};
+
+static const u32 ldo_volt_table1[] = {
+	1800000, 1900000, 2000000, 2200000,
+};
+
+static const u32 ldo_volt_table2[] = {
+	3300000, 3400000, 3500000, 3600000,
+};
+
+static const u32 ldo_volt_table3[] = {
+	1800000, 3300000,
+};
+
+static const u32 ldo_volt_table4[] = {
+	3000000, 3300000,
+};
+
+static const u32 ldo_volt_table5[] = {
+	1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000,
+};
+
+static const u32 ldo_volt_table6[] = {
+	1240000, 1390000,
+};
+
+static const u32 ldo_volt_table7[] = {
+	1200000, 1300000, 1500000, 1800000,
+};
+
+static const u32 ldo_volt_table8[] = {
+	1800000, 2000000,
+};
+
+static int mt6392_get_status(struct regulator_dev *rdev)
+{
+	int ret;
+	u32 regval;
+	struct mt6392_regulator_info *info = rdev_get_drvdata(rdev);
+
+	ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);
+	if (ret != 0) {
+		dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
+		return ret;
+	}
+
+	return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
+}
+
+static int mt6392_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+	int ret, val = 0;
+	struct mt6392_regulator_info *info = rdev_get_drvdata(rdev);
+	u32 reg_value;
+
+	if (!info->modeset_mask) {
+		dev_err(&rdev->dev, "regulator %s doesn't support set_mode\n",
+			info->desc.name);
+		return -EINVAL;
+	}
+
+	switch (mode) {
+	case REGULATOR_MODE_FAST:
+		val = MT6392_BUCK_MODE_FORCE_PWM;
+		break;
+	case REGULATOR_MODE_NORMAL:
+		val = MT6392_BUCK_MODE_AUTO;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	val <<= ffs(info->modeset_mask) - 1;
+
+	ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
+				  info->modeset_mask, val);
+
+	if (regmap_read(rdev->regmap, info->modeset_reg, &reg_value) < 0) {
+		dev_err(&rdev->dev, "Failed to read register value\n");
+		return -EIO;
+	}
+
+	return ret;
+}
+
+static unsigned int mt6392_buck_get_mode(struct regulator_dev *rdev)
+{
+	unsigned int val;
+	unsigned int mode;
+	int ret;
+	struct mt6392_regulator_info *info = rdev_get_drvdata(rdev);
+
+	if (!info->modeset_mask) {
+		dev_err(&rdev->dev, "regulator %s doesn't support get_mode\n",
+			info->desc.name);
+		return -EINVAL;
+	}
+
+	ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
+	if (ret < 0)
+		return ret;
+
+	val &= info->modeset_mask;
+	val >>= ffs(info->modeset_mask) - 1;
+
+	if (val & 0x1)
+		mode = REGULATOR_MODE_FAST;
+	else
+		mode = REGULATOR_MODE_NORMAL;
+
+	return mode;
+}
+
+static int mt6392_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode)
+{
+	int ret, val = 0;
+	struct mt6392_regulator_info *info = rdev_get_drvdata(rdev);
+
+	if (!info->modeset_mask) {
+		dev_err(&rdev->dev, "regulator %s doesn't support set_mode\n",
+			info->desc.name);
+		return -EINVAL;
+	}
+
+	switch (mode) {
+	case REGULATOR_MODE_STANDBY:
+		val = MT6392_LDO_MODE_LP;
+		break;
+	case REGULATOR_MODE_NORMAL:
+		val = MT6392_LDO_MODE_NORMAL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	val <<= ffs(info->modeset_mask) - 1;
+
+	ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
+				  info->modeset_mask, val);
+
+	return ret;
+}
+
+static unsigned int mt6392_ldo_get_mode(struct regulator_dev *rdev)
+{
+	unsigned int val;
+	unsigned int mode;
+	int ret;
+	struct mt6392_regulator_info *info = rdev_get_drvdata(rdev);
+
+	if (!info->modeset_mask) {
+		dev_err(&rdev->dev, "regulator %s doesn't support get_mode\n",
+			info->desc.name);
+		return -EINVAL;
+	}
+
+	ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
+	if (ret < 0)
+		return ret;
+
+	val &= info->modeset_mask;
+	val >>= ffs(info->modeset_mask) - 1;
+
+	if (val & 0x1)
+		mode = REGULATOR_MODE_STANDBY;
+	else
+		mode = REGULATOR_MODE_NORMAL;
+
+	return mode;
+}
+
+static const struct regulator_ops mt6392_volt_range_ops = {
+	.list_voltage = regulator_list_voltage_linear_range,
+	.map_voltage = regulator_map_voltage_linear_range,
+	.set_voltage_sel = regulator_set_voltage_sel_regmap,
+	.get_voltage_sel = regulator_get_voltage_sel_regmap,
+	.set_voltage_time_sel = regulator_set_voltage_time_sel,
+	.enable = regulator_enable_regmap,
+	.disable = regulator_disable_regmap,
+	.is_enabled = regulator_is_enabled_regmap,
+	.get_status = mt6392_get_status,
+	.set_mode = mt6392_buck_set_mode,
+	.get_mode = mt6392_buck_get_mode,
+};
+
+static const struct regulator_ops mt6392_volt_table_ops = {
+	.list_voltage = regulator_list_voltage_table,
+	.map_voltage = regulator_map_voltage_iterate,
+	.set_voltage_sel = regulator_set_voltage_sel_regmap,
+	.get_voltage_sel = regulator_get_voltage_sel_regmap,
+	.set_voltage_time_sel = regulator_set_voltage_time_sel,
+	.enable = regulator_enable_regmap,
+	.disable = regulator_disable_regmap,
+	.is_enabled = regulator_is_enabled_regmap,
+	.get_status = mt6392_get_status,
+	.set_mode = mt6392_ldo_set_mode,
+	.get_mode = mt6392_ldo_get_mode,
+};
+
+static const struct regulator_ops mt6392_volt_fixed_ops = {
+	.list_voltage = regulator_list_voltage_linear,
+	.enable = regulator_enable_regmap,
+	.disable = regulator_disable_regmap,
+	.is_enabled = regulator_is_enabled_regmap,
+	.get_status = mt6392_get_status,
+	.set_mode = mt6392_ldo_set_mode,
+	.get_mode = mt6392_ldo_get_mode,
+};
+
+/* The array is indexed by id(MT6392_ID_XXX) */
+static struct mt6392_regulator_info mt6392_regulators[] = {
+	MT6392_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250,
+		buck_volt_range1, MT6392_VPROC_CON7, MT6392_VPROC_CON9, 0x7f,
+		MT6392_VPROC_CON10, MT6392_VPROC_CON5, MT6392_VPROC_CON2,
+		0x100),
+	MT6392_BUCK("buck_vsys", VSYS, 1400000, 2987500, 12500,
+		buck_volt_range2, MT6392_VSYS_CON7, MT6392_VSYS_CON9, 0x7f,
+		MT6392_VSYS_CON10, MT6392_VSYS_CON5, MT6392_VSYS_CON2, 0x100),
+	MT6392_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250,
+		buck_volt_range1, MT6392_VCORE_CON7, MT6392_VCORE_CON9, 0x7f,
+		MT6392_VCORE_CON10, MT6392_VCORE_CON5, MT6392_VCORE_CON2,
+		0x100),
+	MT6392_REG_FIXED("ldo_vxo22", VXO22, MT6392_ANALDO_CON1, 10, 2200000,
+		MT6392_ANALDO_CON1, 0x2),
+	MT6392_LDO("ldo_vaud22", VAUD22, ldo_volt_table1,
+		MT6392_ANALDO_CON2, 14, MT6392_ANALDO_CON8, 0x60,
+		MT6392_ANALDO_CON2, 0x2),
+	MT6392_REG_FIXED("ldo_vcama", VCAMA, MT6392_ANALDO_CON4, 15, 2800000,
+		-1, 0),
+	MT6392_REG_FIXED("ldo_vaud28", VAUD28, MT6392_ANALDO_CON23, 14, 2800000,
+		MT6392_ANALDO_CON23, 0x2),
+	MT6392_REG_FIXED("ldo_vadc18", VADC18, MT6392_ANALDO_CON25, 14, 1800000,
+		MT6392_ANALDO_CON25, 0x2),
+	MT6392_LDO("ldo_vcn35", VCN35, ldo_volt_table2,
+		MT6392_ANALDO_CON21, 12, MT6392_ANALDO_CON16, 0xC,
+		MT6392_ANALDO_CON21, 0x2),
+	MT6392_REG_FIXED("ldo_vio28", VIO28, MT6392_DIGLDO_CON0, 14, 2800000,
+		MT6392_DIGLDO_CON0, 0x2),
+	MT6392_REG_FIXED("ldo_vusb", VUSB, MT6392_DIGLDO_CON2, 14, 3300000,
+		MT6392_DIGLDO_CON2, 0x2),
+	MT6392_LDO("ldo_vmc", VMC, ldo_volt_table3,
+		MT6392_DIGLDO_CON3, 12, MT6392_DIGLDO_CON24, 0x10,
+		MT6392_DIGLDO_CON3, 0x2),
+	MT6392_LDO("ldo_vmch", VMCH, ldo_volt_table4,
+		MT6392_DIGLDO_CON5, 14, MT6392_DIGLDO_CON26, 0x80,
+		MT6392_DIGLDO_CON5, 0x2),
+	MT6392_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table4,
+		MT6392_DIGLDO_CON6, 14, MT6392_DIGLDO_CON27, 0x80,
+		MT6392_DIGLDO_CON6, 0x2),
+	MT6392_LDO("ldo_vgp1", VGP1, ldo_volt_table5,
+		MT6392_DIGLDO_CON7, 15, MT6392_DIGLDO_CON28, 0xE0,
+		MT6392_DIGLDO_CON7, 0x2),
+	MT6392_LDO("ldo_vgp2", VGP2, ldo_volt_table5,
+		MT6392_DIGLDO_CON8, 15, MT6392_DIGLDO_CON29, 0xE0,
+		MT6392_DIGLDO_CON8, 0x2),
+	MT6392_REG_FIXED("ldo_vcn18", VCN18, MT6392_DIGLDO_CON11, 14, 1800000,
+		MT6392_DIGLDO_CON11, 0x2),
+	MT6392_LDO("ldo_vcamaf", VCAMAF, ldo_volt_table5,
+		MT6392_DIGLDO_CON31, 15, MT6392_DIGLDO_CON32, 0xE0,
+		MT6392_DIGLDO_CON31, 0x2),
+	MT6392_LDO("ldo_vm", VM, ldo_volt_table6,
+		MT6392_DIGLDO_CON47, 14, MT6392_DIGLDO_CON48, 0x30,
+		MT6392_DIGLDO_CON47, 0x2),
+	MT6392_REG_FIXED("ldo_vio18", VIO18, MT6392_DIGLDO_CON49, 14, 1800000,
+		MT6392_DIGLDO_CON49, 0x2),
+	MT6392_LDO("ldo_vcamd", VCAMD, ldo_volt_table7,
+		MT6392_DIGLDO_CON51, 14, MT6392_DIGLDO_CON52, 0x60,
+		MT6392_DIGLDO_CON51, 0x2),
+	MT6392_REG_FIXED("ldo_vcamio", VCAMIO, MT6392_DIGLDO_CON53, 14, 1800000,
+		MT6392_DIGLDO_CON53, 0x2),
+	MT6392_REG_FIXED("ldo_vm25", VM25, MT6392_DIGLDO_CON55, 14, 2500000,
+		MT6392_DIGLDO_CON55, 0x2),
+	MT6392_LDO("ldo_vefuse", VEFUSE, ldo_volt_table8,
+		MT6392_DIGLDO_CON57, 14, MT6392_DIGLDO_CON58, 0x10,
+		MT6392_DIGLDO_CON57, 0x2),
+};
+
+static int mt6392_set_buck_vosel_reg(struct platform_device *pdev)
+{
+	struct mt6397_chip *mt6392 = dev_get_drvdata(pdev->dev.parent);
+	int i;
+	u32 regval;
+
+	for (i = 0; i < MT6392_MAX_REGULATOR; i++) {
+		if (mt6392_regulators[i].vselctrl_reg) {
+			if (regmap_read(mt6392->regmap,
+				mt6392_regulators[i].vselctrl_reg,
+				&regval) < 0) {
+				dev_err(&pdev->dev,
+					"Failed to read buck ctrl\n");
+				return -EIO;
+			}
+
+			if (regval & mt6392_regulators[i].vselctrl_mask) {
+				mt6392_regulators[i].desc.vsel_reg =
+				mt6392_regulators[i].vselon_reg;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int mt6392_regulator_probe(struct platform_device *pdev)
+{
+	struct mt6397_chip *mt6392 = dev_get_drvdata(pdev->dev.parent);
+	struct regulator_config config = {};
+	struct regulator_dev *rdev;
+	struct regulation_constraints *c;
+	int i;
+	u32 reg_value;
+
+	/* Query buck controller to select activated voltage register part */
+	if (mt6392_set_buck_vosel_reg(pdev))
+		return -EIO;
+
+	/* Read PMIC chip revision to update constraints and voltage table */
+	if (regmap_read(mt6392->regmap, MT6392_CID, &reg_value) < 0) {
+		dev_err(&pdev->dev, "Failed to read Chip ID\n");
+		return -EIO;
+	}
+
+	dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
+
+	for (i = 0; i < MT6392_MAX_REGULATOR; i++) {
+		config.dev = &pdev->dev;
+		config.driver_data = &mt6392_regulators[i];
+		config.regmap = mt6392->regmap;
+		rdev = devm_regulator_register(&pdev->dev,
+				&mt6392_regulators[i].desc, &config);
+		if (IS_ERR(rdev)) {
+			dev_err(&pdev->dev, "failed to register %s\n",
+				mt6392_regulators[i].desc.name);
+			return PTR_ERR(rdev);
+		}
+
+		/* Constrain board-specific capabilities according to what
+		 * this driver and the chip itself can actually do.
+		 */
+		c = rdev->constraints;
+		c->valid_modes_mask |= REGULATOR_MODE_NORMAL|
+			REGULATOR_MODE_STANDBY | REGULATOR_MODE_FAST;
+		c->valid_ops_mask |= REGULATOR_CHANGE_MODE;
+
+	}
+	return 0;
+}
+
+static const struct platform_device_id mt6392_platform_ids[] = {
+	{"mt6392-regulator", 0},
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(platform, mt6392_platform_ids);
+
+static const struct of_device_id mt6392_of_match[] = {
+	{ .compatible = "mediatek,mt6392-regulator", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mt6392_of_match);
+
+static struct platform_driver mt6392_regulator_driver = {
+	.driver = {
+		.name = "mt6392-regulator",
+		.of_match_table = of_match_ptr(mt6392_of_match),
+	},
+	.probe = mt6392_regulator_probe,
+	.id_table = mt6392_platform_ids,
+};
+
+module_platform_driver(mt6392_regulator_driver);
+
+MODULE_AUTHOR("Chen Zhong <chen.zhong@mediatek.com>");
+MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6392 PMIC");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/regulator/mt6392-regulator.h b/include/linux/regulator/mt6392-regulator.h
new file mode 100644
index 000000000000..dfcbcacb5ad4
--- /dev/null
+++ b/include/linux/regulator/mt6392-regulator.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#ifndef __LINUX_REGULATOR_MT6392_H
+#define __LINUX_REGULATOR_MT6392_H
+
+enum {
+	MT6392_ID_VPROC = 0,
+	MT6392_ID_VSYS,
+	MT6392_ID_VCORE,
+	MT6392_ID_VXO22,
+	MT6392_ID_VAUD22,
+	MT6392_ID_VCAMA,
+	MT6392_ID_VAUD28,
+	MT6392_ID_VADC18,
+	MT6392_ID_VCN35,
+	MT6392_ID_VIO28,
+	MT6392_ID_VUSB = 10,
+	MT6392_ID_VMC,
+	MT6392_ID_VMCH,
+	MT6392_ID_VEMC3V3,
+	MT6392_ID_VGP1,
+	MT6392_ID_VGP2,
+	MT6392_ID_VCN18,
+	MT6392_ID_VCAMAF,
+	MT6392_ID_VM,
+	MT6392_ID_VIO18,
+	MT6392_ID_VCAMD,
+	MT6392_ID_VCAMIO,
+	MT6392_ID_VM25,
+	MT6392_ID_VEFUSE,
+	MT6392_ID_RG_MAX,
+};
+
+#define MT6392_MAX_REGULATOR	MT6392_ID_RG_MAX
+
+#endif /* __LINUX_REGULATOR_MT6392_H */
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 03/24] dt-bindings: pwrap: mediatek: add pwrap support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
  2019-03-23 21:15 ` [PATCH 01/24] dt-bindings: regulator: add support for MT6392 Fabien Parent
  2019-03-23 21:15 ` [PATCH 02/24] regulator: mt6392: Add support for MT6392 regulator Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-03-28 19:09   ` Rob Herring
  2019-04-12 17:44   ` Matthias Brugger
  2019-03-23 21:15 ` [PATCH 04/24] soc: mediatek: pwrap: add missing check on rstc Fabien Parent
                   ` (20 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of pwrap for MT8516 SoCs.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
index 5a2ef1726e2a..7a32404c6114 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
@@ -25,6 +25,7 @@ Required properties in pwrap device node.
 	"mediatek,mt8135-pwrap" for MT8135 SoCs
 	"mediatek,mt8173-pwrap" for MT8173 SoCs
 	"mediatek,mt8183-pwrap" for MT8183 SoCs
+	"mediatek,mt8516-pwrap" for MT8516 SoCs
 - interrupts: IRQ for pwrap in SOC
 - reg-names: Must include the following entries:
   "pwrap": Main registers base
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 04/24] soc: mediatek: pwrap: add missing check on rstc
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (2 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 03/24] dt-bindings: pwrap: mediatek: add pwrap support for MT8516 Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-04-12 17:44   ` Matthias Brugger
  2019-03-23 21:15 ` [PATCH 05/24] soc: mediatek: pwrap: add support for MT8516 pwrap Fabien Parent
                   ` (19 subsequent siblings)
  23 siblings, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

The variable rstc is set only when the SoC PWRAP have the
PWRAP_CAP_RESET capability. Check whether rstc is set before
using it to avoid errors.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/soc/mediatek/mtk-pmic-wrap.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 8236a6c87e19..b3ba2301f569 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -1478,7 +1478,8 @@ static int pwrap_init(struct pmic_wrapper *wrp)
 {
 	int ret;
 
-	reset_control_reset(wrp->rstc);
+	if (wrp->rstc)
+		reset_control_reset(wrp->rstc);
 	if (wrp->rstc_bridge)
 		reset_control_reset(wrp->rstc_bridge);
 
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 05/24] soc: mediatek: pwrap: add support for MT8516 pwrap
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (3 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 04/24] soc: mediatek: pwrap: add missing check on rstc Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-04-12 17:44   ` Matthias Brugger
  2019-03-23 21:15 ` [PATCH 06/24] mfd: mt6397: Add support for MT6397 pmic Fabien Parent
                   ` (18 subsequent siblings)
  23 siblings, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add the code to support the pwrap IP on the MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/soc/mediatek/mtk-pmic-wrap.c | 106 +++++++++++++++++++++++++++
 1 file changed, 106 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index b3ba2301f569..73f0be0567bd 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -381,6 +381,10 @@ enum pwrap_regs {
 	PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
 	PWRAP_GPSINF_0_STA,
 	PWRAP_GPSINF_1_STA,
+
+	/* MT8516 only regs */
+	PWRAP_OP_TYPE,
+	PWRAP_MSB_FIRST,
 };
 
 static int mt2701_regs[] = {
@@ -852,6 +856,91 @@ static int mt8183_regs[] = {
 	[PWRAP_WACS2_VLDCLR] =			0xC28,
 };
 
+static int mt8516_regs[] = {
+	[PWRAP_MUX_SEL] =		0x0,
+	[PWRAP_WRAP_EN] =		0x4,
+	[PWRAP_DIO_EN] =		0x8,
+	[PWRAP_SIDLY] =			0xc,
+	[PWRAP_RDDMY] =			0x10,
+	[PWRAP_SI_CK_CON] =		0x14,
+	[PWRAP_CSHEXT_WRITE] =		0x18,
+	[PWRAP_CSHEXT_READ] =		0x1c,
+	[PWRAP_CSLEXT_START] =		0x20,
+	[PWRAP_CSLEXT_END] =		0x24,
+	[PWRAP_STAUPD_PRD] =		0x28,
+	[PWRAP_STAUPD_GRPEN] =		0x2c,
+	[PWRAP_STAUPD_MAN_TRIG] =	0x40,
+	[PWRAP_STAUPD_STA] =		0x44,
+	[PWRAP_WRAP_STA] =		0x48,
+	[PWRAP_HARB_INIT] =		0x4c,
+	[PWRAP_HARB_HPRIO] =		0x50,
+	[PWRAP_HIPRIO_ARB_EN] =		0x54,
+	[PWRAP_HARB_STA0] =		0x58,
+	[PWRAP_HARB_STA1] =		0x5c,
+	[PWRAP_MAN_EN] =		0x60,
+	[PWRAP_MAN_CMD] =		0x64,
+	[PWRAP_MAN_RDATA] =		0x68,
+	[PWRAP_MAN_VLDCLR] =		0x6c,
+	[PWRAP_WACS0_EN] =		0x70,
+	[PWRAP_INIT_DONE0] =		0x74,
+	[PWRAP_WACS0_CMD] =		0x78,
+	[PWRAP_WACS0_RDATA] =		0x7c,
+	[PWRAP_WACS0_VLDCLR] =		0x80,
+	[PWRAP_WACS1_EN] =		0x84,
+	[PWRAP_INIT_DONE1] =		0x88,
+	[PWRAP_WACS1_CMD] =		0x8c,
+	[PWRAP_WACS1_RDATA] =		0x90,
+	[PWRAP_WACS1_VLDCLR] =		0x94,
+	[PWRAP_WACS2_EN] =		0x98,
+	[PWRAP_INIT_DONE2] =		0x9c,
+	[PWRAP_WACS2_CMD] =		0xa0,
+	[PWRAP_WACS2_RDATA] =		0xa4,
+	[PWRAP_WACS2_VLDCLR] =		0xa8,
+	[PWRAP_INT_EN] =		0xac,
+	[PWRAP_INT_FLG_RAW] =		0xb0,
+	[PWRAP_INT_FLG] =		0xb4,
+	[PWRAP_INT_CLR] =		0xb8,
+	[PWRAP_SIG_ADR] =		0xbc,
+	[PWRAP_SIG_MODE] =		0xc0,
+	[PWRAP_SIG_VALUE] =		0xc4,
+	[PWRAP_SIG_ERRVAL] =		0xc8,
+	[PWRAP_CRC_EN] =		0xcc,
+	[PWRAP_TIMER_EN] =		0xd0,
+	[PWRAP_TIMER_STA] =		0xd4,
+	[PWRAP_WDT_UNIT] =		0xd8,
+	[PWRAP_WDT_SRC_EN] =		0xdc,
+	[PWRAP_WDT_FLG] =		0xe0,
+	[PWRAP_DEBUG_INT_SEL] =		0xe4,
+	[PWRAP_DVFS_ADR0] =		0xe8,
+	[PWRAP_DVFS_WDATA0] =		0xec,
+	[PWRAP_DVFS_ADR1] =		0xf0,
+	[PWRAP_DVFS_WDATA1] =		0xf4,
+	[PWRAP_DVFS_ADR2] =		0xf8,
+	[PWRAP_DVFS_WDATA2] =		0xfc,
+	[PWRAP_DVFS_ADR3] =		0x100,
+	[PWRAP_DVFS_WDATA3] =		0x104,
+	[PWRAP_DVFS_ADR4] =		0x108,
+	[PWRAP_DVFS_WDATA4] =		0x10c,
+	[PWRAP_DVFS_ADR5] =		0x110,
+	[PWRAP_DVFS_WDATA5] =		0x114,
+	[PWRAP_DVFS_ADR6] =		0x118,
+	[PWRAP_DVFS_WDATA6] =		0x11c,
+	[PWRAP_DVFS_ADR7] =		0x120,
+	[PWRAP_DVFS_WDATA7] =		0x124,
+	[PWRAP_SPMINF_STA] =		0x128,
+	[PWRAP_CIPHER_KEY_SEL] =	0x12c,
+	[PWRAP_CIPHER_IV_SEL] =		0x130,
+	[PWRAP_CIPHER_EN] =		0x134,
+	[PWRAP_CIPHER_RDY] =		0x138,
+	[PWRAP_CIPHER_MODE] =		0x13c,
+	[PWRAP_CIPHER_SWRST] =		0x140,
+	[PWRAP_DCM_EN] =		0x144,
+	[PWRAP_DCM_DBC_PRD] =		0x148,
+	[PWRAP_SW_RST] =		0x168,
+	[PWRAP_OP_TYPE] =		0x16c,
+	[PWRAP_MSB_FIRST] =		0x170,
+};
+
 enum pmic_type {
 	PMIC_MT6323,
 	PMIC_MT6351,
@@ -869,6 +958,7 @@ enum pwrap_type {
 	PWRAP_MT8135,
 	PWRAP_MT8173,
 	PWRAP_MT8183,
+	PWRAP_MT8516,
 };
 
 struct pmic_wrapper;
@@ -1297,6 +1387,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
 	case PWRAP_MT6765:
 	case PWRAP_MT6797:
 	case PWRAP_MT8173:
+	case PWRAP_MT8516:
 		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
 		break;
 	case PWRAP_MT7622:
@@ -1765,6 +1856,18 @@ static const struct pmic_wrapper_type pwrap_mt8183 = {
 	.init_soc_specific = pwrap_mt8183_init_soc_specific,
 };
 
+static struct pmic_wrapper_type pwrap_mt8516 = {
+	.regs = mt8516_regs,
+	.type = PWRAP_MT8516,
+	.arb_en_all = 0xff,
+	.int_en_all = ~(u32)(BIT(31) | BIT(2)),
+	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
+	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
+	.caps = PWRAP_CAP_DCM,
+	.init_reg_clock = pwrap_mt2701_init_reg_clock,
+	.init_soc_specific = NULL,
+};
+
 static const struct of_device_id of_pwrap_match_tbl[] = {
 	{
 		.compatible = "mediatek,mt2701-pwrap",
@@ -1787,6 +1890,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
 	}, {
 		.compatible = "mediatek,mt8183-pwrap",
 		.data = &pwrap_mt8183,
+	}, {
+		.compatible = "mediatek,mt8516-pwrap",
+		.data = &pwrap_mt8516,
 	}, {
 		/* sentinel */
 	}
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 06/24] mfd: mt6397: Add support for MT6397 pmic
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (4 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 05/24] soc: mediatek: pwrap: add support for MT8516 pwrap Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-03-23 21:15 ` [PATCH 07/24] arm64: dts: mt6392: Add PMIC mt6392 dtsi Fabien Parent
                   ` (17 subsequent siblings)
  23 siblings, 0 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Update the MT6397 MFD driver to support the MT6392 PMIC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/mfd/mt6397-core.c            |  96 ++++++
 include/linux/mfd/mt6392/core.h      |  42 +++
 include/linux/mfd/mt6392/registers.h | 487 +++++++++++++++++++++++++++
 3 files changed, 625 insertions(+)
 create mode 100644 include/linux/mfd/mt6392/core.h
 create mode 100644 include/linux/mfd/mt6392/registers.h

diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index ab24e176ef44..f5e74f4afcc4 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -18,17 +18,38 @@
 #include <linux/of_irq.h>
 #include <linux/regmap.h>
 #include <linux/mfd/core.h>
+#include <linux/mfd/mt6392/core.h>
 #include <linux/mfd/mt6397/core.h>
 #include <linux/mfd/mt6323/core.h>
+#include <linux/mfd/mt6392/registers.h>
 #include <linux/mfd/mt6397/registers.h>
 #include <linux/mfd/mt6323/registers.h>
 
+#define MT6392_RTC_BASE		0x8000
+#define MT6392_RTC_SIZE		0x3e
 #define MT6397_RTC_BASE		0xe000
 #define MT6397_RTC_SIZE		0x3e
 
+#define MT6392_TYPEC_BASE	0x800
+#define MT6392_TYPEC_SIZE	0x100
+
 #define MT6323_CID_CODE		0x23
 #define MT6391_CID_CODE		0x91
 #define MT6397_CID_CODE		0x97
+#define MT6392_CID_CODE		0x92
+
+static const struct resource mt6392_rtc_resources[] = {
+	{
+		.start = MT6392_RTC_BASE,
+		.end   = MT6392_RTC_BASE + MT6392_RTC_SIZE,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = MT6392_IRQ_STATUS_RTC,
+		.end   = MT6392_IRQ_STATUS_RTC,
+		.flags = IORESOURCE_IRQ,
+	},
+};
 
 static const struct resource mt6397_rtc_resources[] = {
 	{
@@ -43,6 +64,14 @@ static const struct resource mt6397_rtc_resources[] = {
 	},
 };
 
+static const struct resource mt6392_keys_resources[] = {
+	{
+		.start = MT6392_IRQ_STATUS_PWRKEY,
+		.end   = MT6392_IRQ_STATUS_RELEASE_FCHRKEY,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
 static const struct resource mt6323_keys_resources[] = {
 	DEFINE_RES_IRQ(MT6323_IRQ_STATUS_PWRKEY),
 	DEFINE_RES_IRQ(MT6323_IRQ_STATUS_FCHRKEY),
@@ -53,6 +82,58 @@ static const struct resource mt6397_keys_resources[] = {
 	DEFINE_RES_IRQ(MT6397_IRQ_HOMEKEY),
 };
 
+static const struct resource mt6392_typec_resources[] = {
+	{
+		.start = MT6392_TYPEC_BASE,
+		.end   = MT6392_TYPEC_BASE + MT6392_TYPEC_SIZE,
+		.flags = IORESOURCE_MEM,
+	},
+	{
+		.start = MT6392_IRQ_STATUS_TYPE_C_CC,
+		.end   = MT6392_IRQ_STATUS_TYPE_C_CC,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static const struct mfd_cell mt6392_devs[] = {
+	{
+		.name = "mt6392-pmic",
+		.of_compatible = "mediatek,mt6392-pmic",
+	}, {
+		.name = "mt6392-regulator",
+		.of_compatible = "mediatek,mt6392-regulator",
+	}, {
+		.name = "mt6392-pinctrl",
+		.of_compatible = "mediatek,mt6392-pinctrl",
+	}, {
+		.name = "mt6397-rtc",
+		.num_resources = ARRAY_SIZE(mt6392_rtc_resources),
+		.resources = mt6392_rtc_resources,
+		.of_compatible = "mediatek,mt6392-rtc",
+	}, {
+		.name = "mt6397-misc",
+		.num_resources = ARRAY_SIZE(mt6392_rtc_resources),
+		.resources = mt6392_rtc_resources,
+		.of_compatible = "mediatek,mt6392-misc",
+	}, {
+		.name = "mt6392-adc",
+		.of_compatible = "mediatek,mt6392-adc"
+	}, {
+		.name = "mtk-pmic-keys",
+		.num_resources = ARRAY_SIZE(mt6392_keys_resources),
+		.resources = mt6392_keys_resources,
+		.of_compatible = "mediatek,mt6392-keys"
+	}, {
+		.name = "mt6392-thermal",
+		.of_compatible = "mediatek,mt6392-thermal"
+	}, {
+		.name = "mt6392-typec",
+		.num_resources = ARRAY_SIZE(mt6392_typec_resources),
+		.resources = mt6392_typec_resources,
+		.of_compatible = "mediatek,mt6392-typec",
+	},
+};
+
 static const struct mfd_cell mt6323_devs[] = {
 	{
 		.name = "mt6323-regulator",
@@ -327,6 +408,20 @@ static int mt6397_probe(struct platform_device *pdev)
 					   0, pmic->irq_domain);
 		break;
 
+	case MT6392_CID_CODE:
+		pmic->int_con[0] = MT6392_INT_CON0;
+		pmic->int_con[1] = MT6392_INT_CON1;
+		pmic->int_status[0] = MT6392_INT_STATUS0;
+		pmic->int_status[1] = MT6392_INT_STATUS1;
+		ret = mt6397_irq_init(pmic);
+		if (ret)
+			return ret;
+
+		ret = devm_mfd_add_devices(&pdev->dev, -1, mt6392_devs,
+					   ARRAY_SIZE(mt6392_devs), NULL,
+					   0, NULL);
+		break;
+
 	default:
 		dev_err(&pdev->dev, "unsupported chip: %d\n", id);
 		return -ENODEV;
@@ -343,6 +438,7 @@ static int mt6397_probe(struct platform_device *pdev)
 static const struct of_device_id mt6397_of_match[] = {
 	{ .compatible = "mediatek,mt6397" },
 	{ .compatible = "mediatek,mt6323" },
+	{ .compatible = "mediatek,mt6392" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mt6397_of_match);
diff --git a/include/linux/mfd/mt6392/core.h b/include/linux/mfd/mt6392/core.h
new file mode 100644
index 000000000000..9a99f91d845a
--- /dev/null
+++ b/include/linux/mfd/mt6392/core.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#ifndef __MFD_MT6392_CORE_H__
+#define __MFD_MT6392_CORE_H__
+
+enum MT6392_IRQ_STATUS_numbers {
+	MT6392_IRQ_STATUS_SPKL_AB = 0,
+	MT6392_IRQ_STATUS_SPKL,
+	MT6392_IRQ_STATUS_BAT_L,
+	MT6392_IRQ_STATUS_BAT_H,
+	MT6392_IRQ_STATUS_WATCHDOG,
+	MT6392_IRQ_STATUS_PWRKEY,
+	MT6392_IRQ_STATUS_THR_L,
+	MT6392_IRQ_STATUS_THR_H,
+	MT6392_IRQ_STATUS_VBATON_UNDET,
+	MT6392_IRQ_STATUS_BVALID_DET,
+	MT6392_IRQ_STATUS_CHRDET,
+	MT6392_IRQ_STATUS_OV,
+	MT6392_IRQ_STATUS_LDO = 16,
+	MT6392_IRQ_STATUS_FCHRKEY,
+	MT6392_IRQ_STATUS_RELEASE_PWRKEY,
+	MT6392_IRQ_STATUS_RELEASE_FCHRKEY,
+	MT6392_IRQ_STATUS_RTC,
+	MT6392_IRQ_STATUS_VPROC,
+	MT6392_IRQ_STATUS_VSYS,
+	MT6392_IRQ_STATUS_VCORE,
+	MT6392_IRQ_STATUS_TYPE_C_CC,
+	MT6392_IRQ_STATUS_TYPEC_H_MAX,
+	MT6392_IRQ_STATUS_TYPEC_H_MIN,
+	MT6392_IRQ_STATUS_TYPEC_L_MAX,
+	MT6392_IRQ_STATUS_TYPEC_L_MIN,
+	MT6392_IRQ_STATUS_THR_MAX,
+	MT6392_IRQ_STATUS_THR_MIN,
+	MT6392_IRQ_STATUS_NAG_C_DLTV,
+	MT6392_IRQ_STATUS_NR,
+};
+
+#endif /* __MFD_MT6392_CORE_H__ */
diff --git a/include/linux/mfd/mt6392/registers.h b/include/linux/mfd/mt6392/registers.h
new file mode 100644
index 000000000000..f02b478fc418
--- /dev/null
+++ b/include/linux/mfd/mt6392/registers.h
@@ -0,0 +1,487 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Chen Zhong <chen.zhong@mediatek.com>
+ */
+
+#ifndef __MFD_MT6392_REGISTERS_H__
+#define __MFD_MT6392_REGISTERS_H__
+
+/* PMIC Registers */
+#define MT6392_CHR_CON0                         0x0000
+#define MT6392_CHR_CON1                         0x0002
+#define MT6392_CHR_CON2                         0x0004
+#define MT6392_CHR_CON3                         0x0006
+#define MT6392_CHR_CON4                         0x0008
+#define MT6392_CHR_CON5                         0x000A
+#define MT6392_CHR_CON6                         0x000C
+#define MT6392_CHR_CON7                         0x000E
+#define MT6392_CHR_CON8                         0x0010
+#define MT6392_CHR_CON9                         0x0012
+#define MT6392_CHR_CON10                        0x0014
+#define MT6392_CHR_CON11                        0x0016
+#define MT6392_CHR_CON12                        0x0018
+#define MT6392_CHR_CON13                        0x001A
+#define MT6392_CHR_CON14                        0x001C
+#define MT6392_CHR_CON15                        0x001E
+#define MT6392_CHR_CON16                        0x0020
+#define MT6392_CHR_CON17                        0x0022
+#define MT6392_CHR_CON18                        0x0024
+#define MT6392_CHR_CON19                        0x0026
+#define MT6392_CHR_CON20                        0x0028
+#define MT6392_CHR_CON21                        0x002A
+#define MT6392_CHR_CON22                        0x002C
+#define MT6392_CHR_CON23                        0x002E
+#define MT6392_CHR_CON24                        0x0030
+#define MT6392_CHR_CON25                        0x0032
+#define MT6392_CHR_CON26                        0x0034
+#define MT6392_CHR_CON27                        0x0036
+#define MT6392_CHR_CON28                        0x0038
+#define MT6392_CHR_CON29                        0x003A
+#define MT6392_STRUP_CON0                       0x003C
+#define MT6392_STRUP_CON2                       0x003E
+#define MT6392_STRUP_CON3                       0x0040
+#define MT6392_STRUP_CON4                       0x0042
+#define MT6392_STRUP_CON5                       0x0044
+#define MT6392_STRUP_CON6                       0x0046
+#define MT6392_STRUP_CON7                       0x0048
+#define MT6392_STRUP_CON8                       0x004A
+#define MT6392_STRUP_CON9                       0x004C
+#define MT6392_STRUP_CON10                      0x004E
+#define MT6392_STRUP_CON11                      0x0050
+#define MT6392_SPK_CON0                         0x0052
+#define MT6392_SPK_CON1                         0x0054
+#define MT6392_SPK_CON2                         0x0056
+#define MT6392_SPK_CON6                         0x005E
+#define MT6392_SPK_CON7                         0x0060
+#define MT6392_SPK_CON8                         0x0062
+#define MT6392_SPK_CON9                         0x0064
+#define MT6392_SPK_CON10                        0x0066
+#define MT6392_SPK_CON11                        0x0068
+#define MT6392_SPK_CON12                        0x006A
+#define MT6392_STRUP_CON12                      0x006E
+#define MT6392_STRUP_CON13                      0x0070
+#define MT6392_STRUP_CON14                      0x0072
+#define MT6392_STRUP_CON15                      0x0074
+#define MT6392_STRUP_CON16                      0x0076
+#define MT6392_STRUP_CON17                      0x0078
+#define MT6392_STRUP_CON18                      0x007A
+#define MT6392_STRUP_CON19                      0x007C
+#define MT6392_STRUP_CON20                      0x007E
+#define MT6392_CID                              0x0100
+#define MT6392_TOP_CKPDN0                       0x0102
+#define MT6392_TOP_CKPDN0_SET                   0x0104
+#define MT6392_TOP_CKPDN0_CLR                   0x0106
+#define MT6392_TOP_CKPDN1                       0x0108
+#define MT6392_TOP_CKPDN1_SET                   0x010A
+#define MT6392_TOP_CKPDN1_CLR                   0x010C
+#define MT6392_TOP_CKPDN2                       0x010E
+#define MT6392_TOP_CKPDN2_SET                   0x0110
+#define MT6392_TOP_CKPDN2_CLR                   0x0112
+#define MT6392_TOP_RST_CON                      0x0114
+#define MT6392_TOP_RST_CON_SET                  0x0116
+#define MT6392_TOP_RST_CON_CLR                  0x0118
+#define MT6392_TOP_RST_MISC                     0x011A
+#define MT6392_TOP_RST_MISC_SET                 0x011C
+#define MT6392_TOP_RST_MISC_CLR                 0x011E
+#define MT6392_TOP_CKCON0                       0x0120
+#define MT6392_TOP_CKCON0_SET                   0x0122
+#define MT6392_TOP_CKCON0_CLR                   0x0124
+#define MT6392_TOP_CKCON1                       0x0126
+#define MT6392_TOP_CKCON1_SET                   0x0128
+#define MT6392_TOP_CKCON1_CLR                   0x012A
+#define MT6392_TOP_CKTST0                       0x012C
+#define MT6392_TOP_CKTST1                       0x012E
+#define MT6392_TOP_CKTST2                       0x0130
+#define MT6392_TEST_OUT                         0x0132
+#define MT6392_TEST_CON0                        0x0134
+#define MT6392_TEST_CON1                        0x0136
+#define MT6392_EN_STATUS0                       0x0138
+#define MT6392_EN_STATUS1                       0x013A
+#define MT6392_OCSTATUS0                        0x013C
+#define MT6392_OCSTATUS1                        0x013E
+#define MT6392_PGSTATUS                         0x0140
+#define MT6392_CHRSTATUS                        0x0142
+#define MT6392_TDSEL_CON                        0x0144
+#define MT6392_RDSEL_CON                        0x0146
+#define MT6392_SMT_CON0                         0x0148
+#define MT6392_SMT_CON1                         0x014A
+#define MT6392_DRV_CON0                         0x0152
+#define MT6392_DRV_CON1                         0x0154
+#define MT6392_INT_CON0                         0x0160
+#define MT6392_INT_CON0_SET                     0x0162
+#define MT6392_INT_CON0_CLR                     0x0164
+#define MT6392_INT_CON1                         0x0166
+#define MT6392_INT_CON1_SET                     0x0168
+#define MT6392_INT_CON1_CLR                     0x016A
+#define MT6392_INT_MISC_CON                     0x016C
+#define MT6392_INT_MISC_CON_SET                 0x016E
+#define MT6392_INT_MISC_CON_CLR                 0x0170
+#define MT6392_INT_STATUS0                      0x0172
+#define MT6392_INT_STATUS1                      0x0174
+#define MT6392_OC_GEAR_0                        0x0176
+#define MT6392_OC_GEAR_1                        0x0178
+#define MT6392_OC_GEAR_2                        0x017A
+#define MT6392_OC_CTL_VPROC                     0x017C
+#define MT6392_OC_CTL_VSYS                      0x017E
+#define MT6392_OC_CTL_VCORE                     0x0180
+#define MT6392_FQMTR_CON0                       0x0182
+#define MT6392_FQMTR_CON1                       0x0184
+#define MT6392_FQMTR_CON2                       0x0186
+#define MT6392_RG_SPI_CON                       0x0188
+#define MT6392_DEW_DIO_EN                       0x018A
+#define MT6392_DEW_READ_TEST                    0x018C
+#define MT6392_DEW_WRITE_TEST                   0x018E
+#define MT6392_DEW_CRC_SWRST                    0x0190
+#define MT6392_DEW_CRC_EN                       0x0192
+#define MT6392_DEW_CRC_VAL                      0x0194
+#define MT6392_DEW_DBG_MON_SEL                  0x0196
+#define MT6392_DEW_CIPHER_KEY_SEL               0x0198
+#define MT6392_DEW_CIPHER_IV_SEL                0x019A
+#define MT6392_DEW_CIPHER_EN                    0x019C
+#define MT6392_DEW_CIPHER_RDY                   0x019E
+#define MT6392_DEW_CIPHER_MODE                  0x01A0
+#define MT6392_DEW_CIPHER_SWRST                 0x01A2
+#define MT6392_DEW_RDDMY_NO                     0x01A4
+#define MT6392_DEW_RDATA_DLY_SEL                0x01A6
+#define MT6392_CLK_TRIM_CON0                    0x01A8
+#define MT6392_BUCK_CON0                        0x0200
+#define MT6392_BUCK_CON1                        0x0202
+#define MT6392_BUCK_CON2                        0x0204
+#define MT6392_BUCK_CON3                        0x0206
+#define MT6392_BUCK_CON4                        0x0208
+#define MT6392_BUCK_CON5                        0x020A
+#define MT6392_VPROC_CON0                       0x020C
+#define MT6392_VPROC_CON1                       0x020E
+#define MT6392_VPROC_CON2                       0x0210
+#define MT6392_VPROC_CON3                       0x0212
+#define MT6392_VPROC_CON4                       0x0214
+#define MT6392_VPROC_CON5                       0x0216
+#define MT6392_VPROC_CON7                       0x021A
+#define MT6392_VPROC_CON8                       0x021C
+#define MT6392_VPROC_CON9                       0x021E
+#define MT6392_VPROC_CON10                      0x0220
+#define MT6392_VPROC_CON11                      0x0222
+#define MT6392_VPROC_CON12                      0x0224
+#define MT6392_VPROC_CON13                      0x0226
+#define MT6392_VPROC_CON14                      0x0228
+#define MT6392_VPROC_CON15                      0x022A
+#define MT6392_VPROC_CON18                      0x0230
+#define MT6392_VSYS_CON0                        0x0232
+#define MT6392_VSYS_CON1                        0x0234
+#define MT6392_VSYS_CON2                        0x0236
+#define MT6392_VSYS_CON3                        0x0238
+#define MT6392_VSYS_CON4                        0x023A
+#define MT6392_VSYS_CON5                        0x023C
+#define MT6392_VSYS_CON7                        0x0240
+#define MT6392_VSYS_CON8                        0x0242
+#define MT6392_VSYS_CON9                        0x0244
+#define MT6392_VSYS_CON10                       0x0246
+#define MT6392_VSYS_CON11                       0x0248
+#define MT6392_VSYS_CON12                       0x024A
+#define MT6392_VSYS_CON13                       0x024C
+#define MT6392_VSYS_CON14                       0x024E
+#define MT6392_VSYS_CON15                       0x0250
+#define MT6392_VSYS_CON18                       0x0256
+#define MT6392_BUCK_OC_CON0                     0x0258
+#define MT6392_BUCK_OC_CON1                     0x025A
+#define MT6392_BUCK_OC_CON2                     0x025C
+#define MT6392_BUCK_OC_CON3                     0x025E
+#define MT6392_BUCK_OC_CON4                     0x0260
+#define MT6392_BUCK_OC_VPROC_CON0               0x0262
+#define MT6392_BUCK_OC_VCORE_CON0               0x0264
+#define MT6392_BUCK_OC_VSYS_CON0                0x0266
+#define MT6392_BUCK_ANA_MON_CON0                0x0268
+#define MT6392_BUCK_EFUSE_OC_CON0               0x026A
+#define MT6392_VCORE_CON0                       0x0300
+#define MT6392_VCORE_CON1                       0x0302
+#define MT6392_VCORE_CON2                       0x0304
+#define MT6392_VCORE_CON3                       0x0306
+#define MT6392_VCORE_CON4                       0x0308
+#define MT6392_VCORE_CON5                       0x030A
+#define MT6392_VCORE_CON7                       0x030E
+#define MT6392_VCORE_CON8                       0x0310
+#define MT6392_VCORE_CON9                       0x0312
+#define MT6392_VCORE_CON10                      0x0314
+#define MT6392_VCORE_CON11                      0x0316
+#define MT6392_VCORE_CON12                      0x0318
+#define MT6392_VCORE_CON13                      0x031A
+#define MT6392_VCORE_CON14                      0x031C
+#define MT6392_VCORE_CON15                      0x031E
+#define MT6392_VCORE_CON18                      0x0324
+#define MT6392_BUCK_K_CON0                      0x032A
+#define MT6392_BUCK_K_CON1                      0x032C
+#define MT6392_BUCK_K_CON2                      0x032E
+#define MT6392_ANALDO_CON0                      0x0400
+#define MT6392_ANALDO_CON1                      0x0402
+#define MT6392_ANALDO_CON2                      0x0404
+#define MT6392_ANALDO_CON3                      0x0406
+#define MT6392_ANALDO_CON4                      0x0408
+#define MT6392_ANALDO_CON6                      0x040C
+#define MT6392_ANALDO_CON7                      0x040E
+#define MT6392_ANALDO_CON8                      0x0410
+#define MT6392_ANALDO_CON10                     0x0412
+#define MT6392_ANALDO_CON15                     0x0414
+#define MT6392_ANALDO_CON16                     0x0416
+#define MT6392_ANALDO_CON17                     0x0418
+#define MT6392_ANALDO_CON21                     0x0420
+#define MT6392_ANALDO_CON22                     0x0422
+#define MT6392_ANALDO_CON23                     0x0424
+#define MT6392_ANALDO_CON24                     0x0426
+#define MT6392_ANALDO_CON25                     0x0428
+#define MT6392_ANALDO_CON26                     0x042A
+#define MT6392_ANALDO_CON27                     0x042C
+#define MT6392_ANALDO_CON28                     0x042E
+#define MT6392_ANALDO_CON29                     0x0430
+#define MT6392_DIGLDO_CON0                      0x0500
+#define MT6392_DIGLDO_CON2                      0x0502
+#define MT6392_DIGLDO_CON3                      0x0504
+#define MT6392_DIGLDO_CON5                      0x0506
+#define MT6392_DIGLDO_CON6                      0x0508
+#define MT6392_DIGLDO_CON7                      0x050A
+#define MT6392_DIGLDO_CON8                      0x050C
+#define MT6392_DIGLDO_CON10                     0x0510
+#define MT6392_DIGLDO_CON11                     0x0512
+#define MT6392_DIGLDO_CON12                     0x0514
+#define MT6392_DIGLDO_CON15                     0x051A
+#define MT6392_DIGLDO_CON20                     0x0524
+#define MT6392_DIGLDO_CON21                     0x0526
+#define MT6392_DIGLDO_CON23                     0x0528
+#define MT6392_DIGLDO_CON24                     0x052A
+#define MT6392_DIGLDO_CON26                     0x052C
+#define MT6392_DIGLDO_CON27                     0x052E
+#define MT6392_DIGLDO_CON28                     0x0530
+#define MT6392_DIGLDO_CON29                     0x0532
+#define MT6392_DIGLDO_CON30                     0x0534
+#define MT6392_DIGLDO_CON31                     0x0536
+#define MT6392_DIGLDO_CON32                     0x0538
+#define MT6392_DIGLDO_CON33                     0x053A
+#define MT6392_DIGLDO_CON36                     0x0540
+#define MT6392_DIGLDO_CON41                     0x0546
+#define MT6392_DIGLDO_CON44                     0x054C
+#define MT6392_DIGLDO_CON47                     0x0552
+#define MT6392_DIGLDO_CON48                     0x0554
+#define MT6392_DIGLDO_CON49                     0x0556
+#define MT6392_DIGLDO_CON50                     0x0558
+#define MT6392_DIGLDO_CON51                     0x055A
+#define MT6392_DIGLDO_CON52                     0x055C
+#define MT6392_DIGLDO_CON53                     0x055E
+#define MT6392_DIGLDO_CON54                     0x0560
+#define MT6392_DIGLDO_CON55                     0x0562
+#define MT6392_DIGLDO_CON56                     0x0564
+#define MT6392_DIGLDO_CON57                     0x0566
+#define MT6392_DIGLDO_CON58                     0x0568
+#define MT6392_DIGLDO_CON59                     0x056A
+#define MT6392_DIGLDO_CON60                     0x056C
+#define MT6392_DIGLDO_CON61                     0x056E
+#define MT6392_DIGLDO_CON62                     0x0570
+#define MT6392_DIGLDO_CON63                     0x0572
+#define MT6392_EFUSE_CON0                       0x0600
+#define MT6392_EFUSE_CON1                       0x0602
+#define MT6392_EFUSE_CON2                       0x0604
+#define MT6392_EFUSE_CON3                       0x0606
+#define MT6392_EFUSE_CON4                       0x0608
+#define MT6392_EFUSE_CON5                       0x060A
+#define MT6392_EFUSE_CON6                       0x060C
+#define MT6392_EFUSE_VAL_0_15                   0x060E
+#define MT6392_EFUSE_VAL_16_31                  0x0610
+#define MT6392_EFUSE_VAL_32_47                  0x0612
+#define MT6392_EFUSE_VAL_48_63                  0x0614
+#define MT6392_EFUSE_VAL_64_79                  0x0616
+#define MT6392_EFUSE_VAL_80_95                  0x0618
+#define MT6392_EFUSE_VAL_96_111                 0x061A
+#define MT6392_EFUSE_VAL_112_127                0x061C
+#define MT6392_EFUSE_VAL_128_143                0x061E
+#define MT6392_EFUSE_VAL_144_159                0x0620
+#define MT6392_EFUSE_VAL_160_175                0x0622
+#define MT6392_EFUSE_VAL_176_191                0x0624
+#define MT6392_EFUSE_VAL_192_207                0x0626
+#define MT6392_EFUSE_VAL_208_223                0x0628
+#define MT6392_EFUSE_VAL_224_239                0x062A
+#define MT6392_EFUSE_VAL_240_255                0x062C
+#define MT6392_EFUSE_VAL_256_271                0x062E
+#define MT6392_EFUSE_VAL_272_287                0x0630
+#define MT6392_EFUSE_VAL_288_303                0x0632
+#define MT6392_EFUSE_VAL_304_319                0x0634
+#define MT6392_EFUSE_VAL_320_335                0x0636
+#define MT6392_EFUSE_VAL_336_351                0x0638
+#define MT6392_EFUSE_VAL_352_367                0x063A
+#define MT6392_EFUSE_VAL_368_383                0x063C
+#define MT6392_EFUSE_VAL_384_399                0x063E
+#define MT6392_EFUSE_VAL_400_415                0x0640
+#define MT6392_EFUSE_VAL_416_431                0x0642
+#define MT6392_RTC_MIX_CON0                     0x0644
+#define MT6392_RTC_MIX_CON1                     0x0646
+#define MT6392_EFUSE_VAL_432_447                0x0648
+#define MT6392_EFUSE_VAL_448_463                0x064A
+#define MT6392_EFUSE_VAL_464_479                0x064C
+#define MT6392_EFUSE_VAL_480_495                0x064E
+#define MT6392_EFUSE_VAL_496_511                0x0650
+#define MT6392_EFUSE_DOUT_0_15                  0x0652
+#define MT6392_EFUSE_DOUT_16_31                 0x0654
+#define MT6392_EFUSE_DOUT_32_47                 0x0656
+#define MT6392_EFUSE_DOUT_48_63                 0x0658
+#define MT6392_EFUSE_DOUT_64_79                 0x065A
+#define MT6392_EFUSE_DOUT_80_95                 0x065C
+#define MT6392_EFUSE_DOUT_96_111                0x065E
+#define MT6392_EFUSE_DOUT_112_127               0x0660
+#define MT6392_EFUSE_DOUT_128_143               0x0662
+#define MT6392_EFUSE_DOUT_144_159               0x0664
+#define MT6392_EFUSE_DOUT_160_175               0x0666
+#define MT6392_EFUSE_DOUT_176_191               0x0668
+#define MT6392_EFUSE_DOUT_192_207               0x066A
+#define MT6392_EFUSE_DOUT_208_223               0x066C
+#define MT6392_EFUSE_DOUT_224_239               0x066E
+#define MT6392_EFUSE_DOUT_240_255               0x0670
+#define MT6392_EFUSE_DOUT_256_271               0x0672
+#define MT6392_EFUSE_DOUT_272_287               0x0674
+#define MT6392_EFUSE_DOUT_288_303               0x0676
+#define MT6392_EFUSE_DOUT_304_319               0x0678
+#define MT6392_EFUSE_DOUT_320_335               0x067A
+#define MT6392_EFUSE_DOUT_336_351               0x067C
+#define MT6392_EFUSE_DOUT_352_367               0x067E
+#define MT6392_EFUSE_DOUT_368_383               0x0680
+#define MT6392_EFUSE_DOUT_384_399               0x0682
+#define MT6392_EFUSE_DOUT_400_415               0x0684
+#define MT6392_EFUSE_DOUT_416_431               0x0686
+#define MT6392_EFUSE_DOUT_432_447               0x0688
+#define MT6392_EFUSE_DOUT_448_463               0x068A
+#define MT6392_EFUSE_DOUT_464_479               0x068C
+#define MT6392_EFUSE_DOUT_480_495               0x068E
+#define MT6392_EFUSE_DOUT_496_511               0x0690
+#define MT6392_EFUSE_CON7                       0x0692
+#define MT6392_EFUSE_CON8                       0x0694
+#define MT6392_EFUSE_CON9                       0x0696
+#define MT6392_AUXADC_ADC0                      0x0700
+#define MT6392_AUXADC_ADC1                      0x0702
+#define MT6392_AUXADC_ADC2                      0x0704
+#define MT6392_AUXADC_ADC3                      0x0706
+#define MT6392_AUXADC_ADC4                      0x0708
+#define MT6392_AUXADC_ADC5                      0x070A
+#define MT6392_AUXADC_ADC6                      0x070C
+#define MT6392_AUXADC_ADC7                      0x070E
+#define MT6392_AUXADC_ADC8                      0x0710
+#define MT6392_AUXADC_ADC9                      0x0712
+#define MT6392_AUXADC_ADC10                     0x0714
+#define MT6392_AUXADC_ADC11                     0x0716
+#define MT6392_AUXADC_ADC12                     0x0718
+#define MT6392_AUXADC_ADC13                     0x071A
+#define MT6392_AUXADC_ADC14                     0x071C
+#define MT6392_AUXADC_ADC15                     0x071E
+#define MT6392_AUXADC_ADC16                     0x0720
+#define MT6392_AUXADC_ADC17                     0x0722
+#define MT6392_AUXADC_ADC18                     0x0724
+#define MT6392_AUXADC_ADC19                     0x0726
+#define MT6392_AUXADC_ADC20                     0x0728
+#define MT6392_AUXADC_ADC21                     0x072A
+#define MT6392_AUXADC_ADC22                     0x072C
+#define MT6392_AUXADC_STA0                      0x072E
+#define MT6392_AUXADC_STA1                      0x0730
+#define MT6392_AUXADC_RQST0                     0x0732
+#define MT6392_AUXADC_RQST0_SET                 0x0734
+#define MT6392_AUXADC_RQST0_CLR                 0x0736
+#define MT6392_AUXADC_CON0                      0x0738
+#define MT6392_AUXADC_CON0_SET                  0x073A
+#define MT6392_AUXADC_CON0_CLR                  0x073C
+#define MT6392_AUXADC_CON1                      0x073E
+#define MT6392_AUXADC_CON2                      0x0740
+#define MT6392_AUXADC_CON3                      0x0742
+#define MT6392_AUXADC_CON4                      0x0744
+#define MT6392_AUXADC_CON5                      0x0746
+#define MT6392_AUXADC_CON6                      0x0748
+#define MT6392_AUXADC_CON7                      0x074A
+#define MT6392_AUXADC_CON8                      0x074C
+#define MT6392_AUXADC_CON9                      0x074E
+#define MT6392_AUXADC_CON10                     0x0750
+#define MT6392_AUXADC_CON11                     0x0752
+#define MT6392_AUXADC_CON12                     0x0754
+#define MT6392_AUXADC_CON13                     0x0756
+#define MT6392_AUXADC_CON14                     0x0758
+#define MT6392_AUXADC_CON15                     0x075A
+#define MT6392_AUXADC_CON16                     0x075C
+#define MT6392_AUXADC_AUTORPT0                  0x075E
+#define MT6392_AUXADC_LBAT0                     0x0760
+#define MT6392_AUXADC_LBAT1                     0x0762
+#define MT6392_AUXADC_LBAT2                     0x0764
+#define MT6392_AUXADC_LBAT3                     0x0766
+#define MT6392_AUXADC_LBAT4                     0x0768
+#define MT6392_AUXADC_LBAT5                     0x076A
+#define MT6392_AUXADC_LBAT6                     0x076C
+#define MT6392_AUXADC_THR0                      0x076E
+#define MT6392_AUXADC_THR1                      0x0770
+#define MT6392_AUXADC_THR2                      0x0772
+#define MT6392_AUXADC_THR3                      0x0774
+#define MT6392_AUXADC_THR4                      0x0776
+#define MT6392_AUXADC_THR5                      0x0778
+#define MT6392_AUXADC_THR6                      0x077A
+#define MT6392_AUXADC_EFUSE0                    0x077C
+#define MT6392_AUXADC_EFUSE1                    0x077E
+#define MT6392_AUXADC_EFUSE2                    0x0780
+#define MT6392_AUXADC_EFUSE3                    0x0782
+#define MT6392_AUXADC_EFUSE4                    0x0784
+#define MT6392_AUXADC_EFUSE5                    0x0786
+#define MT6392_AUXADC_NAG_0                     0x0788
+#define MT6392_AUXADC_NAG_1                     0x078A
+#define MT6392_AUXADC_NAG_2                     0x078C
+#define MT6392_AUXADC_NAG_3                     0x078E
+#define MT6392_AUXADC_NAG_4                     0x0790
+#define MT6392_AUXADC_NAG_5                     0x0792
+#define MT6392_AUXADC_NAG_6                     0x0794
+#define MT6392_AUXADC_NAG_7                     0x0796
+#define MT6392_AUXADC_NAG_8                     0x0798
+#define MT6392_AUXADC_TYPEC_H_1                 0x079A
+#define MT6392_AUXADC_TYPEC_H_2                 0x079C
+#define MT6392_AUXADC_TYPEC_H_3                 0x079E
+#define MT6392_AUXADC_TYPEC_H_4                 0x07A0
+#define MT6392_AUXADC_TYPEC_H_5                 0x07A2
+#define MT6392_AUXADC_TYPEC_H_6                 0x07A4
+#define MT6392_AUXADC_TYPEC_H_7                 0x07A6
+#define MT6392_AUXADC_TYPEC_L_1                 0x07A8
+#define MT6392_AUXADC_TYPEC_L_2                 0x07AA
+#define MT6392_AUXADC_TYPEC_L_3                 0x07AC
+#define MT6392_AUXADC_TYPEC_L_4                 0x07AE
+#define MT6392_AUXADC_TYPEC_L_5                 0x07B0
+#define MT6392_AUXADC_TYPEC_L_6                 0x07B2
+#define MT6392_AUXADC_TYPEC_L_7                 0x07B4
+#define MT6392_AUXADC_NAG_9                     0x07B6
+#define MT6392_TYPE_C_PHY_RG_0                  0x0800
+#define MT6392_TYPE_C_PHY_RG_CC_RESERVE_CSR     0x0802
+#define MT6392_TYPE_C_VCMP_CTRL                 0x0804
+#define MT6392_TYPE_C_CTRL                      0x0806
+#define MT6392_TYPE_C_CC_SW_CTRL                0x080a
+#define MT6392_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL  0x080c
+#define MT6392_TYPE_C_CC_VOL_DEBOUCE_CNT_VAL    0x080e
+#define MT6392_TYPE_C_DRP_SRC_CNT_VAL_0         0x0810
+#define MT6392_TYPE_C_DRP_SNK_CNT_VAL_0         0x0814
+#define MT6392_TYPE_C_DRP_TRY_CNT_VAL_0         0x0818
+#define MT6392_TYPE_C_CC_SRC_DEFAULT_DAC_VAL    0x0820
+#define MT6392_TYPE_C_CC_SRC_15_DAC_VAL         0x0822
+#define MT6392_TYPE_C_CC_SRC_30_DAC_VAL         0x0824
+#define MT6392_TYPE_C_CC_SNK_DAC_VAL_0          0x0828
+#define MT6392_TYPE_C_CC_SNK_DAC_VAL_1          0x082a
+#define MT6392_TYPE_C_INTR_EN_0                 0x0830
+#define MT6392_TYPE_C_INTR_EN_2                 0x0834
+#define MT6392_TYPE_C_INTR_0                    0x0838
+#define MT6392_TYPE_C_INTR_2                    0x083C
+#define MT6392_TYPE_C_CC_STATUS                 0x0840
+#define MT6392_TYPE_C_PWR_STATUS                0x0842
+#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_0   0x0844
+#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_1   0x0846
+#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_0   0x0848
+#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_1   0x084a
+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_0 0x0860
+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_0    0x0864
+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_1    0x0866
+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_1 0x0868
+#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_2    0x086c
+#define MT6392_TYPE_C_CC_DAC_CALI_CTRL          0x0870
+#define MT6392_TYPE_C_CC_DAC_CALI_RESULT        0x0872
+#define MT6392_TYPE_C_DEBUG_PORT_SELECT_0       0x0880
+#define MT6392_TYPE_C_DEBUG_PORT_SELECT_1       0x0882
+#define MT6392_TYPE_C_DEBUG_MODE_SELECT         0x0884
+#define MT6392_TYPE_C_DEBUG_OUT_READ_0          0x0888
+#define MT6392_TYPE_C_DEBUG_OUT_READ_1          0x088a
+#define MT6392_TYPE_C_SW_DEBUG_PORT_0           0x088c
+#define MT6392_TYPE_C_SW_DEBUG_PORT_1           0x088e
+
+#endif /* __MFD_MT6392_REGISTERS_H__ */
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 07/24] arm64: dts: mt6392: Add PMIC mt6392 dtsi
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (5 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 06/24] mfd: mt6397: Add support for MT6397 pmic Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-03-28 19:18   ` Rob Herring
  2019-03-23 21:15 ` [PATCH 08/24] dt-bindings: mmc: mtk-sd: add mtk-sd support for MT8516 Fabien Parent
                   ` (16 subsequent siblings)
  23 siblings, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add the regulator nodes for the MT6392 PMIC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt6392.dtsi | 208 +++++++++++++++++++++++
 1 file changed, 208 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt6392.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt6392.dtsi b/arch/arm64/boot/dts/mediatek/mt6392.dtsi
new file mode 100644
index 000000000000..e33a45fd52af
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6392.dtsi
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+&pwrap {
+	pmic: mt6392 {
+		compatible = "mediatek,mt6392", "mediatek,mt6323";
+		mediatek,system-power-controller;
+
+		mt6392_regulator: mt6392_regulator {
+			compatible = "mediatek,mt6392-regulator";
+
+			mt6392_vproc_reg: buck_vproc {
+				regulator-name = "buck_vproc";
+				regulator-min-microvolt = < 700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <12500>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vsys_reg: buck_vsys {
+				regulator-name = "buck_vsys";
+				regulator-min-microvolt = <1400000>;
+				regulator-max-microvolt = <2987500>;
+				regulator-ramp-delay = <25000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vcore_reg: buck_vcore {
+				regulator-name = "buck_vcore";
+				regulator-min-microvolt = < 700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <12500>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vxo22_reg: ldo_vxo22 {
+				regulator-name = "ldo_vxo22";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <2200000>;
+				regulator-enable-ramp-delay = <110>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vaud22_reg: ldo_vaud22 {
+				regulator-name = "ldo_vaud22";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <2200000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vcama_reg: ldo_vcama {
+				regulator-name = "ldo_vcama";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vaud28_reg: ldo_vaud28 {
+				regulator-name = "ldo_vaud28";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vadc18_reg: ldo_vadc18 {
+				regulator-name = "ldo_vadc18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vcn35_reg: ldo_vcn35 {
+				regulator-name = "ldo_vcn35";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vio28_reg: ldo_vio28 {
+				regulator-name = "ldo_vio28";
+				regulator-min-microvolt = <2800000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vusb_reg: ldo_vusb {
+				regulator-name = "ldo_vusb";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vmc_reg: ldo_vmc {
+				regulator-name = "ldo_vmc";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-boot-on;
+			};
+
+			mt6392_vmch_reg: ldo_vmch {
+				regulator-name = "ldo_vmch";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-boot-on;
+			};
+
+			mt6392_vemc3v3_reg: ldo_vemc3v3 {
+				regulator-name = "ldo_vemc3v3";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-boot-on;
+			};
+
+			mt6392_vgp1_reg: ldo_vgp1 {
+				regulator-name = "ldo_vgp1";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vgp2_reg: ldo_vgp2 {
+				regulator-name = "ldo_vgp2";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vcn18_reg: ldo_vcn18 {
+				regulator-name = "ldo_vcn18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vcamaf_reg: ldo_vcamaf {
+				regulator-name = "ldo_vcamaf";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vm_reg: ldo_vm {
+				regulator-name = "ldo_vm";
+				regulator-min-microvolt = <1240000>;
+				regulator-max-microvolt = <1390000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vio18_reg: ldo_vio18 {
+				regulator-name = "ldo_vio18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			mt6392_vcamd_reg: ldo_vcamd {
+				regulator-name = "ldo_vcamd";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vcamio_reg: ldo_vcamio {
+				regulator-name = "ldo_vcamio";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vm25_reg: ldo_vm25 {
+				regulator-name = "ldo_vm25";
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+
+			mt6392_vefuse_reg: ldo_vefuse {
+				regulator-name = "ldo_vefuse";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-enable-ramp-delay = <264>;
+			};
+		};
+	};
+};
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 08/24] dt-bindings: mmc: mtk-sd: add mtk-sd support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (6 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 07/24] arm64: dts: mt6392: Add PMIC mt6392 dtsi Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-03-23 21:15 ` [PATCH 09/24] mmc: mtk-sd: check for valid optional memory resource Fabien Parent
                   ` (15 subsequent siblings)
  23 siblings, 0 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of mtk-sd for MT8516 SoCs.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index f5bcda3980cc..91a2ec59e497 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -11,6 +11,7 @@ Required properties:
 	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
 	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
 	"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
+	"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
 	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
 	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
 	"mediatek,mt7622-mmc": for MT7622 SoC
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 09/24] mmc: mtk-sd: check for valid optional memory resource
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (7 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 08/24] dt-bindings: mmc: mtk-sd: add mtk-sd support for MT8516 Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-03-24  3:34   ` Yingjoe Chen
  2019-03-23 21:15 ` [PATCH 10/24] mmc: mtk-sd: add support for MT8516 Fabien Parent
                   ` (14 subsequent siblings)
  23 siblings, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

'top_base' memory region is optional. Check that the resource is valid
before using it. This avoid getting a "invalid resource" error message
printed by the kernel.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/mmc/host/mtk-sd.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 833ef0590af8..573aa127d00b 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -2123,9 +2123,11 @@ static int msdc_drv_probe(struct platform_device *pdev)
 	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	host->top_base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(host->top_base))
-		host->top_base = NULL;
+	if (ret) {
+		host->top_base = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(host->top_base))
+			host->top_base = NULL;
+	}
 
 	ret = mmc_regulator_get_supply(mmc);
 	if (ret)
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 10/24] mmc: mtk-sd: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (8 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 09/24] mmc: mtk-sd: check for valid optional memory resource Fabien Parent
@ 2019-03-23 21:15 ` Fabien Parent
  2019-03-23 21:15 ` [PATCH 11/24] dt-bindings: mediatek: topckgen: " Fabien Parent
                   ` (13 subsequent siblings)
  23 siblings, 0 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add the MSDC configuration for the MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/mmc/host/mtk-sd.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 573aa127d00b..51139275b1b2 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -507,6 +507,16 @@ static const struct mtk_mmc_compatible mt7622_compat = {
 	.support_64g = false,
 };
 
+static const struct mtk_mmc_compatible mt8516_compat = {
+	.clk_div_bits = 12,
+	.hs400_tune = false,
+	.pad_tune_reg = MSDC_PAD_TUNE0,
+	.async_fifo = true,
+	.data_tune = true,
+	.busy_check = true,
+	.stop_clk_fix = true,
+};
+
 static const struct of_device_id msdc_of_ids[] = {
 	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
 	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
@@ -514,6 +524,7 @@ static const struct of_device_id msdc_of_ids[] = {
 	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
 	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
+	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
 	{}
 };
 MODULE_DEVICE_TABLE(of, msdc_of_ids);
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 11/24] dt-bindings: mediatek: topckgen: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (9 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 10/24] mmc: mtk-sd: add support for MT8516 Fabien Parent
@ 2019-03-23 21:15 ` " Fabien Parent
  2019-03-28 19:09   ` Rob Herring
  2019-04-25 21:34   ` Stephen Boyd
  2019-03-23 21:16 ` [PATCH 12/24] dt-bindings: mediatek: infracfg: " Fabien Parent
                   ` (12 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:15 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of topckgen for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 .../arm/mediatek/mediatek,topckgen.txt        |   1 +
 include/dt-bindings/clock/mt8516-clk.h        | 192 ++++++++++++++++++
 2 files changed, 193 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt8516-clk.h

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index d160c2b4b6fe..0843d73a1282 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -14,6 +14,7 @@ Required Properties:
 	- "mediatek,mt7629-topckgen"
 	- "mediatek,mt8135-topckgen"
 	- "mediatek,mt8173-topckgen"
+	- "mediatek,mt8516-topckgen"
 - #clock-cells: Must be 1
 
 The topckgen controller uses the common clk binding from
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
new file mode 100644
index 000000000000..8d44cb32efba
--- /dev/null
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8516_H
+#define _DT_BINDINGS_CLK_MT8516_H
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL		0
+#define CLK_TOP_I2S_INFRA_BCK		1
+#define CLK_TOP_MEMPLL			2
+#define CLK_TOP_DMPLL			3
+#define CLK_TOP_MAINPLL_D2		4
+#define CLK_TOP_MAINPLL_D4		5
+#define CLK_TOP_MAINPLL_D8		6
+#define CLK_TOP_MAINPLL_D16		7
+#define CLK_TOP_MAINPLL_D11		8
+#define CLK_TOP_MAINPLL_D22		9
+#define CLK_TOP_MAINPLL_D3		10
+#define CLK_TOP_MAINPLL_D6		11
+#define CLK_TOP_MAINPLL_D12		12
+#define CLK_TOP_MAINPLL_D5		13
+#define CLK_TOP_MAINPLL_D10		14
+#define CLK_TOP_MAINPLL_D20		15
+#define CLK_TOP_MAINPLL_D40		16
+#define CLK_TOP_MAINPLL_D7		17
+#define CLK_TOP_MAINPLL_D14		18
+#define CLK_TOP_UNIVPLL_D2		19
+#define CLK_TOP_UNIVPLL_D4		20
+#define CLK_TOP_UNIVPLL_D8		21
+#define CLK_TOP_UNIVPLL_D16		22
+#define CLK_TOP_UNIVPLL_D3		23
+#define CLK_TOP_UNIVPLL_D6		24
+#define CLK_TOP_UNIVPLL_D12		25
+#define CLK_TOP_UNIVPLL_D24		26
+#define CLK_TOP_UNIVPLL_D5		27
+#define CLK_TOP_UNIVPLL_D20		28
+#define CLK_TOP_MMPLL380M		29
+#define CLK_TOP_MMPLL_D2		30
+#define CLK_TOP_MMPLL_200M		31
+#define CLK_TOP_USB_PHY48M		32
+#define CLK_TOP_APLL1			33
+#define CLK_TOP_APLL1_D2		34
+#define CLK_TOP_APLL1_D4		35
+#define CLK_TOP_APLL1_D8		36
+#define CLK_TOP_APLL2			37
+#define CLK_TOP_APLL2_D2		38
+#define CLK_TOP_APLL2_D4		39
+#define CLK_TOP_APLL2_D8		40
+#define CLK_TOP_CLK26M			41
+#define CLK_TOP_CLK26M_D2		42
+#define CLK_TOP_AHB_INFRA_D2		43
+#define CLK_TOP_NFI1X			44
+#define CLK_TOP_ETH_D2			45
+#define CLK_TOP_THEM			46
+#define CLK_TOP_APDMA			47
+#define CLK_TOP_I2C0			48
+#define CLK_TOP_I2C1			49
+#define CLK_TOP_AUXADC1			50
+#define CLK_TOP_NFI			51
+#define CLK_TOP_NFIECC			52
+#define CLK_TOP_DEBUGSYS		53
+#define CLK_TOP_PWM			54
+#define CLK_TOP_UART0			55
+#define CLK_TOP_UART1			56
+#define CLK_TOP_BTIF			57
+#define CLK_TOP_USB			58
+#define CLK_TOP_FLASHIF_26M		59
+#define CLK_TOP_AUXADC2			60
+#define CLK_TOP_I2C2			61
+#define CLK_TOP_MSDC0			62
+#define CLK_TOP_MSDC1			63
+#define CLK_TOP_NFI2X			64
+#define CLK_TOP_PMICWRAP_AP		65
+#define CLK_TOP_SEJ			66
+#define CLK_TOP_MEMSLP_DLYER		67
+#define CLK_TOP_SPI			68
+#define CLK_TOP_APXGPT			69
+#define CLK_TOP_AUDIO			70
+#define CLK_TOP_PMICWRAP_MD		71
+#define CLK_TOP_PMICWRAP_CONN		72
+#define CLK_TOP_PMICWRAP_26M		73
+#define CLK_TOP_AUX_ADC			74
+#define CLK_TOP_AUX_TP			75
+#define CLK_TOP_MSDC2			76
+#define CLK_TOP_RBIST			77
+#define CLK_TOP_NFI_BUS			78
+#define CLK_TOP_GCE			79
+#define CLK_TOP_TRNG			80
+#define CLK_TOP_SEJ_13M			81
+#define CLK_TOP_AES			82
+#define CLK_TOP_PWM_B			83
+#define CLK_TOP_PWM1_FB			84
+#define CLK_TOP_PWM2_FB			85
+#define CLK_TOP_PWM3_FB			86
+#define CLK_TOP_PWM4_FB			87
+#define CLK_TOP_PWM5_FB			88
+#define CLK_TOP_USB_1P			89
+#define CLK_TOP_FLASHIF_FREERUN		90
+#define CLK_TOP_66M_ETH			91
+#define CLK_TOP_133M_ETH		92
+#define CLK_TOP_FETH_25M		93
+#define CLK_TOP_FETH_50M		94
+#define CLK_TOP_FLASHIF_AXI		95
+#define CLK_TOP_USBIF			96
+#define CLK_TOP_UART2			97
+#define CLK_TOP_BSI			98
+#define CLK_TOP_RG_SPINOR		99
+#define CLK_TOP_RG_MSDC2		100
+#define CLK_TOP_RG_ETH			101
+#define CLK_TOP_RG_AUD1			102
+#define CLK_TOP_RG_AUD2			103
+#define CLK_TOP_RG_AUD_ENGEN1		104
+#define CLK_TOP_RG_AUD_ENGEN2		105
+#define CLK_TOP_RG_I2C			106
+#define CLK_TOP_RG_PWM_INFRA		107
+#define CLK_TOP_RG_AUD_SPDIF_IN		108
+#define CLK_TOP_RG_UART2		109
+#define CLK_TOP_RG_BSI			110
+#define CLK_TOP_RG_DBG_ATCLK		111
+#define CLK_TOP_RG_NFIECC		112
+#define CLK_TOP_RG_APLL1_D2_EN		113
+#define CLK_TOP_RG_APLL1_D4_EN		114
+#define CLK_TOP_RG_APLL1_D8_EN		115
+#define CLK_TOP_RG_APLL2_D2_EN		116
+#define CLK_TOP_RG_APLL2_D4_EN		117
+#define CLK_TOP_RG_APLL2_D8_EN		118
+#define CLK_TOP_APLL12_DIV0		119
+#define CLK_TOP_APLL12_DIV1		120
+#define CLK_TOP_APLL12_DIV2		121
+#define CLK_TOP_APLL12_DIV3		122
+#define CLK_TOP_APLL12_DIV4		123
+#define CLK_TOP_APLL12_DIV4B		124
+#define CLK_TOP_APLL12_DIV5		125
+#define CLK_TOP_APLL12_DIV5B		126
+#define CLK_TOP_APLL12_DIV6		127
+#define CLK_TOP_UART0_SEL		128
+#define CLK_TOP_EMI_DDRPHY_SEL		129
+#define CLK_TOP_AHB_INFRA_SEL		130
+#define CLK_TOP_MSDC0_SEL		131
+#define CLK_TOP_UART1_SEL		132
+#define CLK_TOP_MSDC1_SEL		133
+#define CLK_TOP_PMICSPI_SEL		134
+#define CLK_TOP_QAXI_AUD26M_SEL		135
+#define CLK_TOP_AUD_INTBUS_SEL		136
+#define CLK_TOP_NFI2X_PAD_SEL		137
+#define CLK_TOP_NFI1X_PAD_SEL		138
+#define CLK_TOP_DDRPHYCFG_SEL		139
+#define CLK_TOP_USB_78M_SEL		140
+#define CLK_TOP_SPINOR_SEL		141
+#define CLK_TOP_MSDC2_SEL		142
+#define CLK_TOP_ETH_SEL			143
+#define CLK_TOP_AUD1_SEL		144
+#define CLK_TOP_AUD2_SEL		145
+#define CLK_TOP_AUD_ENGEN1_SEL		146
+#define CLK_TOP_AUD_ENGEN2_SEL		147
+#define CLK_TOP_I2C_SEL			148
+#define CLK_TOP_AUD_I2S0_M_SEL		149
+#define CLK_TOP_AUD_I2S1_M_SEL		150
+#define CLK_TOP_AUD_I2S2_M_SEL		151
+#define CLK_TOP_AUD_I2S3_M_SEL		152
+#define CLK_TOP_AUD_I2S4_M_SEL		153
+#define CLK_TOP_AUD_I2S5_M_SEL		154
+#define CLK_TOP_AUD_SPDIF_B_SEL		155
+#define CLK_TOP_PWM_SEL			156
+#define CLK_TOP_SPI_SEL			157
+#define CLK_TOP_AUD_SPDIFIN_SEL		158
+#define CLK_TOP_UART2_SEL		159
+#define CLK_TOP_BSI_SEL			160
+#define CLK_TOP_DBG_ATCLK_SEL		161
+#define CLK_TOP_CSW_NFIECC_SEL		162
+#define CLK_TOP_NFIECC_SEL		163
+#define CLK_TOP_APLL12_CK_DIV0		164
+#define CLK_TOP_APLL12_CK_DIV1		165
+#define CLK_TOP_APLL12_CK_DIV2		166
+#define CLK_TOP_APLL12_CK_DIV3		167
+#define CLK_TOP_APLL12_CK_DIV4		168
+#define CLK_TOP_APLL12_CK_DIV4B		169
+#define CLK_TOP_APLL12_CK_DIV5		170
+#define CLK_TOP_APLL12_CK_DIV5B		171
+#define CLK_TOP_APLL12_CK_DIV6		172
+#define CLK_TOP_USB_78M			173
+#define CLK_TOP_MSDC0_INFRA		174
+#define CLK_TOP_MSDC1_INFRA		175
+#define CLK_TOP_MSDC2_INFRA		176
+#define CLK_TOP_NR_CLK			177
+
+#endif /* _DT_BINDINGS_CLK_MT8516_H */
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 12/24] dt-bindings: mediatek: infracfg: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (10 preceding siblings ...)
  2019-03-23 21:15 ` [PATCH 11/24] dt-bindings: mediatek: topckgen: " Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-03-28 19:10   ` Rob Herring
  2019-04-25 21:34   ` Stephen Boyd
  2019-03-23 21:16 ` [PATCH 13/24] dt-bindings: mediatek: apmixedsys: " Fabien Parent
                   ` (11 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of infracfg for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 .../bindings/arm/mediatek/mediatek,infracfg.txt          | 1 +
 include/dt-bindings/clock/mt8516-clk.h                   | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index 417bd83d1378..cbc38a8ee985 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -15,6 +15,7 @@ Required Properties:
 	- "mediatek,mt7629-infracfg", "syscon"
 	- "mediatek,mt8135-infracfg", "syscon"
 	- "mediatek,mt8173-infracfg", "syscon"
+	- "mediatek,mt8516-infracfg", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1
 
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
index 8d44cb32efba..956ee2c0748e 100644
--- a/include/dt-bindings/clock/mt8516-clk.h
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -8,6 +8,15 @@
 #ifndef _DT_BINDINGS_CLK_MT8516_H
 #define _DT_BINDINGS_CLK_MT8516_H
 
+/* INFRACFG */
+
+#define CLK_IFR_MUX1_SEL		0
+#define CLK_IFR_ETH_25M_SEL		1
+#define CLK_IFR_I2C0_SEL		2
+#define CLK_IFR_I2C1_SEL		3
+#define CLK_IFR_I2C2_SEL		4
+#define CLK_IFR_NR_CLK			5
+
 /* TOPCKGEN */
 
 #define CLK_TOP_CLK_NULL		0
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 13/24] dt-bindings: mediatek: apmixedsys: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (11 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 12/24] dt-bindings: mediatek: infracfg: " Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-03-28 19:11   ` Rob Herring
  2019-04-25 21:35   ` Stephen Boyd
  2019-03-23 21:16 ` [PATCH 14/24] clk: mediatek: add clock driver " Fabien Parent
                   ` (10 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of apmixedsys for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 .../bindings/arm/mediatek/mediatek,apmixedsys.txt      |  1 +
 include/dt-bindings/clock/mt8516-clk.h                 | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index de4075413d91..c33d83f066c9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -14,6 +14,7 @@ Required Properties:
 	- "mediatek,mt7629-apmixedsys"
 	- "mediatek,mt8135-apmixedsys"
 	- "mediatek,mt8173-apmixedsys"
+	- "mediatek,mt8516-apmixedsys"
 - #clock-cells: Must be 1
 
 The apmixedsys controller uses the common clk binding from
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
index 956ee2c0748e..9cfca53cd78d 100644
--- a/include/dt-bindings/clock/mt8516-clk.h
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -8,6 +8,16 @@
 #ifndef _DT_BINDINGS_CLK_MT8516_H
 #define _DT_BINDINGS_CLK_MT8516_H
 
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIVPLL		2
+#define CLK_APMIXED_MMPLL		3
+#define CLK_APMIXED_APLL1		4
+#define CLK_APMIXED_APLL2		5
+#define CLK_APMIXED_NR_CLK		6
+
 /* INFRACFG */
 
 #define CLK_IFR_MUX1_SEL		0
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 14/24] clk: mediatek: add clock driver for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (12 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 13/24] dt-bindings: mediatek: apmixedsys: " Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-04-25 21:39   ` Stephen Boyd
  2019-03-23 21:16 ` [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support " Fabien Parent
                   ` (9 subsequent siblings)
  23 siblings, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add the clock driver for the MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/clk/mediatek/Kconfig      |   9 +
 drivers/clk/mediatek/Makefile     |   1 +
 drivers/clk/mediatek/clk-mt8516.c | 815 ++++++++++++++++++++++++++++++
 3 files changed, 825 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8516.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 53edade25a1d..1e951ae49982 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -216,4 +216,13 @@ config COMMON_CLK_MT8173
 	default ARCH_MEDIATEK
 	---help---
 	  This driver supports MediaTek MT8173 clocks.
+
+config COMMON_CLK_MT8516
+	bool "Clock driver for MediaTek MT8516"
+	depends on ARCH_MEDIATEK || COMPILE_TEST
+	select COMMON_CLK_MEDIATEK
+	default ARCH_MEDIATEK
+	help
+	  This driver supports MediaTek MT8516 clocks.
+
 endmenu
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index ee4410ff43ab..c4f413ef5aad 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
 obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
new file mode 100644
index 000000000000..26fe43cc9ea2
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -0,0 +1,815 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ *         Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8516-clk.h>
+
+static DEFINE_SPINLOCK(mt8516_clk_lock);
+
+static const struct mtk_fixed_clk fixed_clks[] __initconst = {
+	FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
+	FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
+	FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
+};
+
+static const struct mtk_fixed_factor top_divs[] __initconst = {
+	FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
+	FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
+	FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
+	FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
+	FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
+	FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
+	FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
+	FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
+	FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
+	FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
+	FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
+	FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
+	FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
+	FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
+	FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
+	FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
+	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+	FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
+	FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
+	FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
+	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+	FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
+	FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
+	FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
+	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+	FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
+	FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
+	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
+	FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
+	FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
+	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
+	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
+	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
+	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
+	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
+	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
+	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
+	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
+	FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
+	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
+	FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
+	FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
+	FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
+};
+
+static const char * const uart0_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d24"
+};
+
+static const char * const ahb_infra_parents[] __initconst = {
+	"clk_null",
+	"clk26m_ck",
+	"mainpll_d11",
+	"clk_null",
+	"mainpll_d12",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"mainpll_d10"
+};
+
+static const char * const msdc0_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d6",
+	"mainpll_d8",
+	"univpll_d8",
+	"mainpll_d16",
+	"mmpll_200m",
+	"mainpll_d12",
+	"mmpll_d2"
+};
+
+static const char * const uart1_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d24"
+};
+
+static const char * const msdc1_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d6",
+	"mainpll_d8",
+	"univpll_d8",
+	"mainpll_d16",
+	"mmpll_200m",
+	"mainpll_d12",
+	"mmpll_d2"
+};
+
+static const char * const pmicspi_parents[] __initconst = {
+	"univpll_d20",
+	"usb_phy48m_ck",
+	"univpll_d16",
+	"clk26m_ck"
+};
+
+static const char * const qaxi_aud26m_parents[] __initconst = {
+	"clk26m_ck",
+	"ahb_infra_sel"
+};
+
+static const char * const aud_intbus_parents[] __initconst = {
+	"clk_null",
+	"clk26m_ck",
+	"mainpll_d22",
+	"clk_null",
+	"mainpll_d11"
+};
+
+static const char * const nfi2x_pad_parents[] __initconst = {
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk26m_ck",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"mainpll_d12",
+	"mainpll_d8",
+	"clk_null",
+	"mainpll_d6",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"mainpll_d4",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"clk_null",
+	"mainpll_d10",
+	"mainpll_d7",
+	"clk_null",
+	"mainpll_d5"
+};
+
+static const char * const nfi1x_pad_parents[] __initconst = {
+	"ahb_infra_sel",
+	"nfi1x_ck"
+};
+
+static const char * const ddrphycfg_parents[] __initconst = {
+	"clk26m_ck",
+	"mainpll_d16"
+};
+
+static const char * const usb_78m_parents[] __initconst = {
+	"clk_null",
+	"clk26m_ck",
+	"univpll_d16",
+	"clk_null",
+	"mainpll_d20"
+};
+
+static const char * const spinor_parents[] __initconst = {
+	"clk26m_d2",
+	"clk26m_ck",
+	"mainpll_d40",
+	"univpll_d24",
+	"univpll_d20",
+	"mainpll_d20",
+	"mainpll_d16",
+	"univpll_d12"
+};
+
+static const char * const msdc2_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d6",
+	"mainpll_d8",
+	"univpll_d8",
+	"mainpll_d16",
+	"mmpll_200m",
+	"mainpll_d12",
+	"mmpll_d2"
+};
+
+static const char * const eth_parents[] __initconst = {
+	"clk26m_ck",
+	"mainpll_d40",
+	"univpll_d24",
+	"univpll_d20",
+	"mainpll_d20"
+};
+
+static const char * const aud1_parents[] __initconst = {
+	"clk26m_ck",
+	"apll1_ck"
+};
+
+static const char * const aud2_parents[] __initconst = {
+	"clk26m_ck",
+	"apll2_ck"
+};
+
+static const char * const aud_engen1_parents[] __initconst = {
+	"clk26m_ck",
+	"rg_apll1_d2_en",
+	"rg_apll1_d4_en",
+	"rg_apll1_d8_en"
+};
+
+static const char * const aud_engen2_parents[] __initconst = {
+	"clk26m_ck",
+	"rg_apll2_d2_en",
+	"rg_apll2_d4_en",
+	"rg_apll2_d8_en"
+};
+
+static const char * const i2c_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d20",
+	"univpll_d16",
+	"univpll_d12"
+};
+
+static const char * const aud_i2s0_m_parents[] __initconst = {
+	"rg_aud1",
+	"rg_aud2"
+};
+
+static const char * const pwm_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d12"
+};
+
+static const char * const spi_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d12",
+	"univpll_d8",
+	"univpll_d6"
+};
+
+static const char * const aud_spdifin_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d2"
+};
+
+static const char * const uart2_parents[] __initconst = {
+	"clk26m_ck",
+	"univpll_d24"
+};
+
+static const char * const bsi_parents[] __initconst = {
+	"clk26m_ck",
+	"mainpll_d10",
+	"mainpll_d12",
+	"mainpll_d20"
+};
+
+static const char * const dbg_atclk_parents[] __initconst = {
+	"clk_null",
+	"clk26m_ck",
+	"mainpll_d5",
+	"clk_null",
+	"univpll_d5"
+};
+
+static const char * const csw_nfiecc_parents[] __initconst = {
+	"clk_null",
+	"mainpll_d7",
+	"mainpll_d6",
+	"clk_null",
+	"mainpll_d5"
+};
+
+static const char * const nfiecc_parents[] __initconst = {
+	"clk_null",
+	"nfi2x_pad_sel",
+	"mainpll_d4",
+	"clk_null",
+	"csw_nfiecc_sel"
+};
+
+static struct mtk_composite top_muxes[] __initdata = {
+	/* CLK_MUX_SEL0 */
+	MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
+		0x000, 0, 1),
+	MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
+		0x000, 4, 4),
+	MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
+		0x000, 11, 3),
+	MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
+		0x000, 19, 1),
+	MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
+		0x000, 20, 3),
+	MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
+		0x000, 24, 2),
+	MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
+		0x000, 26, 1),
+	MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
+		0x000, 27, 3),
+	/* CLK_MUX_SEL1 */
+	MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
+		0x004, 0, 7),
+	MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
+		0x004, 7, 1),
+	MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
+		0x004, 20, 3),
+	/* CLK_MUX_SEL8 */
+	MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
+		0x040, 0, 3),
+	MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
+		0x040, 3, 3),
+	MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
+		0x040, 6, 3),
+	MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
+		0x040, 22, 1),
+	MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
+		0x040, 23, 1),
+	MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
+		0x040, 24, 2),
+	MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
+		0x040, 26, 2),
+	MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
+		0x040, 28, 2),
+	/* CLK_SEL_9 */
+	MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
+		0x044, 12, 1),
+	MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
+		0x044, 13, 1),
+	MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
+		0x044, 14, 1),
+	MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
+		0x044, 15, 1),
+	MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
+		0x044, 16, 1),
+	MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
+		0x044, 17, 1),
+	MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
+		0x044, 18, 1),
+	/* CLK_MUX_SEL13 */
+	MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
+		0x07c, 0, 1),
+	MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
+		0x07c, 1, 2),
+	MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
+		0x07c, 3, 1),
+	MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
+		0x07c, 4, 1),
+	MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
+		0x07c, 5, 2),
+	MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
+		0x07c, 7, 3),
+	MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
+		0x07c, 10, 3),
+	MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
+		0x07c, 13, 3),
+};
+
+static const char * const ifr_mux1_parents[] __initconst = {
+	"clk26m_ck",
+	"armpll",
+	"univpll",
+	"mainpll_d2"
+};
+
+static const char * const ifr_eth_25m_parents[] __initconst = {
+	"eth_d2_ck",
+	"rg_eth"
+};
+
+static const char * const ifr_i2c0_parents[] __initconst = {
+	"ahb_infra_d2",
+	"rg_i2c"
+};
+
+static const struct mtk_composite ifr_muxes[] __initconst = {
+	MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
+		2, 2),
+	MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
+		0, 1),
+	MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
+		1, 1),
+	MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
+		2, 1),
+	MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
+		3, 1),
+};
+
+#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) {	\
+		.id = _id,					\
+		.name = _name,					\
+		.parent_name = _parent,				\
+		.div_reg = _reg,				\
+		.div_shift = _shift,				\
+		.div_width = _width,				\
+}
+
+static const struct mtk_clk_divider top_adj_divs[] = {
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
+		0x0048, 0, 8),
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
+		0x0048, 8, 8),
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
+		0x0048, 16, 8),
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
+		0x0048, 24, 8),
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
+		0x004c, 0, 8),
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
+		0x004c, 8, 8),
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
+		0x004c, 16, 8),
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
+		0x004c, 24, 8),
+	DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
+		0x0078, 0, 8),
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+	.set_ofs = 0x54,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+	.set_ofs = 0x6c,
+	.clr_ofs = 0x9c,
+	.sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+	.set_ofs = 0xa0,
+	.clr_ofs = 0xb0,
+	.sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xb4,
+	.sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+	.set_ofs = 0x44,
+	.clr_ofs = 0x44,
+	.sta_ofs = 0x44,
+};
+
+#define GATE_TOP1(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &top1_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_setclr,	\
+	}
+
+#define GATE_TOP2(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &top2_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_setclr,	\
+	}
+
+#define GATE_TOP2_I(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &top2_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_setclr_inv,	\
+	}
+
+#define GATE_TOP3(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &top3_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_setclr,	\
+	}
+
+#define GATE_TOP4_I(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &top4_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_setclr_inv,	\
+	}
+
+#define GATE_TOP5(_id, _name, _parent, _shift) {	\
+		.id = _id,				\
+		.name = _name,				\
+		.parent_name = _parent,			\
+		.regs = &top5_cg_regs,			\
+		.shift = _shift,			\
+		.ops = &mtk_clk_gate_ops_no_setclr,	\
+	}
+
+static const struct mtk_gate top_clks[] __initconst = {
+	/* TOP1 */
+	GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
+	GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
+	GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
+	GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
+	GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
+	GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
+	GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
+	GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
+	GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
+	GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
+	GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
+	GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
+	GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
+	GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
+	GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
+	GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
+	GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
+	GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
+	GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
+	GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
+	GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
+	GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
+	GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
+	GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
+	GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
+	GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
+	GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
+	GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
+	GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
+	GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
+	/* TOP2 */
+	GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
+	GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
+	GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
+	GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
+	GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
+	GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
+	GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
+	GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
+	GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
+	GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
+	GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
+	GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
+	GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
+	GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
+	GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
+		15),
+	GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
+	GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
+	GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
+	GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
+	GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
+	GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
+	GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
+	GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
+	GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
+	GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
+	GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
+	GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
+	/* TOP3 */
+	GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
+	GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
+	GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
+	GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
+	GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
+	GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
+	GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
+	GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
+	GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
+	GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
+		14),
+	GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
+	GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
+	GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
+	GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
+	/* TOP4 */
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
+	GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
+	GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
+	/* TOP5 */
+	GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
+	GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
+	GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
+	GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
+	GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
+	GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
+	GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
+	GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
+	GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
+};
+
+static void __init mtk_topckgen_init(struct device_node *node)
+{
+	struct clk_onecell_data *clk_data;
+	int r;
+	void __iomem *base;
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s(): ioremap failed\n", __func__);
+		return;
+	}
+
+	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+	mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
+				    clk_data);
+	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
+
+	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
+		&mt8516_clk_lock, clk_data);
+	mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
+				base, &mt8516_clk_lock, clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+			__func__, r);
+}
+CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init);
+
+static void __init mtk_infracfg_init(struct device_node *node)
+{
+	struct clk_onecell_data *clk_data;
+	int r;
+	void __iomem *base;
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s(): ioremap failed\n", __func__);
+		return;
+	}
+
+	clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
+
+	mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
+		&mt8516_clk_lock, clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+			__func__, r);
+}
+CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init);
+
+#define MT8516_PLL_FMAX		(1502UL * MHZ)
+
+#define CON0_MT8516_RST_BAR	BIT(27)
+
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
+			_pcw_shift, _div_table) {			\
+		.id = _id,						\
+		.name = _name,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.flags = _flags,					\
+		.rst_bar_mask = CON0_MT8516_RST_BAR,			\
+		.fmax = MT8516_PLL_FMAX,				\
+		.pcwbits = _pcwbits,					\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = _pd_shift,					\
+		.tuner_reg = _tuner_reg,				\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = _pcw_shift,				\
+		.div_table = _div_table,				\
+	}
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
+			_pcw_shift)					\
+		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+			NULL)
+
+static const struct mtk_pll_div_table mmpll_div_table[] = {
+	{ .div = 0, .freq = MT8516_PLL_FMAX },
+	{ .div = 1, .freq = 1000000000 },
+	{ .div = 2, .freq = 604500000 },
+	{ .div = 3, .freq = 253500000 },
+	{ .div = 4, .freq = 126750000 },
+	{ } /* sentinel */
+};
+
+static const struct mtk_pll_data plls[] = {
+	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
+		21, 0x0104, 24, 0, 0x0104, 0),
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001,
+		HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001,
+		HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
+	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0,
+		21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0,
+		31, 0x0180, 1, 0x0194, 0x0184, 0),
+	PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0,
+		31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
+};
+
+static void __init mtk_apmixedsys_init(struct device_node *node)
+{
+	struct clk_onecell_data *clk_data;
+	void __iomem *base;
+	int r;
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s(): ioremap failed\n", __func__);
+		return;
+	}
+
+	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+	if (r)
+		pr_err("%s(): could not register clock provider: %d\n",
+			__func__, r);
+
+}
+CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8516-apmixedsys",
+		mtk_apmixedsys_init);
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (13 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 14/24] clk: mediatek: add clock driver " Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-03-28 19:11   ` Rob Herring
  2019-04-08 20:44   ` Linus Walleij
  2019-03-23 21:16 ` [PATCH 16/24] pinctrl: mediatek: Add MT8516 Pinctrl driver Fabien Parent
                   ` (8 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of pinctrl-mt65xx for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
index e7d6f81c227f..205be98ae078 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -11,6 +11,7 @@ Required properties:
 	"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
 	"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
 	"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
+	"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
   specify pins.
 - gpio-controller : Marks the device node as a gpio controller.
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 16/24] pinctrl: mediatek: Add MT8516 Pinctrl driver
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (14 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support " Fabien Parent
@ 2019-03-23 21:16 ` Fabien Parent
  2019-04-01 21:02   ` Sean Wang
  2019-03-23 21:16 ` [PATCH 17/24] dt-bindings: wdog: mtk-wdt: add support for MT851 Fabien Parent
                   ` (7 subsequent siblings)
  23 siblings, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 drivers/pinctrl/mediatek/Kconfig              |    7 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt8516.c     |  384 ++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h | 1182 +++++++++++++++++
 4 files changed, 1574 insertions(+)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8516.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h

diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index a005cbccb4f7..26ed5dca1460 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -113,6 +113,13 @@ config PINCTRL_MT8183
 	default ARM64 && ARCH_MEDIATEK
 	select PINCTRL_MTK_PARIS
 
+config PINCTRL_MT8516
+	bool "Mediatek MT8516 pin control"
+	depends on OF
+	depends on ARM64 || COMPILE_TEST
+	default ARM64 && ARCH_MEDIATEK
+	select PINCTRL_MTK
+
 # For PMIC
 config PINCTRL_MT6397
 	bool "Mediatek MT6397 pin control"
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 4b4e2eaf6f2d..a74325abd877 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
 obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
 obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
 obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
+obj-$(CONFIG_PINCTRL_MT8516)	+= pinctrl-mt8516.o
 obj-$(CONFIG_PINCTRL_MT6397)	+= pinctrl-mt6397.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
new file mode 100644
index 000000000000..1e965f119eca
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Min.Guo <min.guo@mediatek.com>
+ */
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8516.h"
+
+static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
+	/* 0E4E8SR 4/8/12/16 */
+	MTK_DRV_GRP(4, 16, 1, 2, 4),
+	/* 0E2E4SR  2/4/6/8 */
+	MTK_DRV_GRP(2, 8, 1, 2, 2),
+	/* E8E4E2  2/4/6/8/10/12/14/16 */
+	MTK_DRV_GRP(2, 16, 0, 2, 2)
+};
+
+static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
+	MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
+	MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
+	MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
+	MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
+	MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
+
+	MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
+	MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
+	MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
+	MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
+	MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
+	MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
+
+	MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
+	MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
+	MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
+
+	MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
+	MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
+	MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
+	MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
+
+	MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
+	MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
+	MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
+
+	MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
+	MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
+	MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
+
+	MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
+	MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
+
+	MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
+	MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
+	MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
+	MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
+	MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
+
+	MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
+	MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
+	MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
+
+	MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
+	MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
+
+	MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
+	MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
+	MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
+	MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
+
+	MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
+
+	MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
+	MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
+	MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
+
+	MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
+	MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
+	MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
+	MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
+
+	MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
+	MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
+	MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
+	MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
+
+	MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
+
+	MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
+	MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
+	MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
+
+	MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
+	MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
+	MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
+	MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
+	MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
+	MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
+
+	MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
+
+	MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
+
+	MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
+	MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
+	MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
+	MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
+
+	MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
+	MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
+	MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
+	MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
+
+	MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
+
+	MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
+
+	MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
+	MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
+	MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
+	MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
+
+	MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
+	MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
+	MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
+	MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
+
+	MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
+
+	MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
+
+	MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
+
+	MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
+	MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
+	MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
+	MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
+};
+
+static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
+	MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
+	MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
+	MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
+	MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
+
+	MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
+	MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
+	MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
+
+	MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
+	MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
+	MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
+	MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
+
+	MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
+	MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
+	MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
+	MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
+	MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
+	MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
+
+	MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
+	MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
+	MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
+	MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
+	MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
+	MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
+	MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
+	MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
+	MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
+	MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
+	MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
+	MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
+	MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
+	MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
+	MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
+	MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
+	MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
+};
+
+static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
+			unsigned char align, bool isup, unsigned int r1r0)
+{
+	return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
+		ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
+}
+
+static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
+	MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
+	MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
+	MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
+	MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
+	MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
+	MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
+	MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
+	MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
+	MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
+	MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
+	MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
+	MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
+	MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
+	MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
+	MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
+	MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
+	MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
+	MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
+	MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
+	MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
+	MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
+	MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
+	MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
+	MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
+	MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
+	MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
+	MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
+	MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
+	MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
+	MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
+	MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
+	MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
+	MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
+	MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
+	MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
+	MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
+	MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
+	MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
+	MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
+	MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
+	MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
+	MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
+	MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
+	MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
+	MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
+	MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
+};
+
+static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
+	MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
+	MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
+	MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
+	MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
+	MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
+	MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
+	MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
+	MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
+	MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
+	MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
+	MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
+	MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
+	MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
+	MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
+	MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
+	MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
+	MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
+	MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
+	MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
+	MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
+	MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
+	MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
+	MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
+	MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
+	MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
+	MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
+	MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
+
+	MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
+	MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
+	MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
+	MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
+	MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
+	MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
+	MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
+	MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
+	MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
+	MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
+	MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
+	MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
+	MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
+	MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
+	MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
+	MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
+	MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
+	MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
+	MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
+};
+
+static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
+		unsigned char align, int value, enum pin_config_param arg)
+{
+	if (arg == PIN_CONFIG_INPUT_ENABLE)
+		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
+			ARRAY_SIZE(mt8516_ies_set), pin, align, value);
+	else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
+		return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
+			ARRAY_SIZE(mt8516_smt_set), pin, align, value);
+	return -EINVAL;
+}
+
+static struct mtk_eint_regs mt8516_eint_regs = {
+	.stat = 0x000,
+	.ack = 0x040,
+	.mask = 0x080,
+	.mask_set = 0x0c0,
+	.mask_clr = 0x100,
+	.sens = 0x140,
+	.sens_set = 0x180,
+	.sens_clr = 0x1c0,
+	.soft = 0x200,
+	.soft_set = 0x240,
+	.soft_clr = 0x280,
+	.pol = 0x300,
+	.pol_set = 0x340,
+	.pol_clr = 0x380,
+	.dom_en = 0x400,
+	.dbnc_ctrl = 0x500,
+	.dbnc_set = 0x600,
+	.dbnc_clr = 0x700,
+};
+
+static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
+	.pins = mtk_pins_mt8516,
+	.npins = ARRAY_SIZE(mtk_pins_mt8516),
+	.grp_desc = mt8516_drv_grp,
+	.n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
+	.pin_drv_grp = mt8516_pin_drv,
+	.n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
+	.spec_pull_set = mt8516_spec_pull_set,
+	.spec_ies_smt_set = mt8516_ies_smt_set,
+	.dir_offset = 0x0000,
+	.pullen_offset = 0x0500,
+	.pullsel_offset = 0x0600,
+	.dout_offset = 0x0100,
+	.din_offset = 0x0200,
+	.pinmux_offset = 0x0300,
+	.type1_start = 125,
+	.type1_end = 125,
+	.port_shf = 4,
+	.port_mask = 0xf,
+	.port_align = 4,
+	.eint_regs = &mt8516_eint_regs,
+	.eint_hw = {
+		.port_mask = 7,
+		.ports     = 6,
+		.ap_num    = 169,
+		.db_cnt    = 64,
+	},
+};
+
+static int mt8516_pinctrl_probe(struct platform_device *pdev)
+{
+	return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
+}
+
+static const struct of_device_id mt8516_pctrl_match[] = {
+	{
+		.compatible = "mediatek,mt8516-pinctrl",
+	},
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
+
+static struct platform_driver mtk_pinctrl_driver = {
+	.probe = mt8516_pinctrl_probe,
+	.driver = {
+		.name = "mediatek-mt8516-pinctrl",
+		.of_match_table = mt8516_pctrl_match,
+		.pm = &mtk_eint_pm_ops,
+	},
+};
+
+static int __init mtk_pinctrl_init(void)
+{
+	return platform_driver_register(&mtk_pinctrl_driver);
+}
+arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
new file mode 100644
index 000000000000..f7a4c6e4a026
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
@@ -0,0 +1,1182 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+#ifndef __PINCTRL_MTK_MT8516_H
+#define __PINCTRL_MTK_MT8516_H
+
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mtk-common.h"
+
+static const struct mtk_desc_pin mtk_pins_mt8516[] = {
+	MTK_PIN(
+		PINCTRL_PIN(0, "EINT0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 0),
+		MTK_FUNCTION(0, "GPIO0"),
+		MTK_FUNCTION(1, "PWM_B"),
+		MTK_FUNCTION(3, "I2S2_BCK"),
+		MTK_FUNCTION(4, "EXT_TXD0"),
+		MTK_FUNCTION(6, "SQICS"),
+		MTK_FUNCTION(7, "DBG_MON_A[6]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(1, "EINT1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 1),
+		MTK_FUNCTION(0, "GPIO1"),
+		MTK_FUNCTION(1, "PWM_C"),
+		MTK_FUNCTION(3, "I2S2_DI"),
+		MTK_FUNCTION(4, "EXT_TXD1"),
+		MTK_FUNCTION(5, "CONN_MCU_TDO"),
+		MTK_FUNCTION(6, "SQISO"),
+		MTK_FUNCTION(7, "DBG_MON_A[7]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(2, "EINT2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 2),
+		MTK_FUNCTION(0, "GPIO2"),
+		MTK_FUNCTION(1, "CLKM0"),
+		MTK_FUNCTION(3, "I2S2_LRCK"),
+		MTK_FUNCTION(4, "EXT_TXD2"),
+		MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
+		MTK_FUNCTION(6, "SQISI"),
+		MTK_FUNCTION(7, "DBG_MON_A[8]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(3, "EINT3"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 3),
+		MTK_FUNCTION(0, "GPIO3"),
+		MTK_FUNCTION(1, "CLKM1"),
+		MTK_FUNCTION(3, "SPI_MI"),
+		MTK_FUNCTION(4, "EXT_TXD3"),
+		MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
+		MTK_FUNCTION(6, "SQIWP"),
+		MTK_FUNCTION(7, "DBG_MON_A[9]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(4, "EINT4"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 4),
+		MTK_FUNCTION(0, "GPIO4"),
+		MTK_FUNCTION(1, "CLKM2"),
+		MTK_FUNCTION(3, "SPI_MO"),
+		MTK_FUNCTION(4, "EXT_TXC"),
+		MTK_FUNCTION(5, "CONN_MCU_TCK"),
+		MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"),
+		MTK_FUNCTION(7, "DBG_MON_A[10]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(5, "EINT5"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 5),
+		MTK_FUNCTION(0, "GPIO5"),
+		MTK_FUNCTION(1, "UCTS2"),
+		MTK_FUNCTION(3, "SPI_CSB"),
+		MTK_FUNCTION(4, "EXT_RXER"),
+		MTK_FUNCTION(5, "CONN_MCU_TDI"),
+		MTK_FUNCTION(6, "CONN_TEST_CK"),
+		MTK_FUNCTION(7, "DBG_MON_A[11]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(6, "EINT6"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 6),
+		MTK_FUNCTION(0, "GPIO6"),
+		MTK_FUNCTION(1, "URTS2"),
+		MTK_FUNCTION(3, "SPI_CLK"),
+		MTK_FUNCTION(4, "EXT_RXC"),
+		MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
+		MTK_FUNCTION(7, "DBG_MON_A[12]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(7, "EINT7"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 7),
+		MTK_FUNCTION(0, "GPIO7"),
+		MTK_FUNCTION(1, "SQIRST"),
+		MTK_FUNCTION(3, "SDA1_0"),
+		MTK_FUNCTION(4, "EXT_RXDV"),
+		MTK_FUNCTION(5, "CONN_MCU_TMS"),
+		MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"),
+		MTK_FUNCTION(7, "DBG_MON_A[13]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(8, "EINT8"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 8),
+		MTK_FUNCTION(0, "GPIO8"),
+		MTK_FUNCTION(1, "SQICK"),
+		MTK_FUNCTION(2, "CLKM3"),
+		MTK_FUNCTION(3, "SCL1_0"),
+		MTK_FUNCTION(4, "EXT_RXD0"),
+		MTK_FUNCTION(5, "ANT_SEL0"),
+		MTK_FUNCTION(7, "DBG_MON_A[14]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(9, "EINT9"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 9),
+		MTK_FUNCTION(0, "GPIO9"),
+		MTK_FUNCTION(1, "CLKM4"),
+		MTK_FUNCTION(2, "SDA2_0"),
+		MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+		MTK_FUNCTION(4, "EXT_RXD1"),
+		MTK_FUNCTION(5, "ANT_SEL1"),
+		MTK_FUNCTION(7, "DBG_MON_A[15]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(10, "EINT10"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 10),
+		MTK_FUNCTION(0, "GPIO10"),
+		MTK_FUNCTION(1, "CLKM5"),
+		MTK_FUNCTION(2, "SCL2_0"),
+		MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+		MTK_FUNCTION(4, "EXT_RXD2"),
+		MTK_FUNCTION(5, "ANT_SEL2"),
+		MTK_FUNCTION(7, "DBG_MON_A[16]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(11, "EINT11"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 11),
+		MTK_FUNCTION(0, "GPIO11"),
+		MTK_FUNCTION(1, "CLKM4"),
+		MTK_FUNCTION(2, "PWM_C"),
+		MTK_FUNCTION(3, "CONN_TEST_CK"),
+		MTK_FUNCTION(4, "ANT_SEL3"),
+		MTK_FUNCTION(6, "EXT_RXD3"),
+		MTK_FUNCTION(7, "DBG_MON_A[17]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(12, "EINT12"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 12),
+		MTK_FUNCTION(0, "GPIO12"),
+		MTK_FUNCTION(1, "CLKM5"),
+		MTK_FUNCTION(2, "PWM_A"),
+		MTK_FUNCTION(3, "SPDIF_OUT"),
+		MTK_FUNCTION(4, "ANT_SEL4"),
+		MTK_FUNCTION(6, "EXT_TXEN"),
+		MTK_FUNCTION(7, "DBG_MON_A[18]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(13, "EINT13"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 13),
+		MTK_FUNCTION(0, "GPIO13"),
+		MTK_FUNCTION(3, "TSF_IN"),
+		MTK_FUNCTION(4, "ANT_SEL5"),
+		MTK_FUNCTION(6, "SPDIF_IN"),
+		MTK_FUNCTION(7, "DBG_MON_A[19]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(14, "EINT14"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 14),
+		MTK_FUNCTION(0, "GPIO14"),
+		MTK_FUNCTION(2, "I2S_8CH_DO1"),
+		MTK_FUNCTION(3, "TDM_RX_MCK"),
+		MTK_FUNCTION(4, "ANT_SEL1"),
+		MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
+		MTK_FUNCTION(6, "NCLE"),
+		MTK_FUNCTION(7, "DBG_MON_B[8]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(15, "EINT15"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 15),
+		MTK_FUNCTION(0, "GPIO15"),
+		MTK_FUNCTION(2, "I2S_8CH_LRCK"),
+		MTK_FUNCTION(3, "TDM_RX_BCK"),
+		MTK_FUNCTION(4, "ANT_SEL2"),
+		MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
+		MTK_FUNCTION(6, "NCEB1"),
+		MTK_FUNCTION(7, "DBG_MON_B[9]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(16, "EINT16"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 16),
+		MTK_FUNCTION(0, "GPIO16"),
+		MTK_FUNCTION(2, "I2S_8CH_BCK"),
+		MTK_FUNCTION(3, "TDM_RX_LRCK"),
+		MTK_FUNCTION(4, "ANT_SEL3"),
+		MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
+		MTK_FUNCTION(6, "NCEB0"),
+		MTK_FUNCTION(7, "DBG_MON_B[10]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(17, "EINT17"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 17),
+		MTK_FUNCTION(0, "GPIO17"),
+		MTK_FUNCTION(2, "I2S_8CH_MCK"),
+		MTK_FUNCTION(3, "TDM_RX_DI"),
+		MTK_FUNCTION(4, "IDDIG"),
+		MTK_FUNCTION(5, "ANT_SEL4"),
+		MTK_FUNCTION(6, "NREB"),
+		MTK_FUNCTION(7, "DBG_MON_B[11]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(18, "EINT18"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 18),
+		MTK_FUNCTION(0, "GPIO18"),
+		MTK_FUNCTION(2, "USB_DRVVBUS"),
+		MTK_FUNCTION(3, "I2S3_LRCK"),
+		MTK_FUNCTION(4, "CLKM1"),
+		MTK_FUNCTION(5, "ANT_SEL3"),
+		MTK_FUNCTION(6, "I2S2_BCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[20]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(19, "EINT19"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 19),
+		MTK_FUNCTION(0, "GPIO19"),
+		MTK_FUNCTION(1, "UCTS1"),
+		MTK_FUNCTION(2, "IDDIG"),
+		MTK_FUNCTION(3, "I2S3_BCK"),
+		MTK_FUNCTION(4, "CLKM2"),
+		MTK_FUNCTION(5, "ANT_SEL4"),
+		MTK_FUNCTION(6, "I2S2_DI"),
+		MTK_FUNCTION(7, "DBG_MON_A[21]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(20, "EINT20"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 20),
+		MTK_FUNCTION(0, "GPIO20"),
+		MTK_FUNCTION(1, "URTS1"),
+		MTK_FUNCTION(3, "I2S3_DO"),
+		MTK_FUNCTION(4, "CLKM3"),
+		MTK_FUNCTION(5, "ANT_SEL5"),
+		MTK_FUNCTION(6, "I2S2_LRCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[22]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(21, "EINT21"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 21),
+		MTK_FUNCTION(0, "GPIO21"),
+		MTK_FUNCTION(1, "NRNB"),
+		MTK_FUNCTION(2, "ANT_SEL0"),
+		MTK_FUNCTION(3, "I2S_8CH_DO4"),
+		MTK_FUNCTION(7, "DBG_MON_B[31]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(22, "EINT22"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 22),
+		MTK_FUNCTION(0, "GPIO22"),
+		MTK_FUNCTION(2, "I2S_8CH_DO2"),
+		MTK_FUNCTION(3, "TSF_IN"),
+		MTK_FUNCTION(4, "USB_DRVVBUS"),
+		MTK_FUNCTION(5, "SPDIF_OUT"),
+		MTK_FUNCTION(6, "NRE_C"),
+		MTK_FUNCTION(7, "DBG_MON_B[12]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(23, "EINT23"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 23),
+		MTK_FUNCTION(0, "GPIO23"),
+		MTK_FUNCTION(2, "I2S_8CH_DO3"),
+		MTK_FUNCTION(3, "CLKM0"),
+		MTK_FUNCTION(4, "IR"),
+		MTK_FUNCTION(5, "SPDIF_IN"),
+		MTK_FUNCTION(6, "NDQS_C"),
+		MTK_FUNCTION(7, "DBG_MON_B[13]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(24, "EINT24"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 24),
+		MTK_FUNCTION(0, "GPIO24"),
+		MTK_FUNCTION(3, "ANT_SEL1"),
+		MTK_FUNCTION(4, "UCTS2"),
+		MTK_FUNCTION(5, "PWM_A"),
+		MTK_FUNCTION(6, "I2S0_MCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[0]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(25, "EINT25"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 25),
+		MTK_FUNCTION(0, "GPIO25"),
+		MTK_FUNCTION(3, "ANT_SEL0"),
+		MTK_FUNCTION(4, "URTS2"),
+		MTK_FUNCTION(5, "PWM_B"),
+		MTK_FUNCTION(6, "I2S_8CH_MCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[1]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(26, "PWRAP_SPI0_MI"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 26),
+		MTK_FUNCTION(0, "GPIO26"),
+		MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
+		MTK_FUNCTION(2, "PWRAP_SPI0_MI")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(27, "PWRAP_SPI0_MO"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 27),
+		MTK_FUNCTION(0, "GPIO27"),
+		MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
+		MTK_FUNCTION(2, "PWRAP_SPI0_MO")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(28, "PWRAP_INT"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 28),
+		MTK_FUNCTION(0, "GPIO28"),
+		MTK_FUNCTION(1, "I2S0_MCK"),
+		MTK_FUNCTION(4, "I2S_8CH_MCK"),
+		MTK_FUNCTION(5, "I2S2_MCK"),
+		MTK_FUNCTION(6, "I2S3_MCK")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(29, "PWRAP_SPI0_CK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 29),
+		MTK_FUNCTION(0, "GPIO29"),
+		MTK_FUNCTION(1, "PWRAP_SPI0_CK")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(30, "PWRAP_SPI0_CSN"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 30),
+		MTK_FUNCTION(0, "GPIO30"),
+		MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(31, "RTC32K_CK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 31),
+		MTK_FUNCTION(0, "GPIO31"),
+		MTK_FUNCTION(1, "RTC32K_CK")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(32, "WATCHDOG"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 32),
+		MTK_FUNCTION(0, "GPIO32"),
+		MTK_FUNCTION(1, "WATCHDOG")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(33, "SRCLKENA"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 33),
+		MTK_FUNCTION(0, "GPIO33"),
+		MTK_FUNCTION(1, "SRCLKENA0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(34, "URXD2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 34),
+		MTK_FUNCTION(0, "GPIO34"),
+		MTK_FUNCTION(1, "URXD2"),
+		MTK_FUNCTION(3, "UTXD2"),
+		MTK_FUNCTION(4, "DBG_SCL"),
+		MTK_FUNCTION(6, "I2S2_MCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[0]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(35, "UTXD2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 35),
+		MTK_FUNCTION(0, "GPIO35"),
+		MTK_FUNCTION(1, "UTXD2"),
+		MTK_FUNCTION(3, "URXD2"),
+		MTK_FUNCTION(4, "DBG_SDA"),
+		MTK_FUNCTION(6, "I2S3_MCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[1]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(36, "MRG_CLK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 36),
+		MTK_FUNCTION(0, "GPIO36"),
+		MTK_FUNCTION(1, "MRG_CLK"),
+		MTK_FUNCTION(3, "I2S0_BCK"),
+		MTK_FUNCTION(4, "I2S3_BCK"),
+		MTK_FUNCTION(5, "PCM0_CLK"),
+		MTK_FUNCTION(6, "IR"),
+		MTK_FUNCTION(7, "DBG_MON_A[2]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(37, "MRG_SYNC"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 37),
+		MTK_FUNCTION(0, "GPIO37"),
+		MTK_FUNCTION(1, "MRG_SYNC"),
+		MTK_FUNCTION(3, "I2S0_LRCK"),
+		MTK_FUNCTION(4, "I2S3_LRCK"),
+		MTK_FUNCTION(5, "PCM0_SYNC"),
+		MTK_FUNCTION(6, "EXT_COL"),
+		MTK_FUNCTION(7, "DBG_MON_A[3]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(38, "MRG_DI"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 38),
+		MTK_FUNCTION(0, "GPIO38"),
+		MTK_FUNCTION(1, "MRG_DI"),
+		MTK_FUNCTION(3, "I2S0_DI"),
+		MTK_FUNCTION(4, "I2S3_DO"),
+		MTK_FUNCTION(5, "PCM0_DI"),
+		MTK_FUNCTION(6, "EXT_MDIO"),
+		MTK_FUNCTION(7, "DBG_MON_A[4]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(39, "MRG_DO"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 39),
+		MTK_FUNCTION(0, "GPIO39"),
+		MTK_FUNCTION(1, "MRG_DO"),
+		MTK_FUNCTION(3, "I2S0_MCK"),
+		MTK_FUNCTION(4, "I2S3_MCK"),
+		MTK_FUNCTION(5, "PCM0_DO"),
+		MTK_FUNCTION(6, "EXT_MDC"),
+		MTK_FUNCTION(7, "DBG_MON_A[5]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(40, "KPROW0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 40),
+		MTK_FUNCTION(0, "GPIO40"),
+		MTK_FUNCTION(1, "KPROW0"),
+		MTK_FUNCTION(7, "DBG_MON_B[4]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(41, "KPROW1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 41),
+		MTK_FUNCTION(0, "GPIO41"),
+		MTK_FUNCTION(1, "KPROW1"),
+		MTK_FUNCTION(2, "IDDIG"),
+		MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+		MTK_FUNCTION(7, "DBG_MON_B[5]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(42, "KPCOL0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 42),
+		MTK_FUNCTION(0, "GPIO42"),
+		MTK_FUNCTION(1, "KPCOL0"),
+		MTK_FUNCTION(7, "DBG_MON_B[6]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(43, "KPCOL1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 43),
+		MTK_FUNCTION(0, "GPIO43"),
+		MTK_FUNCTION(1, "KPCOL1"),
+		MTK_FUNCTION(2, "USB_DRVVBUS"),
+		MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
+		MTK_FUNCTION(4, "TSF_IN"),
+		MTK_FUNCTION(7, "DBG_MON_B[7]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(44, "JTMS"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 44),
+		MTK_FUNCTION(0, "GPIO44"),
+		MTK_FUNCTION(1, "JTMS"),
+		MTK_FUNCTION(2, "CONN_MCU_TMS"),
+		MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(45, "JTCK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 45),
+		MTK_FUNCTION(0, "GPIO45"),
+		MTK_FUNCTION(1, "JTCK"),
+		MTK_FUNCTION(2, "CONN_MCU_TCK"),
+		MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(46, "JTDI"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 46),
+		MTK_FUNCTION(0, "GPIO46"),
+		MTK_FUNCTION(1, "JTDI"),
+		MTK_FUNCTION(2, "CONN_MCU_TDI")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(47, "JTDO"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 47),
+		MTK_FUNCTION(0, "GPIO47"),
+		MTK_FUNCTION(1, "JTDO"),
+		MTK_FUNCTION(2, "CONN_MCU_TDO")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(48, "SPI_CS"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 48),
+		MTK_FUNCTION(0, "GPIO48"),
+		MTK_FUNCTION(1, "SPI_CSB"),
+		MTK_FUNCTION(3, "I2S0_DI"),
+		MTK_FUNCTION(4, "I2S2_BCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[23]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(49, "SPI_CK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 49),
+		MTK_FUNCTION(0, "GPIO49"),
+		MTK_FUNCTION(1, "SPI_CLK"),
+		MTK_FUNCTION(3, "I2S0_LRCK"),
+		MTK_FUNCTION(4, "I2S2_DI"),
+		MTK_FUNCTION(7, "DBG_MON_A[24]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(50, "SPI_MI"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 50),
+		MTK_FUNCTION(0, "GPIO50"),
+		MTK_FUNCTION(1, "SPI_MI"),
+		MTK_FUNCTION(2, "SPI_MO"),
+		MTK_FUNCTION(3, "I2S0_BCK"),
+		MTK_FUNCTION(4, "I2S2_LRCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[25]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(51, "SPI_MO"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 51),
+		MTK_FUNCTION(0, "GPIO51"),
+		MTK_FUNCTION(1, "SPI_MO"),
+		MTK_FUNCTION(2, "SPI_MI"),
+		MTK_FUNCTION(3, "I2S0_MCK"),
+		MTK_FUNCTION(4, "I2S2_MCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[26]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(52, "SDA1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 52),
+		MTK_FUNCTION(0, "GPIO52"),
+		MTK_FUNCTION(1, "SDA1_0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(53, "SCL1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 53),
+		MTK_FUNCTION(0, "GPIO53"),
+		MTK_FUNCTION(1, "SCL1_0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(54, "GPIO54"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 54),
+		MTK_FUNCTION(0, "GPIO54"),
+		MTK_FUNCTION(2, "PWM_B"),
+		MTK_FUNCTION(7, "DBG_MON_B[2]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(55, "I2S_DATA_IN"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 55),
+		MTK_FUNCTION(0, "GPIO55"),
+		MTK_FUNCTION(1, "I2S0_DI"),
+		MTK_FUNCTION(2, "UCTS0"),
+		MTK_FUNCTION(3, "I2S3_DO"),
+		MTK_FUNCTION(4, "I2S_8CH_DO1"),
+		MTK_FUNCTION(5, "PWM_A"),
+		MTK_FUNCTION(6, "I2S2_BCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[28]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(56, "I2S_LRCK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 56),
+		MTK_FUNCTION(0, "GPIO56"),
+		MTK_FUNCTION(1, "I2S0_LRCK"),
+		MTK_FUNCTION(3, "I2S3_LRCK"),
+		MTK_FUNCTION(4, "I2S_8CH_LRCK"),
+		MTK_FUNCTION(5, "PWM_B"),
+		MTK_FUNCTION(6, "I2S2_DI"),
+		MTK_FUNCTION(7, "DBG_MON_A[29]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(57, "I2S_BCK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 57),
+		MTK_FUNCTION(0, "GPIO57"),
+		MTK_FUNCTION(1, "I2S0_BCK"),
+		MTK_FUNCTION(2, "URTS0"),
+		MTK_FUNCTION(3, "I2S3_BCK"),
+		MTK_FUNCTION(4, "I2S_8CH_BCK"),
+		MTK_FUNCTION(5, "PWM_C"),
+		MTK_FUNCTION(6, "I2S2_LRCK"),
+		MTK_FUNCTION(7, "DBG_MON_A[30]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(58, "SDA0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 58),
+		MTK_FUNCTION(0, "GPIO58"),
+		MTK_FUNCTION(1, "SDA0_0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(59, "SCL0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 59),
+		MTK_FUNCTION(0, "GPIO59"),
+		MTK_FUNCTION(1, "SCL0_0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(60, "SDA2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 60),
+		MTK_FUNCTION(0, "GPIO60"),
+		MTK_FUNCTION(1, "SDA2_0"),
+		MTK_FUNCTION(2, "PWM_B")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(61, "SCL2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 61),
+		MTK_FUNCTION(0, "GPIO61"),
+		MTK_FUNCTION(1, "SCL2_0"),
+		MTK_FUNCTION(2, "PWM_C")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(62, "URXD0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 62),
+		MTK_FUNCTION(0, "GPIO62"),
+		MTK_FUNCTION(1, "URXD0"),
+		MTK_FUNCTION(2, "UTXD0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(63, "UTXD0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 63),
+		MTK_FUNCTION(0, "GPIO63"),
+		MTK_FUNCTION(1, "UTXD0"),
+		MTK_FUNCTION(2, "URXD0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(64, "URXD1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 64),
+		MTK_FUNCTION(0, "GPIO64"),
+		MTK_FUNCTION(1, "URXD1"),
+		MTK_FUNCTION(2, "UTXD1"),
+		MTK_FUNCTION(7, "DBG_MON_A[27]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(65, "UTXD1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 65),
+		MTK_FUNCTION(0, "GPIO65"),
+		MTK_FUNCTION(1, "UTXD1"),
+		MTK_FUNCTION(2, "URXD1"),
+		MTK_FUNCTION(7, "DBG_MON_A[31]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(66, "LCM_RST"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 66),
+		MTK_FUNCTION(0, "GPIO66"),
+		MTK_FUNCTION(1, "LCM_RST"),
+		MTK_FUNCTION(3, "I2S0_MCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[3]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(67, "GPIO67"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 67),
+		MTK_FUNCTION(0, "GPIO67"),
+		MTK_FUNCTION(3, "I2S_8CH_MCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[14]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(68, "MSDC2_CMD"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 68),
+		MTK_FUNCTION(0, "GPIO68"),
+		MTK_FUNCTION(1, "MSDC2_CMD"),
+		MTK_FUNCTION(2, "I2S_8CH_DO4"),
+		MTK_FUNCTION(3, "SDA1_0"),
+		MTK_FUNCTION(5, "USB_SDA"),
+		MTK_FUNCTION(6, "I2S3_BCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[15]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(69, "MSDC2_CLK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 69),
+		MTK_FUNCTION(0, "GPIO69"),
+		MTK_FUNCTION(1, "MSDC2_CLK"),
+		MTK_FUNCTION(2, "I2S_8CH_DO3"),
+		MTK_FUNCTION(3, "SCL1_0"),
+		MTK_FUNCTION(5, "USB_SCL"),
+		MTK_FUNCTION(6, "I2S3_LRCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[16]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(70, "MSDC2_DAT0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 70),
+		MTK_FUNCTION(0, "GPIO70"),
+		MTK_FUNCTION(1, "MSDC2_DAT0"),
+		MTK_FUNCTION(2, "I2S_8CH_DO2"),
+		MTK_FUNCTION(5, "UTXD0"),
+		MTK_FUNCTION(6, "I2S3_DO"),
+		MTK_FUNCTION(7, "DBG_MON_B[17]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(71, "MSDC2_DAT1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 71),
+		MTK_FUNCTION(0, "GPIO71"),
+		MTK_FUNCTION(1, "MSDC2_DAT1"),
+		MTK_FUNCTION(2, "I2S_8CH_DO1"),
+		MTK_FUNCTION(3, "PWM_A"),
+		MTK_FUNCTION(4, "I2S3_MCK"),
+		MTK_FUNCTION(5, "URXD0"),
+		MTK_FUNCTION(6, "PWM_B"),
+		MTK_FUNCTION(7, "DBG_MON_B[18]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(72, "MSDC2_DAT2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 72),
+		MTK_FUNCTION(0, "GPIO72"),
+		MTK_FUNCTION(1, "MSDC2_DAT2"),
+		MTK_FUNCTION(2, "I2S_8CH_LRCK"),
+		MTK_FUNCTION(3, "SDA2_0"),
+		MTK_FUNCTION(5, "UTXD1"),
+		MTK_FUNCTION(6, "PWM_C"),
+		MTK_FUNCTION(7, "DBG_MON_B[19]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(73, "MSDC2_DAT3"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 73),
+		MTK_FUNCTION(0, "GPIO73"),
+		MTK_FUNCTION(1, "MSDC2_DAT3"),
+		MTK_FUNCTION(2, "I2S_8CH_BCK"),
+		MTK_FUNCTION(3, "SCL2_0"),
+		MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
+		MTK_FUNCTION(5, "URXD1"),
+		MTK_FUNCTION(6, "PWM_A"),
+		MTK_FUNCTION(7, "DBG_MON_B[20]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(74, "TDN3"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 74),
+		MTK_FUNCTION(0, "GPIO74"),
+		MTK_FUNCTION(1, "TDN3")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(75, "TDP3"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 75),
+		MTK_FUNCTION(0, "GPIO75"),
+		MTK_FUNCTION(1, "TDP3")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(76, "TDN2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 76),
+		MTK_FUNCTION(0, "GPIO76"),
+		MTK_FUNCTION(1, "TDN2")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(77, "TDP2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 77),
+		MTK_FUNCTION(0, "GPIO77"),
+		MTK_FUNCTION(1, "TDP2")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(78, "TCN"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 78),
+		MTK_FUNCTION(0, "GPIO78"),
+		MTK_FUNCTION(1, "TCN")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(79, "TCP"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 79),
+		MTK_FUNCTION(0, "GPIO79"),
+		MTK_FUNCTION(1, "TCP")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(80, "TDN1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 80),
+		MTK_FUNCTION(0, "GPIO80"),
+		MTK_FUNCTION(1, "TDN1")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(81, "TDP1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 81),
+		MTK_FUNCTION(0, "GPIO81"),
+		MTK_FUNCTION(1, "TDP1")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(82, "TDN0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 82),
+		MTK_FUNCTION(0, "GPIO82"),
+		MTK_FUNCTION(1, "TDN0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(83, "TDP0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 83),
+		MTK_FUNCTION(0, "GPIO83"),
+		MTK_FUNCTION(1, "TDP0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(84, "RDN0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 84),
+		MTK_FUNCTION(0, "GPIO84"),
+		MTK_FUNCTION(1, "RDN0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(85, "RDP0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 85),
+		MTK_FUNCTION(0, "GPIO85"),
+		MTK_FUNCTION(1, "RDP0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(86, "RDN1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 86),
+		MTK_FUNCTION(0, "GPIO86"),
+		MTK_FUNCTION(1, "RDN1")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(87, "RDP1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 87),
+		MTK_FUNCTION(0, "GPIO87"),
+		MTK_FUNCTION(1, "RDP1")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(88, "RCN"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 88),
+		MTK_FUNCTION(0, "GPIO88"),
+		MTK_FUNCTION(1, "RCN")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(89, "RCP"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 89),
+		MTK_FUNCTION(0, "GPIO89"),
+		MTK_FUNCTION(1, "RCP")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(90, "RDN2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 90),
+		MTK_FUNCTION(0, "GPIO90"),
+		MTK_FUNCTION(1, "RDN2"),
+		MTK_FUNCTION(2, "CMDAT8")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(91, "RDP2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 91),
+		MTK_FUNCTION(0, "GPIO91"),
+		MTK_FUNCTION(1, "RDP2"),
+		MTK_FUNCTION(2, "CMDAT9")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(92, "RDN3"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 92),
+		MTK_FUNCTION(0, "GPIO92"),
+		MTK_FUNCTION(1, "RDN3"),
+		MTK_FUNCTION(2, "CMDAT4")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(93, "RDP3"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 93),
+		MTK_FUNCTION(0, "GPIO93"),
+		MTK_FUNCTION(1, "RDP3"),
+		MTK_FUNCTION(2, "CMDAT5")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(94, "RCN_A"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 94),
+		MTK_FUNCTION(0, "GPIO94"),
+		MTK_FUNCTION(1, "RCN_A"),
+		MTK_FUNCTION(2, "CMDAT6")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(95, "RCP_A"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 95),
+		MTK_FUNCTION(0, "GPIO95"),
+		MTK_FUNCTION(1, "RCP_A"),
+		MTK_FUNCTION(2, "CMDAT7")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(96, "RDN1_A"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 96),
+		MTK_FUNCTION(0, "GPIO96"),
+		MTK_FUNCTION(1, "RDN1_A"),
+		MTK_FUNCTION(2, "CMDAT2"),
+		MTK_FUNCTION(3, "CMCSD2")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(97, "RDP1_A"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 97),
+		MTK_FUNCTION(0, "GPIO97"),
+		MTK_FUNCTION(1, "RDP1_A"),
+		MTK_FUNCTION(2, "CMDAT3"),
+		MTK_FUNCTION(3, "CMCSD3")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(98, "RDN0_A"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 98),
+		MTK_FUNCTION(0, "GPIO98"),
+		MTK_FUNCTION(1, "RDN0_A"),
+		MTK_FUNCTION(2, "CMHSYNC")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(99, "RDP0_A"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 99),
+		MTK_FUNCTION(0, "GPIO99"),
+		MTK_FUNCTION(1, "RDP0_A"),
+		MTK_FUNCTION(2, "CMVSYNC")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(100, "CMDAT0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 100),
+		MTK_FUNCTION(0, "GPIO100"),
+		MTK_FUNCTION(1, "CMDAT0"),
+		MTK_FUNCTION(2, "CMCSD0"),
+		MTK_FUNCTION(3, "ANT_SEL2"),
+		MTK_FUNCTION(5, "TDM_RX_MCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[21]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(101, "CMDAT1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 101),
+		MTK_FUNCTION(0, "GPIO101"),
+		MTK_FUNCTION(1, "CMDAT1"),
+		MTK_FUNCTION(2, "CMCSD1"),
+		MTK_FUNCTION(3, "ANT_SEL3"),
+		MTK_FUNCTION(4, "CMFLASH"),
+		MTK_FUNCTION(5, "TDM_RX_BCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[22]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(102, "CMMCLK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 102),
+		MTK_FUNCTION(0, "GPIO102"),
+		MTK_FUNCTION(1, "CMMCLK"),
+		MTK_FUNCTION(3, "ANT_SEL4"),
+		MTK_FUNCTION(5, "TDM_RX_LRCK"),
+		MTK_FUNCTION(7, "DBG_MON_B[23]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(103, "CMPCLK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 103),
+		MTK_FUNCTION(0, "GPIO103"),
+		MTK_FUNCTION(1, "CMPCLK"),
+		MTK_FUNCTION(2, "CMCSK"),
+		MTK_FUNCTION(3, "ANT_SEL5"),
+		MTK_FUNCTION(5, " TDM_RX_DI"),
+		MTK_FUNCTION(7, "DBG_MON_B[24]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(104, "MSDC1_CMD"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 104),
+		MTK_FUNCTION(0, "GPIO104"),
+		MTK_FUNCTION(1, "MSDC1_CMD"),
+		MTK_FUNCTION(4, "SQICS"),
+		MTK_FUNCTION(7, "DBG_MON_B[25]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(105, "MSDC1_CLK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 105),
+		MTK_FUNCTION(0, "GPIO105"),
+		MTK_FUNCTION(1, "MSDC1_CLK"),
+		MTK_FUNCTION(4, "SQISO"),
+		MTK_FUNCTION(7, "DBG_MON_B[26]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(106, "MSDC1_DAT0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 106),
+		MTK_FUNCTION(0, "GPIO106"),
+		MTK_FUNCTION(1, "MSDC1_DAT0"),
+		MTK_FUNCTION(4, "SQISI"),
+		MTK_FUNCTION(7, "DBG_MON_B[27]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(107, "MSDC1_DAT1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 107),
+		MTK_FUNCTION(0, "GPIO107"),
+		MTK_FUNCTION(1, "MSDC1_DAT1"),
+		MTK_FUNCTION(4, "SQIWP"),
+		MTK_FUNCTION(7, "DBG_MON_B[28]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(108, "MSDC1_DAT2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 108),
+		MTK_FUNCTION(0, "GPIO108"),
+		MTK_FUNCTION(1, "MSDC1_DAT2"),
+		MTK_FUNCTION(4, "SQIRST"),
+		MTK_FUNCTION(7, "DBG_MON_B[29]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(109, "MSDC1_DAT3"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 109),
+		MTK_FUNCTION(0, "GPIO109"),
+		MTK_FUNCTION(1, "MSDC1_DAT3"),
+		MTK_FUNCTION(4, "SQICK"), /* WIP */
+		MTK_FUNCTION(7, "DBG_MON_B[30]")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(110, "MSDC0_DAT7"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 110),
+		MTK_FUNCTION(0, "GPIO110"),
+		MTK_FUNCTION(1, "MSDC0_DAT7"),
+		MTK_FUNCTION(4, "NLD7")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(111, "MSDC0_DAT6"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 111),
+		MTK_FUNCTION(0, "GPIO111"),
+		MTK_FUNCTION(1, "MSDC0_DAT6"),
+		MTK_FUNCTION(4, "NLD6")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(112, "MSDC0_DAT5"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 112),
+		MTK_FUNCTION(0, "GPIO112"),
+		MTK_FUNCTION(1, "MSDC0_DAT5"),
+		MTK_FUNCTION(4, "NLD4")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(113, "MSDC0_DAT4"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 113),
+		MTK_FUNCTION(0, "GPIO113"),
+		MTK_FUNCTION(1, "MSDC0_DAT4"),
+		MTK_FUNCTION(4, "NLD3")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(114, "MSDC0_RSTB"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 114),
+		MTK_FUNCTION(0, "GPIO114"),
+		MTK_FUNCTION(1, "MSDC0_RSTB"),
+		MTK_FUNCTION(4, "NLD0")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(115, "MSDC0_CMD"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 115),
+		MTK_FUNCTION(0, "GPIO115"),
+		MTK_FUNCTION(1, "MSDC0_CMD"),
+		MTK_FUNCTION(4, "NALE")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(116, "MSDC0_CLK"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 116),
+		MTK_FUNCTION(0, "GPIO116"),
+		MTK_FUNCTION(1, "MSDC0_CLK"),
+		MTK_FUNCTION(4, "NWEB")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(117, "MSDC0_DAT3"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 117),
+		MTK_FUNCTION(0, "GPIO117"),
+		MTK_FUNCTION(1, "MSDC0_DAT3"),
+		MTK_FUNCTION(4, "NLD1")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(118, "MSDC0_DAT2"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 118),
+		MTK_FUNCTION(0, "GPIO118"),
+		MTK_FUNCTION(1, "MSDC0_DAT2"),
+		MTK_FUNCTION(4, "NLD5")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(119, "MSDC0_DAT1"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 119),
+		MTK_FUNCTION(0, "GPIO119"),
+		MTK_FUNCTION(1, "MSDC0_DAT1"),
+		MTK_FUNCTION(4, "NLD8")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(120, "MSDC0_DAT0"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 120),
+		MTK_FUNCTION(0, "GPIO120"),
+		MTK_FUNCTION(1, "MSDC0_DAT0"),
+		MTK_FUNCTION(4, "WATCHDOG"),
+		MTK_FUNCTION(5, "NLD2")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(121, "GPIO121"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 121),
+		MTK_FUNCTION(0, "GPIO121")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(122, "GPIO122"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 122),
+		MTK_FUNCTION(0, "GPIO122")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(123, "GPIO123"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 123),
+		MTK_FUNCTION(0, "GPIO123")
+	),
+	MTK_PIN(
+		PINCTRL_PIN(124, "GPIO124"),
+		NULL, "mt8516",
+		MTK_EINT_FUNCTION(0, 124),
+		MTK_FUNCTION(0, "GPIO124")
+	),
+};
+
+#endif /* __PINCTRL_MTK_MT8516_H */
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 17/24] dt-bindings: wdog: mtk-wdt: add support for MT851
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (15 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 16/24] pinctrl: mediatek: Add MT8516 Pinctrl driver Fabien Parent
@ 2019-03-23 21:16 ` Fabien Parent
  2019-03-24 15:13   ` Guenter Roeck
  2019-03-28 19:13   ` Rob Herring
  2019-03-23 21:16 ` [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516 Fabien Parent
                   ` (6 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of mtk-wdt for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 8682d6a93e5b..fd380eb28df5 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -9,6 +9,7 @@ Required properties:
 	"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
 	"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
 	"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
+	"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
 
 - reg : Specifies base physical address and size of the registers.
 
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (16 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 17/24] dt-bindings: wdog: mtk-wdt: add support for MT851 Fabien Parent
@ 2019-03-23 21:16 ` Fabien Parent
  2019-03-28 19:12   ` Rob Herring
  2019-04-16  7:54   ` Matthias Brugger
  2019-03-23 21:16 ` [PATCH 19/24] dt-bindings: spi: spi-mt65xx: " Fabien Parent
                   ` (5 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of mtk-timer for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index ff7c567a7972..74c3eadad844 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -17,6 +17,7 @@ Required properties:
 	* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
 	* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
 	* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
+	* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
 	* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
 
 	For those SoCs that use SYST
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (17 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516 Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-03-28 19:12   ` Rob Herring
  2019-04-16  7:55   ` Matthias Brugger
  2019-03-23 21:16 ` [PATCH 20/24] dt-bindings: serial: mtk-uart: " Fabien Parent
                   ` (4 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of spi-mt65xx for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
index 69c356767cf8..69ac5976b952 100644
--- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
+++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
@@ -10,6 +10,7 @@ Required properties:
     - mediatek,mt8135-spi: for mt8135 platforms
     - mediatek,mt8173-spi: for mt8173 platforms
     - mediatek,mt8183-spi: for mt8183 platforms
+    - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
 
 - #address-cells: should be 1.
 
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 20/24] dt-bindings: serial: mtk-uart: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (18 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 19/24] dt-bindings: spi: spi-mt65xx: " Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-03-28 19:12   ` Rob Herring
  2019-04-16  7:56   ` Matthias Brugger
  2019-03-23 21:16 ` [PATCH 21/24] dt-bindings: irq: mtk,sysirq: " Fabien Parent
                   ` (3 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of mtk-uart for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 742cb470595b..1af981f7a33b 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -16,6 +16,7 @@ Required properties:
   * "mediatek,mt8127-uart" for MT8127 compatible UARTS
   * "mediatek,mt8135-uart" for MT8135 compatible UARTS
   * "mediatek,mt8173-uart" for MT8173 compatible UARTS
+  * "mediatek,mt8516-uart" for MT8516 compatible UARTS
   * "mediatek,mt6577-uart" for MT6577 and all of the above
 
 - reg: The base address of the UART register bank.
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 21/24] dt-bindings: irq: mtk,sysirq: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (19 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 20/24] dt-bindings: serial: mtk-uart: " Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-03-28 19:13   ` Rob Herring
  2019-04-16  7:57   ` Matthias Brugger
  2019-03-23 21:16 ` [PATCH 22/24] dt-bindings: i2c: i2c-mtk: " Fabien Parent
                   ` (2 subsequent siblings)
  23 siblings, 2 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of mediatek,sysirq for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 .../bindings/interrupt-controller/mediatek,sysirq.txt          | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index c5d589108a94..deaaba70d548 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -1,10 +1,11 @@
-+Mediatek MT65xx/MT67xx/MT81xx sysirq
++Mediatek MT65xx/MT67xx/MT81xx/MT85xx sysirq
 
 Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
 interrupt.
 
 Required properties:
 - compatible: should be
+	"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
 	"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
 	"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
 	"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (20 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 21/24] dt-bindings: irq: mtk,sysirq: " Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-03-28 19:13   ` Rob Herring
                     ` (2 more replies)
  2019-03-23 21:16 ` [PATCH 23/24] arm64: dts: mediatek: add dtsi " Fabien Parent
  2019-03-23 21:16 ` [PATCH 24/24] arm64: dts: mediatek: add pumpkin board dts Fabien Parent
  23 siblings, 3 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Add binding documentation of i2c-mtk for MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
index ee4c32454198..aac7b56f251f 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
@@ -12,6 +12,7 @@ Required properties:
       "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
       "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
       "mediatek,mt8173-i2c": for MediaTek MT8173
+      "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
   - reg: physical base address of the controller and dma base, length of memory
     mapped region.
   - interrupts: interrupt number to the cpu.
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 23/24] arm64: dts: mediatek: add dtsi for MT8516
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (21 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 22/24] dt-bindings: i2c: i2c-mtk: " Fabien Parent
@ 2019-03-23 21:16 ` " Fabien Parent
  2019-03-28 19:22   ` Rob Herring
  2019-03-23 21:16 ` [PATCH 24/24] arm64: dts: mediatek: add pumpkin board dts Fabien Parent
  23 siblings, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

The MT8516 SoC provides the following peripherals: GPIO, UART, USB2,
SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, Timers, IR, Ethernet, and
Audio (I2S, SPDIF, TDM).

This commit is adding the basic dtsi file with the support of the
following IOs: GPIO, UART, SPI, eMMC, I2C, Timers.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h | 663 ++++++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8516.dtsi      | 409 +++++++++++
 2 files changed, 1072 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8516.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h
new file mode 100644
index 000000000000..73339bb48f0d
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h
@@ -0,0 +1,663 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+#ifndef __DTS_MT8516_PINFUNC_H
+#define __DTS_MT8516_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT8516_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT8516_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1)
+#define MT8516_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)
+#define MT8516_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)
+#define MT8516_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6)
+#define MT8516_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7)
+
+#define MT8516_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT8516_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1)
+#define MT8516_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3)
+#define MT8516_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)
+#define MT8516_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5)
+#define MT8516_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6)
+#define MT8516_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7)
+
+#define MT8516_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT8516_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1)
+#define MT8516_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3)
+#define MT8516_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)
+#define MT8516_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5)
+#define MT8516_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6)
+#define MT8516_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7)
+
+#define MT8516_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT8516_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1)
+#define MT8516_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3)
+#define MT8516_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)
+#define MT8516_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5)
+#define MT8516_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6)
+#define MT8516_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7)
+
+#define MT8516_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT8516_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1)
+#define MT8516_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3)
+#define MT8516_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)
+#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5)
+#define MT8516_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6)
+#define MT8516_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7)
+
+#define MT8516_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT8516_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1)
+#define MT8516_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3)
+#define MT8516_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)
+#define MT8516_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5)
+#define MT8516_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6)
+#define MT8516_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7)
+
+#define MT8516_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT8516_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1)
+#define MT8516_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3)
+#define MT8516_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)
+#define MT8516_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5)
+#define MT8516_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7)
+
+#define MT8516_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT8516_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1)
+#define MT8516_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3)
+#define MT8516_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)
+#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5)
+#define MT8516_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6)
+#define MT8516_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7)
+
+#define MT8516_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT8516_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1)
+#define MT8516_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2)
+#define MT8516_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3)
+#define MT8516_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)
+#define MT8516_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5)
+#define MT8516_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7)
+
+#define MT8516_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT8516_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1)
+#define MT8516_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2)
+#define MT8516_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
+#define MT8516_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)
+#define MT8516_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5)
+#define MT8516_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7)
+
+#define MT8516_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT8516_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1)
+#define MT8516_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2)
+#define MT8516_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3)
+#define MT8516_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)
+#define MT8516_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5)
+#define MT8516_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7)
+
+#define MT8516_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT8516_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1)
+#define MT8516_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2)
+#define MT8516_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3)
+#define MT8516_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4)
+#define MT8516_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6)
+#define MT8516_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7)
+
+#define MT8516_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT8516_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1)
+#define MT8516_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2)
+#define MT8516_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3)
+#define MT8516_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4)
+#define MT8516_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6)
+#define MT8516_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7)
+
+#define MT8516_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT8516_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3)
+#define MT8516_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4)
+#define MT8516_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6)
+#define MT8516_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7)
+
+#define MT8516_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT8516_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2)
+#define MT8516_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3)
+#define MT8516_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4)
+#define MT8516_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5)
+#define MT8516_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6)
+#define MT8516_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7)
+
+#define MT8516_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT8516_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2)
+#define MT8516_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3)
+#define MT8516_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4)
+#define MT8516_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5)
+#define MT8516_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6)
+#define MT8516_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7)
+
+#define MT8516_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define MT8516_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2)
+#define MT8516_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3)
+#define MT8516_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4)
+#define MT8516_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5)
+#define MT8516_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6)
+#define MT8516_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7)
+
+#define MT8516_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define MT8516_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2)
+#define MT8516_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3)
+#define MT8516_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4)
+#define MT8516_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5)
+#define MT8516_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6)
+#define MT8516_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7)
+
+#define MT8516_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT8516_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2)
+#define MT8516_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3)
+#define MT8516_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4)
+#define MT8516_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5)
+#define MT8516_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6)
+#define MT8516_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7)
+
+#define MT8516_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT8516_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1)
+#define MT8516_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2)
+#define MT8516_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3)
+#define MT8516_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4)
+#define MT8516_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5)
+#define MT8516_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6)
+#define MT8516_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7)
+
+#define MT8516_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT8516_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1)
+#define MT8516_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3)
+#define MT8516_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4)
+#define MT8516_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5)
+#define MT8516_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6)
+#define MT8516_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7)
+
+#define MT8516_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT8516_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1)
+#define MT8516_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2)
+#define MT8516_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3)
+#define MT8516_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7)
+
+#define MT8516_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT8516_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2)
+#define MT8516_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3)
+#define MT8516_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4)
+#define MT8516_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5)
+#define MT8516_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6)
+#define MT8516_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7)
+
+#define MT8516_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT8516_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2)
+#define MT8516_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3)
+#define MT8516_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4)
+#define MT8516_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5)
+#define MT8516_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6)
+#define MT8516_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7)
+
+#define MT8516_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT8516_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3)
+#define MT8516_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4)
+#define MT8516_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5)
+#define MT8516_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6)
+#define MT8516_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7)
+
+#define MT8516_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT8516_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3)
+#define MT8516_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4)
+#define MT8516_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5)
+#define MT8516_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6)
+#define MT8516_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7)
+
+#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1)
+#define MT8516_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2)
+
+#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1)
+#define MT8516_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2)
+
+#define MT8516_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1)
+#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4)
+#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5)
+#define MT8516_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6)
+
+#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT8516_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1)
+
+#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define MT8516_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1)
+
+#define MT8516_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define MT8516_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1)
+
+#define MT8516_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define MT8516_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1)
+
+#define MT8516_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT8516_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1)
+
+#define MT8516_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT8516_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1)
+#define MT8516_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3)
+#define MT8516_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4)
+#define MT8516_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6)
+#define MT8516_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7)
+
+#define MT8516_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT8516_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1)
+#define MT8516_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3)
+#define MT8516_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4)
+#define MT8516_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6)
+#define MT8516_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7)
+
+#define MT8516_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT8516_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1)
+#define MT8516_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3)
+#define MT8516_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4)
+#define MT8516_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5)
+#define MT8516_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6)
+#define MT8516_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7)
+
+#define MT8516_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT8516_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1)
+#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3)
+#define MT8516_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4)
+#define MT8516_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5)
+#define MT8516_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6)
+#define MT8516_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7)
+
+#define MT8516_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define MT8516_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1)
+#define MT8516_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3)
+#define MT8516_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4)
+#define MT8516_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5)
+#define MT8516_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6)
+#define MT8516_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7)
+
+#define MT8516_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT8516_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1)
+#define MT8516_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3)
+#define MT8516_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4)
+#define MT8516_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5)
+#define MT8516_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6)
+#define MT8516_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7)
+
+#define MT8516_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT8516_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1)
+#define MT8516_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7)
+
+#define MT8516_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT8516_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1)
+#define MT8516_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2)
+#define MT8516_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3)
+#define MT8516_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7)
+
+#define MT8516_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT8516_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1)
+#define MT8516_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7)
+
+#define MT8516_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT8516_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1)
+#define MT8516_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2)
+#define MT8516_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3)
+#define MT8516_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4)
+#define MT8516_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7)
+
+#define MT8516_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT8516_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1)
+#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2)
+#define MT8516_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3)
+#define MT8516_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5)
+#define MT8516_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6)
+
+#define MT8516_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT8516_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1)
+#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2)
+#define MT8516_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3)
+
+#define MT8516_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT8516_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1)
+#define MT8516_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2)
+
+#define MT8516_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT8516_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1)
+#define MT8516_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2)
+
+#define MT8516_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT8516_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1)
+#define MT8516_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3)
+#define MT8516_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4)
+#define MT8516_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7)
+
+#define MT8516_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT8516_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1)
+#define MT8516_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3)
+#define MT8516_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4)
+#define MT8516_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7)
+
+#define MT8516_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1)
+#define MT8516_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2)
+#define MT8516_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3)
+#define MT8516_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4)
+#define MT8516_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7)
+
+#define MT8516_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1)
+#define MT8516_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2)
+#define MT8516_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3)
+#define MT8516_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4)
+#define MT8516_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7)
+
+#define MT8516_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define MT8516_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1)
+
+#define MT8516_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT8516_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1)
+
+#define MT8516_PIN_54_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT8516_PIN_54_GPIO54__FUNC_PWM_B (MTK_PIN_NO(54) | 2)
+#define MT8516_PIN_54_GPIO54__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7)
+
+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1)
+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2)
+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3)
+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4)
+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5)
+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6)
+#define MT8516_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7)
+
+#define MT8516_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1)
+#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3)
+#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4)
+#define MT8516_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5)
+#define MT8516_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6)
+#define MT8516_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7)
+
+#define MT8516_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT8516_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1)
+#define MT8516_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2)
+#define MT8516_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3)
+#define MT8516_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4)
+#define MT8516_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5)
+#define MT8516_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6)
+#define MT8516_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7)
+
+#define MT8516_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT8516_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1)
+
+#define MT8516_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define MT8516_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1)
+
+#define MT8516_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT8516_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1)
+#define MT8516_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2)
+
+#define MT8516_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT8516_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1)
+#define MT8516_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2)
+
+#define MT8516_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT8516_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1)
+#define MT8516_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2)
+
+#define MT8516_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT8516_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1)
+#define MT8516_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2)
+
+#define MT8516_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT8516_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1)
+#define MT8516_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2)
+#define MT8516_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7)
+
+#define MT8516_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT8516_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1)
+#define MT8516_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2)
+#define MT8516_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7)
+
+#define MT8516_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT8516_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1)
+#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2)
+#define MT8516_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3)
+#define MT8516_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5)
+#define MT8516_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6)
+#define MT8516_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7)
+
+#define MT8516_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT8516_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1)
+#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2)
+#define MT8516_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3)
+#define MT8516_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5)
+#define MT8516_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6)
+#define MT8516_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7)
+
+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1)
+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2)
+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5)
+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6)
+#define MT8516_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7)
+
+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1)
+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2)
+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3)
+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4)
+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5)
+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6)
+#define MT8516_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7)
+
+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1)
+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2)
+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3)
+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5)
+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6)
+#define MT8516_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7)
+
+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1)
+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2)
+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3)
+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4)
+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5)
+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6)
+#define MT8516_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7)
+
+#define MT8516_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0)
+#define MT8516_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1)
+
+#define MT8516_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0)
+#define MT8516_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1)
+
+#define MT8516_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0)
+#define MT8516_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1)
+
+#define MT8516_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0)
+#define MT8516_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1)
+
+#define MT8516_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0)
+#define MT8516_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1)
+
+#define MT8516_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0)
+#define MT8516_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1)
+
+#define MT8516_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0)
+#define MT8516_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1)
+
+#define MT8516_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0)
+#define MT8516_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1)
+
+#define MT8516_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0)
+#define MT8516_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1)
+
+#define MT8516_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0)
+#define MT8516_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1)
+
+#define MT8516_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0)
+#define MT8516_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1)
+
+#define MT8516_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0)
+#define MT8516_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1)
+
+#define MT8516_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0)
+#define MT8516_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1)
+
+#define MT8516_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0)
+#define MT8516_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1)
+
+#define MT8516_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0)
+#define MT8516_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1)
+
+#define MT8516_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0)
+#define MT8516_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1)
+
+#define MT8516_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0)
+#define MT8516_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1)
+#define MT8516_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2)
+
+#define MT8516_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
+#define MT8516_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1)
+#define MT8516_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2)
+
+#define MT8516_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
+#define MT8516_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1)
+#define MT8516_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2)
+
+#define MT8516_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
+#define MT8516_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1)
+#define MT8516_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2)
+
+#define MT8516_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
+#define MT8516_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1)
+#define MT8516_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2)
+
+#define MT8516_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
+#define MT8516_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1)
+#define MT8516_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2)
+
+#define MT8516_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
+#define MT8516_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1)
+#define MT8516_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2)
+#define MT8516_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3)
+
+#define MT8516_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
+#define MT8516_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1)
+#define MT8516_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2)
+#define MT8516_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3)
+
+#define MT8516_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
+#define MT8516_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1)
+#define MT8516_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2)
+
+#define MT8516_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
+#define MT8516_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1)
+#define MT8516_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2)
+
+#define MT8516_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT8516_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1)
+#define MT8516_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2)
+#define MT8516_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3)
+#define MT8516_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5)
+#define MT8516_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7)
+
+#define MT8516_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT8516_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1)
+#define MT8516_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2)
+#define MT8516_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3)
+#define MT8516_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4)
+#define MT8516_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5)
+#define MT8516_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7)
+
+#define MT8516_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT8516_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1)
+#define MT8516_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3)
+#define MT8516_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5)
+#define MT8516_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7)
+
+#define MT8516_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT8516_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1)
+#define MT8516_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2)
+#define MT8516_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3)
+#define MT8516_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5)
+#define MT8516_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7)
+
+#define MT8516_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT8516_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1)
+#define MT8516_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4)
+#define MT8516_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7)
+
+#define MT8516_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT8516_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1)
+#define MT8516_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4)
+#define MT8516_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7)
+
+#define MT8516_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT8516_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1)
+#define MT8516_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4)
+#define MT8516_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7)
+
+#define MT8516_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT8516_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1)
+#define MT8516_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4)
+#define MT8516_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7)
+
+#define MT8516_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT8516_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1)
+#define MT8516_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4)
+#define MT8516_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7)
+
+#define MT8516_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT8516_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1)
+#define MT8516_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4)
+#define MT8516_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7)
+
+#define MT8516_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT8516_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1)
+#define MT8516_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4)
+
+#define MT8516_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT8516_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1)
+#define MT8516_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4)
+
+#define MT8516_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT8516_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1)
+#define MT8516_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4)
+
+#define MT8516_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT8516_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1)
+#define MT8516_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4)
+
+#define MT8516_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT8516_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1)
+#define MT8516_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4)
+
+#define MT8516_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT8516_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1)
+#define MT8516_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4)
+
+#define MT8516_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT8516_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1)
+#define MT8516_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4)
+
+#define MT8516_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT8516_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1)
+#define MT8516_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4)
+
+#define MT8516_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT8516_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1)
+#define MT8516_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4)
+
+#define MT8516_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT8516_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1)
+#define MT8516_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4)
+
+#define MT8516_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT8516_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1)
+#define MT8516_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4)
+#define MT8516_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5)
+
+#endif				/* __DTS_MT8516_PINFUNC_H */
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
new file mode 100644
index 000000000000..6f7a6648e992
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <dt-bindings/clock/mt8516-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "mt8516-pinfunc.h"
+
+/ {
+	compatible = "mediatek,mt8516";
+	interrupt-parent = <&sysirq>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		opp-598000000 {
+			opp-hz = /bits/ 64 <598000000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-747500000 {
+			opp-hz = /bits/ 64 <747500000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-1040000000 {
+			opp-hz = /bits/ 64 <1040000000>;
+			opp-microvolt = <1200000>;
+		};
+		opp-1196000000 {
+			opp-hz = /bits/ 64 <1196000000>;
+			opp-microvolt = <1250000>;
+		};
+		opp-1300000000 {
+			opp-hz = /bits/ 64 <1300000000>;
+			opp-microvolt = <1300000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0>;
+			enable-method = "psci";
+			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
+				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
+			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
+				 <&topckgen CLK_TOP_MAINPLL_D2>,
+				 <&apmixedsys CLK_APMIXED_ARMPLL>;
+			clock-names = "cpu", "intermediate", "armpll";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x1>;
+			enable-method = "psci";
+			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
+				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
+			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
+				 <&topckgen CLK_TOP_MAINPLL_D2>,
+				 <&apmixedsys CLK_APMIXED_ARMPLL>;
+			clock-names = "cpu", "intermediate", "armpll";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x2>;
+			enable-method = "psci";
+			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
+				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
+			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
+				 <&topckgen CLK_TOP_MAINPLL_D2>,
+				 <&apmixedsys CLK_APMIXED_ARMPLL>;
+			clock-names = "cpu", "intermediate", "armpll";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x3>;
+			enable-method = "psci";
+			cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>,
+				<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>;
+			clocks = <&infracfg CLK_IFR_MUX1_SEL>,
+				 <&topckgen CLK_TOP_MAINPLL_D2>,
+				 <&apmixedsys CLK_APMIXED_ARMPLL>;
+			clock-names = "cpu", "intermediate", "armpll";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				entry-latency-us = <600>;
+				exit-latency-us = <600>;
+				min-residency-us = <1200>;
+				arm,psci-suspend-param = <0x0010000>;
+			};
+
+			CLUSTER_SLEEP_0: cluster-sleep-0 {
+				compatible = "arm,idle-state";
+				entry-latency-us = <800>;
+				exit-latency-us = <1000>;
+				min-residency-us = <2000>;
+				arm,psci-suspend-param = <0x2010000>;
+			};
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
+		method      = "smc";
+	};
+
+	clk26m: clk26m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+		clock-output-names = "clk26m";
+	};
+
+	clk32k: clk32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32000>;
+		clock-output-names = "clk32k";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+		bl31_secmon_reserved: secmon@43000000 {
+			no-map;
+			reg = <0 0x43000000 0 0x20000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13
+			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		topckgen: topckgen@10000000 {
+			compatible = "mediatek,mt8516-topckgen", "syscon";
+			reg = <0 0x10000000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		infracfg: infracfg@10001000 {
+			compatible = "mediatek,mt8516-infracfg", "syscon";
+			reg = <0 0x10001000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		apmixedsys: apmixedsys@10018000 {
+			compatible = "mediatek,mt8516-apmixedsys", "syscon";
+			reg = <0 0x10018000 0 0x710>;
+			#clock-cells = <1>;
+		};
+
+		toprgu: toprgu@10007000 {
+			compatible = "mediatek,mt8516-wdt",
+				     "mediatek,mt6589-wdt";
+			reg = <0 0x10007000 0 0x1000>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
+			#reset-cells = <1>;
+		};
+
+		timer: timer@10008000 {
+			compatible = "mediatek,mt8516-timer",
+				     "mediatek,mt6577-timer";
+			reg = <0 0x10008000 0 0x1000>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_CLK26M_D2>,
+				 <&clk32k>,
+				 <&topckgen CLK_TOP_APXGPT>;
+			clock-names = "clk13m", "clk32k", "bus";
+		};
+
+		syscfg_pctl_a: syscfg_pctl_a@10005000 {
+			compatible = "mediatek,mt8516-pctl-a-syscfg", "syscon";
+			reg = <0 0x10005000 0 0x1000>;
+		};
+
+		pio: pinctrl@10005000 {
+			compatible = "mediatek,mt8516-pinctrl";
+			reg = <0 0x1000b000 0 0x1000>;
+			mediatek,pctl-regmap = <&syscfg_pctl_a>;
+			pins-are-numbered;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pwrap: pwrap@1000f000 {
+			compatible = "mediatek,mt8516-pwrap";
+			reg = <0 0x1000f000 0 0x1000>;
+			reg-names = "pwrap";
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
+				 <&topckgen CLK_TOP_PMICWRAP_AP>;
+			clock-names = "spi", "wrap";
+		};
+
+		sysirq: intpol-controller@10200620 {
+			compatible = "mediatek,mt8516-sysirq",
+				     "mediatek,mt6577-sysirq";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			reg = <0 0x10200620 0 0x20>;
+		};
+
+		gic: interrupt-controller@10310000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			reg = <0 0x10310000 0 0x1000>,
+			      <0 0x10320000 0 0x1000>,
+			      <0 0x10340000 0 0x2000>,
+			      <0 0x10360000 0 0x2000>;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		uart0: serial@11005000 {
+			compatible = "mediatek,mt8516-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11005000 0 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_UART0_SEL>,
+				 <&topckgen CLK_TOP_UART0>;
+			clock-names = "baud","bus";
+			status = "disabled";
+		};
+
+		uart1: serial@11006000 {
+			compatible = "mediatek,mt8516-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11006000 0 0x1000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_UART1_SEL>,
+				 <&topckgen CLK_TOP_UART1>;
+			clock-names = "baud","bus";
+			status = "disabled";
+		};
+
+		uart2: serial@11007000 {
+			compatible = "mediatek,mt8516-uart",
+				     "mediatek,mt6577-uart";
+			reg = <0 0x11007000 0 0x1000>;
+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_UART2_SEL>,
+				 <&topckgen CLK_TOP_UART2>;
+			clock-names = "baud","bus";
+			status = "disabled";
+		};
+
+		i2c0: i2c@11009000 {
+			compatible = "mediatek,mt8516-i2c",
+				     "mediatek,mt2712-i2c";
+			reg = <0 0x11009000 0 0x90>,
+			      <0 0x11000180 0 0x80>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
+				 <&infracfg CLK_IFR_I2C0_SEL>,
+				 <&topckgen CLK_TOP_I2C0>,
+				 <&topckgen CLK_TOP_APDMA>;
+			clock-names = "main-source",
+				      "main-sel",
+				      "main",
+				      "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@1100a000 {
+			compatible = "mediatek,mt8516-i2c",
+				     "mediatek,mt2712-i2c";
+			reg = <0 0x1100a000 0 0x90>,
+			      <0 0x11000200 0 0x80>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
+				 <&infracfg CLK_IFR_I2C1_SEL>,
+				 <&topckgen CLK_TOP_I2C1>,
+				 <&topckgen CLK_TOP_APDMA>;
+			clock-names = "main-source",
+				      "main-sel",
+				      "main",
+				      "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@1100b000 {
+			compatible = "mediatek,mt8516-i2c",
+				     "mediatek,mt2712-i2c";
+			reg = <0 0x1100b000 0 0x90>,
+			      <0 0x11000280 0 0x80>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>,
+				 <&infracfg CLK_IFR_I2C2_SEL>,
+				 <&topckgen CLK_TOP_I2C2>,
+				 <&topckgen CLK_TOP_APDMA>;
+			clock-names = "main-source",
+				      "main-sel",
+				      "main",
+				      "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi: spi@1100c000 {
+			compatible = "mediatek,mt8516-spi",
+				     "mediatek,mt2701-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x1100c000 0 0x1000>;
+			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D12>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&topckgen CLK_TOP_SPI>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		mmc0: mmc@11120000 {
+			compatible = "mediatek,mt8516-mmc";
+			reg = <0 0x11120000 0 0x1000>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_MSDC0>,
+					<&topckgen CLK_TOP_AHB_INFRA_SEL>,
+					<&topckgen CLK_TOP_MSDC0_INFRA>;
+			clock-names = "source", "hclk", "source_cg";
+			status = "disabled";
+		};
+
+		mmc1: mmc@11130000 {
+			compatible = "mediatek,mt8516-mmc";
+			reg = <0 0x11130000 0 0x1000>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_MSDC1>,
+					<&topckgen CLK_TOP_AHB_INFRA_SEL>,
+					<&topckgen CLK_TOP_MSDC1_INFRA>;
+			clock-names = "source", "hclk", "source_cg";
+			status = "disabled";
+		};
+
+		mmc2: sdio@11170000 {
+			compatible = "mediatek,mt8516-mmc";
+			reg = <0 0x11170000 0 0x1000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_MSDC2>,
+			       <&topckgen CLK_TOP_RG_MSDC2>,
+			       <&topckgen CLK_TOP_MSDC2_INFRA>;
+			clock-names = "source", "hclk", "source_cg";
+			status = "disabled";
+		};
+	};
+};
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* [PATCH 24/24] arm64: dts: mediatek: add pumpkin board dts
  2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
                   ` (22 preceding siblings ...)
  2019-03-23 21:16 ` [PATCH 23/24] arm64: dts: mediatek: add dtsi " Fabien Parent
@ 2019-03-23 21:16 ` Fabien Parent
  23 siblings, 0 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-23 21:16 UTC (permalink / raw)
  To: matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

The pumpkin board is  made by Gossamer Engineering and is using
a MediaTek SoC. The board currently comes in two available version:
MT8516 SoC and MT8167 SoC.
The board provides the following IOs: eMMC, NAND, SD card, USB type-A,
Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in),
serial over USB, and an expansion header.

Additionally there is a HDMI port, DSI port, and camera port only
on the MT8167 version of the board.

The board can be powered by battery and/or via a USB Type-C port and
is using a PMIC MT6392.

The eMMC and NAND are sharing pins and cannot be used together.

This commit is adding the basic boot support for the Pumpkin MT8516
board on the eMMC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/Makefile         |   1 +
 .../boot/dts/mediatek/mt8516-pumpkin.dts      |  19 ++
 .../boot/dts/mediatek/pumpkin-common.dtsi     | 210 ++++++++++++++++++
 .../dts/mediatek/pumpkin-emmc-common.dtsi     |  75 +++++++
 4 files changed, 305 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
 create mode 100644 arch/arm64/boot/dts/mediatek/pumpkin-emmc-common.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index e8f952fb279b..3c4edaec9449 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts
new file mode 100644
index 000000000000..016f11c6c88c
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "pumpkin-common.dtsi"
+#include "pumpkin-emmc-common.dtsi"
+
+/ {
+	model = "Pumpkin MT8516";
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x40000000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
new file mode 100644
index 000000000000..79d227f28428
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt8516.dtsi"
+#include "mt6392.dtsi"
+
+/ {
+	gpio-keys {
+		compatible = "gpio-keys";
+		input-name = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_keys_default>;
+
+		volume-up {
+			gpios = <&pio 42 GPIO_ACTIVE_LOW>;
+			label = "volume_up";
+			linux,code = <115>;
+			wakeup-source;
+			debounce-interval = <15>;
+		};
+
+		volume-down {
+			gpios = <&pio 43 GPIO_ACTIVE_LOW>;
+			label = "volume_down";
+			linux,code = <114>;
+			wakeup-source;
+			debounce-interval = <15>;
+		};
+	};
+};
+
+&cpu0 {
+	proc-supply = <&mt6392_vproc_reg>;
+};
+
+&cpu1 {
+	proc-supply = <&mt6392_vproc_reg>;
+};
+
+&cpu2 {
+	proc-supply = <&mt6392_vproc_reg>;
+};
+
+&cpu3 {
+	proc-supply = <&mt6392_vproc_reg>;
+};
+
+&i2c0 {
+	clock-div = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_a>;
+	status = "okay";
+
+	tca6416: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		rst-gpio = <&pio 65 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&tca6416_pins>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		eint20_mux_sel0 {
+			gpio-hog;
+			gpios = <0 0>;
+			input;
+			line-name = "eint20_mux_sel0";
+		};
+
+		expcon_mux_sel1 {
+			gpio-hog;
+			gpios = <1 0>;
+			input;
+			line-name = "expcon_mux_sel1";
+		};
+
+		mrg_di_mux_sel2 {
+			gpio-hog;
+			gpios = <2 0>;
+			input;
+			line-name = "mrg_di_mux_sel2";
+		};
+
+		sd_sdio_mux_sel3 {
+			gpio-hog;
+			gpios = <3 0>;
+			input;
+			line-name = "sd_sdio_mux_sel3";
+		};
+
+		sd_sdio_mux_ctrl7 {
+			gpio-hog;
+			gpios = <7 0>;
+			output-low;
+			line-name = "sd_sdio_mux_ctrl7";
+		};
+
+		hw_id0 {
+			gpio-hog;
+			gpios = <8 0>;
+			input;
+			line-name = "hw_id0";
+		};
+
+		hw_id1 {
+			gpio-hog;
+			gpios = <9 0>;
+			input;
+			line-name = "hw_id1";
+		};
+
+		hw_id2 {
+			gpio-hog;
+			gpios = <10 0>;
+			input;
+			line-name = "hw_id2";
+		};
+
+		fg_int_n {
+			gpio-hog;
+			gpios = <11 0>;
+			input;
+			line-name = "fg_int_n";
+		};
+
+		usba_pwr_en {
+			gpio-hog;
+			gpios = <12 0>;
+			output-high;
+			line-name = "usba_pwr_en";
+		};
+
+		wifi_3v3_pg {
+			gpio-hog;
+			gpios = <13 0>;
+			input;
+			line-name = "wifi_3v3_pg";
+		};
+
+		cam_rst {
+			gpio-hog;
+			gpios = <14 0>;
+			output-low;
+			line-name = "cam_rst";
+		};
+
+		cam_pwdn {
+			gpio-hog;
+			gpios = <15 0>;
+			output-low;
+			line-name = "cam_pwdn";
+		};
+	};
+};
+
+&pmic {
+	interrupt-parent = <&pio>;
+	interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&pio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&state_default>;
+
+	state_default:pinconf_default {
+	};
+
+	gpio_keys_default: gpiodefault {
+		pins_cmd_dat {
+			pinmux = <MT8516_PIN_42_KPCOL0__FUNC_GPIO42>,
+				 <MT8516_PIN_43_KPCOL1__FUNC_GPIO43>;
+			bias-pull-up;
+			input-enable;
+		};
+	};
+
+	i2c0_pins_a: i2c0@0 {
+		pins1 {
+			pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>,
+				 <MT8516_PIN_59_SCL0__FUNC_SCL0_0>;
+			bias-disable;
+		};
+	};
+
+
+	tca6416_pins: pinmux_tca6416_pins {
+		gpio_mux_rst_n_pin {
+			pinmux = <MT8516_PIN_65_UTXD1__FUNC_GPIO65>;
+			output-high;
+		};
+
+		gpio_mux_int_n_pin {
+			pinmux = <MT8516_PIN_64_URXD1__FUNC_GPIO64>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-emmc-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-emmc-common.dtsi
new file mode 100644
index 000000000000..6044c8c91cb1
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/pumpkin-emmc-common.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 BayLibre, SAS.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+&mmc0 {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_default>;
+	pinctrl-1 = <&mmc0_pins_uhs>;
+	status = "okay";
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	cap-mmc-hw-reset;
+	vmmc-supply = <&mt6392_vemc3v3_reg>;
+	vqmmc-supply = <&mt6392_vio18_reg>;
+	non-removable;
+};
+
+&pio {
+	mmc0_pins_default: mmc0default {
+		pins_cmd_dat {
+			pinmux = <MT8516_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+				<MT8516_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+				<MT8516_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+				<MT8516_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+				<MT8516_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+				<MT8516_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+				<MT8516_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+				<MT8516_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+				<MT8516_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		pins_clk {
+			pinmux = <MT8516_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK>;
+			bias-pull-down;
+		};
+
+		pins_rst {
+			pinmux = <MT8516_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+			bias-pull-up;
+		};
+	};
+
+	mmc0_pins_uhs: mmc0@0{
+		pins_cmd_dat {
+			pinmux = <MT8516_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+				<MT8516_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+				<MT8516_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+				<MT8516_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+				<MT8516_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+				<MT8516_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+				<MT8516_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+				<MT8516_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+				<MT8516_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <MTK_DRIVE_6mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins_clk {
+			pinmux = <MT8516_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK>;
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins_rst {
+			pinmux = <MT8516_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+			bias-pull-up;
+		};
+	};
+};
-- 
2.20.1


^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 09/24] mmc: mtk-sd: check for valid optional memory resource
  2019-03-23 21:15 ` [PATCH 09/24] mmc: mtk-sd: check for valid optional memory resource Fabien Parent
@ 2019-03-24  3:34   ` Yingjoe Chen
  2019-03-24 15:18     ` Fabien Parent
  0 siblings, 1 reply; 70+ messages in thread
From: Yingjoe Chen @ 2019-03-24  3:34 UTC (permalink / raw)
  To: Fabien Parent
  Cc: matthias.bgg, robh+dt, mark.rutland, linux-arm-kernel,
	devicetree, ryder.lee, linux-watchdog, jjian.zhou, wenzhen.yu,
	stephane.leprovost, sean.wang, linux-mmc, linux-kernel, yong.mao,
	linux-spi, linux-gpio, linux-mediatek, hsin-hsiung.wang,
	linux-serial, linux-clk, chaotian.jing, linux-i2c

On Sat, 2019-03-23 at 22:15 +0100, Fabien Parent wrote:
> 'top_base' memory region is optional. Check that the resource is valid
> before using it. This avoid getting a "invalid resource" error message
> printed by the kernel.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  drivers/mmc/host/mtk-sd.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 833ef0590af8..573aa127d00b 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -2123,9 +2123,11 @@ static int msdc_drv_probe(struct platform_device *pdev)
>  	}
>  
>  	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> -	host->top_base = devm_ioremap_resource(&pdev->dev, res);
> -	if (IS_ERR(host->top_base))
> -		host->top_base = NULL;
> +	if (ret) {

This should be res?

> +		host->top_base = devm_ioremap_resource(&pdev->dev, res);
> +		if (IS_ERR(host->top_base))
> +			host->top_base = NULL;
> +	}
>  
>  	ret = mmc_regulator_get_supply(mmc);
>  	if (ret)



^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 17/24] dt-bindings: wdog: mtk-wdt: add support for MT851
  2019-03-23 21:16 ` [PATCH 17/24] dt-bindings: wdog: mtk-wdt: add support for MT851 Fabien Parent
@ 2019-03-24 15:13   ` Guenter Roeck
  2019-03-28 19:13   ` Rob Herring
  1 sibling, 0 replies; 70+ messages in thread
From: Guenter Roeck @ 2019-03-24 15:13 UTC (permalink / raw)
  To: Fabien Parent, matthias.bgg, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost

On 3/23/19 2:16 PM, Fabien Parent wrote:
> Add binding documentation of mtk-wdt for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>

Acked-by: Guenter Roeck <linux@roeck-us.net>

> ---
>   Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> index 8682d6a93e5b..fd380eb28df5 100644
> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> @@ -9,6 +9,7 @@ Required properties:
>   	"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
>   	"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
>   	"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
> +	"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
>   
>   - reg : Specifies base physical address and size of the registers.
>   
> 


^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 09/24] mmc: mtk-sd: check for valid optional memory resource
  2019-03-24  3:34   ` Yingjoe Chen
@ 2019-03-24 15:18     ` Fabien Parent
  0 siblings, 0 replies; 70+ messages in thread
From: Fabien Parent @ 2019-03-24 15:18 UTC (permalink / raw)
  To: Yingjoe Chen
  Cc: Matthias Brugger, robh+dt, mark.rutland, linux-arm-kernel,
	devicetree, ryder.lee, linux-watchdog, jjian.zhou, wenzhen.yu,
	Stephane Le Provost, sean.wang, linux-mmc, linux-kernel,
	yong.mao, linux-spi, linux-gpio, linux-mediatek,
	hsin-hsiung.wang, linux-serial, linux-clk, Chaotian Jing,
	linux-i2c

On Sun, Mar 24, 2019 at 4:34 AM Yingjoe Chen <yingjoe.chen@mediatek.com> wrote:
>
> On Sat, 2019-03-23 at 22:15 +0100, Fabien Parent wrote:
> > 'top_base' memory region is optional. Check that the resource is valid
> > before using it. This avoid getting a "invalid resource" error message
> > printed by the kernel.
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> >  drivers/mmc/host/mtk-sd.c | 8 +++++---
> >  1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> > index 833ef0590af8..573aa127d00b 100644
> > --- a/drivers/mmc/host/mtk-sd.c
> > +++ b/drivers/mmc/host/mtk-sd.c
> > @@ -2123,9 +2123,11 @@ static int msdc_drv_probe(struct platform_device *pdev)
> >       }
> >
> >       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> > -     host->top_base = devm_ioremap_resource(&pdev->dev, res);
> > -     if (IS_ERR(host->top_base))
> > -             host->top_base = NULL;
> > +     if (ret) {
>
> This should be res?

Indeed. Thanks, I will fix it in v2.

> > +             host->top_base = devm_ioremap_resource(&pdev->dev, res);
> > +             if (IS_ERR(host->top_base))
> > +                     host->top_base = NULL;
> > +     }
> >
> >       ret = mmc_regulator_get_supply(mmc);
> >       if (ret)
>
>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 03/24] dt-bindings: pwrap: mediatek: add pwrap support for MT8516
  2019-03-23 21:15 ` [PATCH 03/24] dt-bindings: pwrap: mediatek: add pwrap support for MT8516 Fabien Parent
@ 2019-03-28 19:09   ` Rob Herring
  2019-04-12 17:44   ` Matthias Brugger
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:09 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:16 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of pwrap for MT8516 SoCs.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 11/24] dt-bindings: mediatek: topckgen: add support for MT8516
  2019-03-23 21:15 ` [PATCH 11/24] dt-bindings: mediatek: topckgen: " Fabien Parent
@ 2019-03-28 19:09   ` Rob Herring
  2019-04-25 21:34   ` Stephen Boyd
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:09 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of topckgen for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  .../arm/mediatek/mediatek,topckgen.txt        |   1 +
>  include/dt-bindings/clock/mt8516-clk.h        | 192 ++++++++++++++++++
>  2 files changed, 193 insertions(+)
>  create mode 100644 include/dt-bindings/clock/mt8516-clk.h

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 12/24] dt-bindings: mediatek: infracfg: add support for MT8516
  2019-03-23 21:16 ` [PATCH 12/24] dt-bindings: mediatek: infracfg: " Fabien Parent
@ 2019-03-28 19:10   ` Rob Herring
  2019-04-25 21:34   ` Stephen Boyd
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:10 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of infracfg for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  .../bindings/arm/mediatek/mediatek,infracfg.txt          | 1 +
>  include/dt-bindings/clock/mt8516-clk.h                   | 9 +++++++++
>  2 files changed, 10 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 13/24] dt-bindings: mediatek: apmixedsys: add support for MT8516
  2019-03-23 21:16 ` [PATCH 13/24] dt-bindings: mediatek: apmixedsys: " Fabien Parent
@ 2019-03-28 19:11   ` Rob Herring
  2019-04-25 21:35   ` Stephen Boyd
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:11 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of apmixedsys for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  .../bindings/arm/mediatek/mediatek,apmixedsys.txt      |  1 +
>  include/dt-bindings/clock/mt8516-clk.h                 | 10 ++++++++++
>  2 files changed, 11 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support for MT8516
  2019-03-23 21:16 ` [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support " Fabien Parent
@ 2019-03-28 19:11   ` Rob Herring
  2019-04-08 20:44   ` Linus Walleij
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:11 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of pinctrl-mt65xx for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516
  2019-03-23 21:16 ` [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516 Fabien Parent
@ 2019-03-28 19:12   ` Rob Herring
  2019-04-16  7:54   ` Matthias Brugger
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:12 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of mtk-timer for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-03-23 21:16 ` [PATCH 19/24] dt-bindings: spi: spi-mt65xx: " Fabien Parent
@ 2019-03-28 19:12   ` Rob Herring
  2019-04-16  7:55   ` Matthias Brugger
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:12 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of spi-mt65xx for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 20/24] dt-bindings: serial: mtk-uart: add support for MT8516
  2019-03-23 21:16 ` [PATCH 20/24] dt-bindings: serial: mtk-uart: " Fabien Parent
@ 2019-03-28 19:12   ` Rob Herring
  2019-04-16  7:56   ` Matthias Brugger
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:12 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of mtk-uart for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 21/24] dt-bindings: irq: mtk,sysirq: add support for MT8516
  2019-03-23 21:16 ` [PATCH 21/24] dt-bindings: irq: mtk,sysirq: " Fabien Parent
@ 2019-03-28 19:13   ` Rob Herring
  2019-04-16  7:57   ` Matthias Brugger
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:13 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of mediatek,sysirq for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  .../bindings/interrupt-controller/mediatek,sysirq.txt          | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
  2019-03-23 21:16 ` [PATCH 22/24] dt-bindings: i2c: i2c-mtk: " Fabien Parent
@ 2019-03-28 19:13   ` Rob Herring
  2019-04-16  7:58   ` Matthias Brugger
  2019-04-16 11:05   ` Wolfram Sang
  2 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:13 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of i2c-mtk for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 17/24] dt-bindings: wdog: mtk-wdt: add support for MT851
  2019-03-23 21:16 ` [PATCH 17/24] dt-bindings: wdog: mtk-wdt: add support for MT851 Fabien Parent
  2019-03-24 15:13   ` Guenter Roeck
@ 2019-03-28 19:13   ` Rob Herring
  1 sibling, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:13 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of mtk-wdt for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 01/24] dt-bindings: regulator: add support for MT6392
  2019-03-23 21:15 ` [PATCH 01/24] dt-bindings: regulator: add support for MT6392 Fabien Parent
@ 2019-03-28 19:17   ` Rob Herring
  0 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:17 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:16 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add binding documentation of the regulator for MT6392 SoCs.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  .../bindings/regulator/mt6392-regulator.txt   | 220 ++++++++++++++++++
>  1 file changed, 220 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
>
> diff --git a/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
> new file mode 100644
> index 000000000000..edf207c838dc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/regulator/mt6392-regulator.txt
> @@ -0,0 +1,220 @@
> +Mediatek MT6392 Regulator
> +
> +Required properties:
> +- compatible: "mediatek,mt6392-regulator"
> +- mt6392regulator: List of regulators provided by this controller. It is named
> +  according to its regulator type, buck_<name> and ldo_<name>.
> +  The definition for each of these nodes is defined using the standard binding
> +  for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
> +
> +The valid names for regulators are::
> +BUCK:
> +  buck_vproc, buck_vsys, buck_vcore
> +LDO:
> +  ldo_vxo22, ldo_vaud22, ldo_vcama, ldo_vaud28, ldo_vadc18, ldo_vcn35,
> +  ldo_vio28. ldo_vusb, ldo_vmc, ldo_vmch, ldo_vemc3v3, ldo_vgp1, ldo_vgp2,
> +  ldo_vcn18, ldo_vcamaf, ldo_vm, ldo_vio18, ldo_vcamd, ldo_vcamio, ldo_vm25,
> +  ldo_vefuse
> +
> +Example:
> +       pmic: mt6392 {

pmic {

> +               compatible = "mediatek,mt6392", "mediatek,mt6323";
> +               mediatek,system-power-controller;
> +
> +               mt6392_regulator: mt6392_regulator {

regulators {

> +                       compatible = "mediatek,mt6392-regulator";
> +
> +                       mt6392_vproc_reg: buck_vproc {

buck-vproc {

And similar for the rest.

> +                               regulator-name = "buck_vproc";
> +                               regulator-min-microvolt = < 700000>;
> +                               regulator-max-microvolt = <1350000>;
> +                               regulator-ramp-delay = <12500>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vsys_reg: buck_vsys {
> +                               regulator-name = "buck_vsys";
> +                               regulator-min-microvolt = <1400000>;
> +                               regulator-max-microvolt = <2987500>;
> +                               regulator-ramp-delay = <25000>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vcore_reg: buck_vcore {
> +                               regulator-name = "buck_vcore";
> +                               regulator-min-microvolt = < 700000>;
> +                               regulator-max-microvolt = <1350000>;
> +                               regulator-ramp-delay = <12500>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vxo22_reg: ldo_vxo22 {
> +                               regulator-name = "ldo_vxo22";
> +                               regulator-min-microvolt = <2200000>;
> +                               regulator-max-microvolt = <2200000>;
> +                               regulator-enable-ramp-delay = <110>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vaud22_reg: ldo_vaud22 {
> +                               regulator-name = "ldo_vaud22";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <2200000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vcama_reg: ldo_vcama {
> +                               regulator-name = "ldo_vcama";
> +                               regulator-min-microvolt = <2800000>;
> +                               regulator-max-microvolt = <2800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vaud28_reg: ldo_vaud28 {
> +                               regulator-name = "ldo_vaud28";
> +                               regulator-min-microvolt = <2800000>;
> +                               regulator-max-microvolt = <2800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vadc18_reg: ldo_vadc18 {
> +                               regulator-name = "ldo_vadc18";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vcn35_reg: ldo_vcn35 {
> +                               regulator-name = "ldo_vcn35";
> +                               regulator-min-microvolt = <3300000>;
> +                               regulator-max-microvolt = <3600000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vio28_reg: ldo_vio28 {
> +                               regulator-name = "ldo_vio28";
> +                               regulator-min-microvolt = <2800000>;
> +                               regulator-max-microvolt = <2800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vusb_reg: ldo_vusb {
> +                               regulator-name = "ldo_vusb";
> +                               regulator-min-microvolt = <3300000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vmc_reg: ldo_vmc {
> +                               regulator-name = "ldo_vmc";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vmch_reg: ldo_vmch {
> +                               regulator-name = "ldo_vmch";
> +                               regulator-min-microvolt = <3000000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vemc3v3_reg: ldo_vemc3v3 {
> +                               regulator-name = "ldo_vemc3v3";
> +                               regulator-min-microvolt = <3000000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vgp1_reg: ldo_vgp1 {
> +                               regulator-name = "ldo_vgp1";
> +                               regulator-min-microvolt = <1200000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vgp2_reg: ldo_vgp2 {
> +                               regulator-name = "ldo_vgp2";
> +                               regulator-min-microvolt = <1200000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vcn18_reg: ldo_vcn18 {
> +                               regulator-name = "ldo_vcn18";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vcamaf_reg: ldo_vcamaf {
> +                               regulator-name = "ldo_vcamaf";
> +                               regulator-min-microvolt = <1200000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vm_reg: ldo_vm {
> +                               regulator-name = "ldo_vm";
> +                               regulator-min-microvolt = <1240000>;
> +                               regulator-max-microvolt = <1390000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vio18_reg: ldo_vio18 {
> +                               regulator-name = "ldo_vio18";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vcamd_reg: ldo_vcamd {
> +                               regulator-name = "ldo_vcamd";
> +                               regulator-min-microvolt = <1200000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vcamio_reg: ldo_vcamio {
> +                               regulator-name = "ldo_vcamio";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vm25_reg: ldo_vm25 {
> +                               regulator-name = "ldo_vm25";
> +                               regulator-min-microvolt = <2500000>;
> +                               regulator-max-microvolt = <2500000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vefuse_reg: ldo_vefuse {
> +                               regulator-name = "ldo_vefuse";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <2000000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +               };
> +       };
> --
> 2.20.1
>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 07/24] arm64: dts: mt6392: Add PMIC mt6392 dtsi
  2019-03-23 21:15 ` [PATCH 07/24] arm64: dts: mt6392: Add PMIC mt6392 dtsi Fabien Parent
@ 2019-03-28 19:18   ` Rob Herring
  0 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:18 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:16 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Add the regulator nodes for the MT6392 PMIC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt6392.dtsi | 208 +++++++++++++++++++++++
>  1 file changed, 208 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt6392.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6392.dtsi b/arch/arm64/boot/dts/mediatek/mt6392.dtsi
> new file mode 100644
> index 000000000000..e33a45fd52af
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6392.dtsi
> @@ -0,0 +1,208 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + */
> +
> +&pwrap {
> +       pmic: mt6392 {

Same comments in binding example apply here.

> +               compatible = "mediatek,mt6392", "mediatek,mt6323";
> +               mediatek,system-power-controller;
> +
> +               mt6392_regulator: mt6392_regulator {
> +                       compatible = "mediatek,mt6392-regulator";
> +
> +                       mt6392_vproc_reg: buck_vproc {
> +                               regulator-name = "buck_vproc";
> +                               regulator-min-microvolt = < 700000>;
> +                               regulator-max-microvolt = <1350000>;
> +                               regulator-ramp-delay = <12500>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vsys_reg: buck_vsys {
> +                               regulator-name = "buck_vsys";
> +                               regulator-min-microvolt = <1400000>;
> +                               regulator-max-microvolt = <2987500>;
> +                               regulator-ramp-delay = <25000>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vcore_reg: buck_vcore {
> +                               regulator-name = "buck_vcore";
> +                               regulator-min-microvolt = < 700000>;
> +                               regulator-max-microvolt = <1350000>;
> +                               regulator-ramp-delay = <12500>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vxo22_reg: ldo_vxo22 {
> +                               regulator-name = "ldo_vxo22";
> +                               regulator-min-microvolt = <2200000>;
> +                               regulator-max-microvolt = <2200000>;
> +                               regulator-enable-ramp-delay = <110>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vaud22_reg: ldo_vaud22 {
> +                               regulator-name = "ldo_vaud22";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <2200000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vcama_reg: ldo_vcama {
> +                               regulator-name = "ldo_vcama";
> +                               regulator-min-microvolt = <2800000>;
> +                               regulator-max-microvolt = <2800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vaud28_reg: ldo_vaud28 {
> +                               regulator-name = "ldo_vaud28";
> +                               regulator-min-microvolt = <2800000>;
> +                               regulator-max-microvolt = <2800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vadc18_reg: ldo_vadc18 {
> +                               regulator-name = "ldo_vadc18";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vcn35_reg: ldo_vcn35 {
> +                               regulator-name = "ldo_vcn35";
> +                               regulator-min-microvolt = <3300000>;
> +                               regulator-max-microvolt = <3600000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vio28_reg: ldo_vio28 {
> +                               regulator-name = "ldo_vio28";
> +                               regulator-min-microvolt = <2800000>;
> +                               regulator-max-microvolt = <2800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vusb_reg: ldo_vusb {
> +                               regulator-name = "ldo_vusb";
> +                               regulator-min-microvolt = <3300000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vmc_reg: ldo_vmc {
> +                               regulator-name = "ldo_vmc";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vmch_reg: ldo_vmch {
> +                               regulator-name = "ldo_vmch";
> +                               regulator-min-microvolt = <3000000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vemc3v3_reg: ldo_vemc3v3 {
> +                               regulator-name = "ldo_vemc3v3";
> +                               regulator-min-microvolt = <3000000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vgp1_reg: ldo_vgp1 {
> +                               regulator-name = "ldo_vgp1";
> +                               regulator-min-microvolt = <1200000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vgp2_reg: ldo_vgp2 {
> +                               regulator-name = "ldo_vgp2";
> +                               regulator-min-microvolt = <1200000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vcn18_reg: ldo_vcn18 {
> +                               regulator-name = "ldo_vcn18";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vcamaf_reg: ldo_vcamaf {
> +                               regulator-name = "ldo_vcamaf";
> +                               regulator-min-microvolt = <1200000>;
> +                               regulator-max-microvolt = <3300000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vm_reg: ldo_vm {
> +                               regulator-name = "ldo_vm";
> +                               regulator-min-microvolt = <1240000>;
> +                               regulator-max-microvolt = <1390000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vio18_reg: ldo_vio18 {
> +                               regulator-name = "ldo_vio18";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                               regulator-always-on;
> +                               regulator-boot-on;
> +                       };
> +
> +                       mt6392_vcamd_reg: ldo_vcamd {
> +                               regulator-name = "ldo_vcamd";
> +                               regulator-min-microvolt = <1200000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vcamio_reg: ldo_vcamio {
> +                               regulator-name = "ldo_vcamio";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <1800000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vm25_reg: ldo_vm25 {
> +                               regulator-name = "ldo_vm25";
> +                               regulator-min-microvolt = <2500000>;
> +                               regulator-max-microvolt = <2500000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +
> +                       mt6392_vefuse_reg: ldo_vefuse {
> +                               regulator-name = "ldo_vefuse";
> +                               regulator-min-microvolt = <1800000>;
> +                               regulator-max-microvolt = <2000000>;
> +                               regulator-enable-ramp-delay = <264>;
> +                       };
> +               };
> +       };
> +};
> --
> 2.20.1
>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 23/24] arm64: dts: mediatek: add dtsi for MT8516
  2019-03-23 21:16 ` [PATCH 23/24] arm64: dts: mediatek: add dtsi " Fabien Parent
@ 2019-03-28 19:22   ` Rob Herring
  2019-04-16  8:04     ` Matthias Brugger
  0 siblings, 1 reply; 70+ messages in thread
From: Rob Herring @ 2019-03-28 19:22 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Mark Rutland, Sean Wang, Ryder Lee,
	Hsin-Hsiung Wang, Wenzhen Yu, Chaotian Jing, Yong Mao,
	jjian.zhou, devicetree, linux-kernel, Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> The MT8516 SoC provides the following peripherals: GPIO, UART, USB2,
> SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, Timers, IR, Ethernet, and
> Audio (I2S, SPDIF, TDM).
>
> This commit is adding the basic dtsi file with the support of the
> following IOs: GPIO, UART, SPI, eMMC, I2C, Timers.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h | 663 ++++++++++++++++++
>  arch/arm64/boot/dts/mediatek/mt8516.dtsi      | 409 +++++++++++
>  2 files changed, 1072 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8516.dtsi

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 16/24] pinctrl: mediatek: Add MT8516 Pinctrl driver
  2019-03-23 21:16 ` [PATCH 16/24] pinctrl: mediatek: Add MT8516 Pinctrl driver Fabien Parent
@ 2019-04-01 21:02   ` Sean Wang
  0 siblings, 0 replies; 70+ messages in thread
From: Sean Wang @ 2019-04-01 21:02 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Rob Herring, Mark Rutland,
	Ryder Lee (李庚諺),
	Hsin-Hsiung Wang, wenzhen.yu, chaotian.jing, yong.mao,
	jjian.zhou, devicetree, linux-kernel, linux-i2c,
	linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
	linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost

Hi, Fabien

On Sat, Mar 23, 2019 at 2:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  drivers/pinctrl/mediatek/Kconfig              |    7 +
>  drivers/pinctrl/mediatek/Makefile             |    1 +
>  drivers/pinctrl/mediatek/pinctrl-mt8516.c     |  384 ++++++
>  drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h | 1182 +++++++++++++++++
>  4 files changed, 1574 insertions(+)
>  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8516.c
>  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
>
> diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
> index a005cbccb4f7..26ed5dca1460 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -113,6 +113,13 @@ config PINCTRL_MT8183
>         default ARM64 && ARCH_MEDIATEK
>         select PINCTRL_MTK_PARIS
>
> +config PINCTRL_MT8516
> +       bool "Mediatek MT8516 pin control"
> +       depends on OF
> +       depends on ARM64 || COMPILE_TEST
> +       default ARM64 && ARCH_MEDIATEK
> +       select PINCTRL_MTK
> +
>  # For PMIC
>  config PINCTRL_MT6397
>         bool "Mediatek MT6397 pin control"
> diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
> index 4b4e2eaf6f2d..a74325abd877 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -17,4 +17,5 @@ obj-$(CONFIG_PINCTRL_MT7623)  += pinctrl-mt7623.o
>  obj-$(CONFIG_PINCTRL_MT7629)   += pinctrl-mt7629.o
>  obj-$(CONFIG_PINCTRL_MT8173)   += pinctrl-mt8173.o
>  obj-$(CONFIG_PINCTRL_MT8183)   += pinctrl-mt8183.o
> +obj-$(CONFIG_PINCTRL_MT8516)   += pinctrl-mt8516.o
>  obj-$(CONFIG_PINCTRL_MT6397)   += pinctrl-mt6397.o
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
> new file mode 100644
> index 000000000000..1e965f119eca
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
> @@ -0,0 +1,384 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Min.Guo <min.guo@mediatek.com>
> + */
> +
> +#include <dt-bindings/pinctrl/mt65xx.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/module.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "pinctrl-mtk-common.h"
> +#include "pinctrl-mtk-mt8516.h"
> +
> +static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
> +       /* 0E4E8SR 4/8/12/16 */
> +       MTK_DRV_GRP(4, 16, 1, 2, 4),
> +       /* 0E2E4SR  2/4/6/8 */
> +       MTK_DRV_GRP(2, 8, 1, 2, 2),
> +       /* E8E4E2  2/4/6/8/10/12/14/16 */
> +       MTK_DRV_GRP(2, 16, 0, 2, 2)
> +};
> +
> +static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
> +       MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
> +       MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
> +       MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
> +       MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
> +       MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
> +
> +       MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
> +       MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
> +       MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
> +       MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
> +       MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
> +       MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
> +
> +       MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
> +       MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
> +       MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
> +
> +       MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
> +       MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
> +       MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
> +       MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
> +
> +       MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
> +       MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
> +       MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
> +
> +       MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
> +       MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
> +       MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
> +
> +       MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
> +       MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
> +
> +       MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
> +       MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
> +       MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
> +       MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
> +       MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
> +
> +       MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
> +       MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
> +       MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
> +
> +       MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
> +       MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
> +
> +       MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
> +       MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
> +       MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
> +       MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
> +
> +       MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
> +
> +       MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
> +       MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
> +       MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
> +
> +       MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
> +       MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
> +       MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
> +       MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
> +
> +       MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
> +       MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
> +       MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
> +       MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
> +
> +       MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
> +
> +       MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
> +       MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
> +       MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
> +
> +       MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
> +       MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
> +       MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
> +       MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
> +       MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
> +       MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
> +
> +       MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
> +
> +       MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
> +
> +       MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
> +       MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
> +       MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
> +       MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
> +
> +       MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
> +       MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
> +       MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
> +       MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
> +
> +       MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
> +
> +       MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
> +
> +       MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
> +       MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
> +       MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
> +       MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
> +
> +       MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
> +       MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
> +       MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
> +       MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
> +
> +       MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
> +
> +       MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
> +
> +       MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
> +
> +       MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
> +       MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
> +       MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
> +       MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
> +};
> +
> +static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
> +       MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
> +       MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
> +       MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
> +       MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
> +
> +       MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
> +       MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
> +       MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
> +
> +       MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
> +       MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
> +       MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
> +       MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
> +
> +       MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
> +       MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
> +       MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
> +       MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
> +       MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
> +       MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
> +
> +       MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
> +       MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
> +       MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
> +       MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
> +       MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
> +       MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
> +       MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
> +       MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
> +       MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
> +       MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
> +       MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
> +       MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
> +       MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
> +       MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
> +       MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
> +       MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
> +       MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
> +};
> +
> +static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
> +                       unsigned char align, bool isup, unsigned int r1r0)
> +{
> +       return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
> +               ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
> +}
> +
> +static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
> +       MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
> +       MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
> +       MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
> +       MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
> +       MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
> +       MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
> +       MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
> +       MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
> +       MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
> +       MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
> +       MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
> +       MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
> +       MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
> +       MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
> +       MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
> +       MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
> +       MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
> +       MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
> +       MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
> +       MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
> +       MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
> +       MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
> +       MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
> +       MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
> +       MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
> +       MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
> +       MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
> +       MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
> +       MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
> +       MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
> +       MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
> +       MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
> +       MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
> +       MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
> +       MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
> +       MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
> +       MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
> +       MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
> +       MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
> +       MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
> +       MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
> +       MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
> +       MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
> +       MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
> +       MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
> +       MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
> +};
> +
> +static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
> +       MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
> +       MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
> +       MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
> +       MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
> +       MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
> +       MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
> +       MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
> +       MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
> +       MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
> +       MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
> +       MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
> +       MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
> +       MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
> +       MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
> +       MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
> +       MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
> +       MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
> +       MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
> +       MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
> +       MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
> +       MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
> +       MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
> +       MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
> +       MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
> +       MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
> +       MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
> +       MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
> +
> +       MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
> +       MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
> +       MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
> +       MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
> +       MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
> +       MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
> +       MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
> +       MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
> +       MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
> +       MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
> +       MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
> +       MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
> +       MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
> +       MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
> +       MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
> +       MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
> +       MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
> +       MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
> +       MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
> +};
> +
> +static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
> +               unsigned char align, int value, enum pin_config_param arg)
> +{
> +       if (arg == PIN_CONFIG_INPUT_ENABLE)
> +               return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
> +                       ARRAY_SIZE(mt8516_ies_set), pin, align, value);
> +       else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
> +               return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
> +                       ARRAY_SIZE(mt8516_smt_set), pin, align, value);
> +       return -EINVAL;
> +}
> +
> +static struct mtk_eint_regs mt8516_eint_regs = {
> +       .stat = 0x000,
> +       .ack = 0x040,
> +       .mask = 0x080,
> +       .mask_set = 0x0c0,
> +       .mask_clr = 0x100,
> +       .sens = 0x140,
> +       .sens_set = 0x180,
> +       .sens_clr = 0x1c0,
> +       .soft = 0x200,
> +       .soft_set = 0x240,
> +       .soft_clr = 0x280,
> +       .pol = 0x300,
> +       .pol_set = 0x340,
> +       .pol_clr = 0x380,
> +       .dom_en = 0x400,
> +       .dbnc_ctrl = 0x500,
> +       .dbnc_set = 0x600,
> +       .dbnc_clr = 0x700,
> +};
> +
> +static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
> +       .pins = mtk_pins_mt8516,
> +       .npins = ARRAY_SIZE(mtk_pins_mt8516),
> +       .grp_desc = mt8516_drv_grp,
> +       .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
> +       .pin_drv_grp = mt8516_pin_drv,
> +       .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
> +       .spec_pull_set = mt8516_spec_pull_set,
> +       .spec_ies_smt_set = mt8516_ies_smt_set,
> +       .dir_offset = 0x0000,
> +       .pullen_offset = 0x0500,
> +       .pullsel_offset = 0x0600,
> +       .dout_offset = 0x0100,
> +       .din_offset = 0x0200,
> +       .pinmux_offset = 0x0300,
> +       .type1_start = 125,
> +       .type1_end = 125,
> +       .port_shf = 4,
> +       .port_mask = 0xf,
> +       .port_align = 4,
> +       .eint_regs = &mt8516_eint_regs,

The eint register layout seems definitely the same to the generic one.
So mt8516_eint_regs struct defintions and the field assignment can be
dropped.  And then the driver will fall back to use a generic one
"mtk_generic_eint_regs" which are currently common to all MediaTek
pinctrls devices. Others look good to me.

> +       .eint_hw = {
> +               .port_mask = 7,
> +               .ports     = 6,
> +               .ap_num    = 169,
> +               .db_cnt    = 64,
> +       },
> +};
> +
> +static int mt8516_pinctrl_probe(struct platform_device *pdev)
> +{
> +       return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
> +}
> +
> +static const struct of_device_id mt8516_pctrl_match[] = {
> +       {
> +               .compatible = "mediatek,mt8516-pinctrl",
> +       },
> +       {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
> +
> +static struct platform_driver mtk_pinctrl_driver = {
> +       .probe = mt8516_pinctrl_probe,
> +       .driver = {
> +               .name = "mediatek-mt8516-pinctrl",
> +               .of_match_table = mt8516_pctrl_match,
> +               .pm = &mtk_eint_pm_ops,
> +       },
> +};
> +
> +static int __init mtk_pinctrl_init(void)
> +{
> +       return platform_driver_register(&mtk_pinctrl_driver);
> +}
> +arch_initcall(mtk_pinctrl_init);
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
> new file mode 100644
> index 000000000000..f7a4c6e4a026
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
> @@ -0,0 +1,1182 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2019 MediaTek Inc.
> + */
> +#ifndef __PINCTRL_MTK_MT8516_H
> +#define __PINCTRL_MTK_MT8516_H
> +
> +#include <linux/pinctrl/pinctrl.h>
> +#include "pinctrl-mtk-common.h"
> +
> +static const struct mtk_desc_pin mtk_pins_mt8516[] = {
> +       MTK_PIN(
> +               PINCTRL_PIN(0, "EINT0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 0),
> +               MTK_FUNCTION(0, "GPIO0"),
> +               MTK_FUNCTION(1, "PWM_B"),
> +               MTK_FUNCTION(3, "I2S2_BCK"),
> +               MTK_FUNCTION(4, "EXT_TXD0"),
> +               MTK_FUNCTION(6, "SQICS"),
> +               MTK_FUNCTION(7, "DBG_MON_A[6]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(1, "EINT1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 1),
> +               MTK_FUNCTION(0, "GPIO1"),
> +               MTK_FUNCTION(1, "PWM_C"),
> +               MTK_FUNCTION(3, "I2S2_DI"),
> +               MTK_FUNCTION(4, "EXT_TXD1"),
> +               MTK_FUNCTION(5, "CONN_MCU_TDO"),
> +               MTK_FUNCTION(6, "SQISO"),
> +               MTK_FUNCTION(7, "DBG_MON_A[7]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(2, "EINT2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 2),
> +               MTK_FUNCTION(0, "GPIO2"),
> +               MTK_FUNCTION(1, "CLKM0"),
> +               MTK_FUNCTION(3, "I2S2_LRCK"),
> +               MTK_FUNCTION(4, "EXT_TXD2"),
> +               MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
> +               MTK_FUNCTION(6, "SQISI"),
> +               MTK_FUNCTION(7, "DBG_MON_A[8]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(3, "EINT3"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 3),
> +               MTK_FUNCTION(0, "GPIO3"),
> +               MTK_FUNCTION(1, "CLKM1"),
> +               MTK_FUNCTION(3, "SPI_MI"),
> +               MTK_FUNCTION(4, "EXT_TXD3"),
> +               MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
> +               MTK_FUNCTION(6, "SQIWP"),
> +               MTK_FUNCTION(7, "DBG_MON_A[9]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(4, "EINT4"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 4),
> +               MTK_FUNCTION(0, "GPIO4"),
> +               MTK_FUNCTION(1, "CLKM2"),
> +               MTK_FUNCTION(3, "SPI_MO"),
> +               MTK_FUNCTION(4, "EXT_TXC"),
> +               MTK_FUNCTION(5, "CONN_MCU_TCK"),
> +               MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"),
> +               MTK_FUNCTION(7, "DBG_MON_A[10]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(5, "EINT5"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 5),
> +               MTK_FUNCTION(0, "GPIO5"),
> +               MTK_FUNCTION(1, "UCTS2"),
> +               MTK_FUNCTION(3, "SPI_CSB"),
> +               MTK_FUNCTION(4, "EXT_RXER"),
> +               MTK_FUNCTION(5, "CONN_MCU_TDI"),
> +               MTK_FUNCTION(6, "CONN_TEST_CK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[11]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(6, "EINT6"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 6),
> +               MTK_FUNCTION(0, "GPIO6"),
> +               MTK_FUNCTION(1, "URTS2"),
> +               MTK_FUNCTION(3, "SPI_CLK"),
> +               MTK_FUNCTION(4, "EXT_RXC"),
> +               MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
> +               MTK_FUNCTION(7, "DBG_MON_A[12]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(7, "EINT7"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 7),
> +               MTK_FUNCTION(0, "GPIO7"),
> +               MTK_FUNCTION(1, "SQIRST"),
> +               MTK_FUNCTION(3, "SDA1_0"),
> +               MTK_FUNCTION(4, "EXT_RXDV"),
> +               MTK_FUNCTION(5, "CONN_MCU_TMS"),
> +               MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"),
> +               MTK_FUNCTION(7, "DBG_MON_A[13]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(8, "EINT8"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 8),
> +               MTK_FUNCTION(0, "GPIO8"),
> +               MTK_FUNCTION(1, "SQICK"),
> +               MTK_FUNCTION(2, "CLKM3"),
> +               MTK_FUNCTION(3, "SCL1_0"),
> +               MTK_FUNCTION(4, "EXT_RXD0"),
> +               MTK_FUNCTION(5, "ANT_SEL0"),
> +               MTK_FUNCTION(7, "DBG_MON_A[14]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(9, "EINT9"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 9),
> +               MTK_FUNCTION(0, "GPIO9"),
> +               MTK_FUNCTION(1, "CLKM4"),
> +               MTK_FUNCTION(2, "SDA2_0"),
> +               MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
> +               MTK_FUNCTION(4, "EXT_RXD1"),
> +               MTK_FUNCTION(5, "ANT_SEL1"),
> +               MTK_FUNCTION(7, "DBG_MON_A[15]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(10, "EINT10"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 10),
> +               MTK_FUNCTION(0, "GPIO10"),
> +               MTK_FUNCTION(1, "CLKM5"),
> +               MTK_FUNCTION(2, "SCL2_0"),
> +               MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
> +               MTK_FUNCTION(4, "EXT_RXD2"),
> +               MTK_FUNCTION(5, "ANT_SEL2"),
> +               MTK_FUNCTION(7, "DBG_MON_A[16]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(11, "EINT11"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 11),
> +               MTK_FUNCTION(0, "GPIO11"),
> +               MTK_FUNCTION(1, "CLKM4"),
> +               MTK_FUNCTION(2, "PWM_C"),
> +               MTK_FUNCTION(3, "CONN_TEST_CK"),
> +               MTK_FUNCTION(4, "ANT_SEL3"),
> +               MTK_FUNCTION(6, "EXT_RXD3"),
> +               MTK_FUNCTION(7, "DBG_MON_A[17]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(12, "EINT12"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 12),
> +               MTK_FUNCTION(0, "GPIO12"),
> +               MTK_FUNCTION(1, "CLKM5"),
> +               MTK_FUNCTION(2, "PWM_A"),
> +               MTK_FUNCTION(3, "SPDIF_OUT"),
> +               MTK_FUNCTION(4, "ANT_SEL4"),
> +               MTK_FUNCTION(6, "EXT_TXEN"),
> +               MTK_FUNCTION(7, "DBG_MON_A[18]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(13, "EINT13"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 13),
> +               MTK_FUNCTION(0, "GPIO13"),
> +               MTK_FUNCTION(3, "TSF_IN"),
> +               MTK_FUNCTION(4, "ANT_SEL5"),
> +               MTK_FUNCTION(6, "SPDIF_IN"),
> +               MTK_FUNCTION(7, "DBG_MON_A[19]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(14, "EINT14"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 14),
> +               MTK_FUNCTION(0, "GPIO14"),
> +               MTK_FUNCTION(2, "I2S_8CH_DO1"),
> +               MTK_FUNCTION(3, "TDM_RX_MCK"),
> +               MTK_FUNCTION(4, "ANT_SEL1"),
> +               MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
> +               MTK_FUNCTION(6, "NCLE"),
> +               MTK_FUNCTION(7, "DBG_MON_B[8]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(15, "EINT15"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 15),
> +               MTK_FUNCTION(0, "GPIO15"),
> +               MTK_FUNCTION(2, "I2S_8CH_LRCK"),
> +               MTK_FUNCTION(3, "TDM_RX_BCK"),
> +               MTK_FUNCTION(4, "ANT_SEL2"),
> +               MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
> +               MTK_FUNCTION(6, "NCEB1"),
> +               MTK_FUNCTION(7, "DBG_MON_B[9]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(16, "EINT16"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 16),
> +               MTK_FUNCTION(0, "GPIO16"),
> +               MTK_FUNCTION(2, "I2S_8CH_BCK"),
> +               MTK_FUNCTION(3, "TDM_RX_LRCK"),
> +               MTK_FUNCTION(4, "ANT_SEL3"),
> +               MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
> +               MTK_FUNCTION(6, "NCEB0"),
> +               MTK_FUNCTION(7, "DBG_MON_B[10]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(17, "EINT17"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 17),
> +               MTK_FUNCTION(0, "GPIO17"),
> +               MTK_FUNCTION(2, "I2S_8CH_MCK"),
> +               MTK_FUNCTION(3, "TDM_RX_DI"),
> +               MTK_FUNCTION(4, "IDDIG"),
> +               MTK_FUNCTION(5, "ANT_SEL4"),
> +               MTK_FUNCTION(6, "NREB"),
> +               MTK_FUNCTION(7, "DBG_MON_B[11]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(18, "EINT18"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 18),
> +               MTK_FUNCTION(0, "GPIO18"),
> +               MTK_FUNCTION(2, "USB_DRVVBUS"),
> +               MTK_FUNCTION(3, "I2S3_LRCK"),
> +               MTK_FUNCTION(4, "CLKM1"),
> +               MTK_FUNCTION(5, "ANT_SEL3"),
> +               MTK_FUNCTION(6, "I2S2_BCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[20]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(19, "EINT19"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 19),
> +               MTK_FUNCTION(0, "GPIO19"),
> +               MTK_FUNCTION(1, "UCTS1"),
> +               MTK_FUNCTION(2, "IDDIG"),
> +               MTK_FUNCTION(3, "I2S3_BCK"),
> +               MTK_FUNCTION(4, "CLKM2"),
> +               MTK_FUNCTION(5, "ANT_SEL4"),
> +               MTK_FUNCTION(6, "I2S2_DI"),
> +               MTK_FUNCTION(7, "DBG_MON_A[21]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(20, "EINT20"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 20),
> +               MTK_FUNCTION(0, "GPIO20"),
> +               MTK_FUNCTION(1, "URTS1"),
> +               MTK_FUNCTION(3, "I2S3_DO"),
> +               MTK_FUNCTION(4, "CLKM3"),
> +               MTK_FUNCTION(5, "ANT_SEL5"),
> +               MTK_FUNCTION(6, "I2S2_LRCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[22]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(21, "EINT21"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 21),
> +               MTK_FUNCTION(0, "GPIO21"),
> +               MTK_FUNCTION(1, "NRNB"),
> +               MTK_FUNCTION(2, "ANT_SEL0"),
> +               MTK_FUNCTION(3, "I2S_8CH_DO4"),
> +               MTK_FUNCTION(7, "DBG_MON_B[31]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(22, "EINT22"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 22),
> +               MTK_FUNCTION(0, "GPIO22"),
> +               MTK_FUNCTION(2, "I2S_8CH_DO2"),
> +               MTK_FUNCTION(3, "TSF_IN"),
> +               MTK_FUNCTION(4, "USB_DRVVBUS"),
> +               MTK_FUNCTION(5, "SPDIF_OUT"),
> +               MTK_FUNCTION(6, "NRE_C"),
> +               MTK_FUNCTION(7, "DBG_MON_B[12]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(23, "EINT23"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 23),
> +               MTK_FUNCTION(0, "GPIO23"),
> +               MTK_FUNCTION(2, "I2S_8CH_DO3"),
> +               MTK_FUNCTION(3, "CLKM0"),
> +               MTK_FUNCTION(4, "IR"),
> +               MTK_FUNCTION(5, "SPDIF_IN"),
> +               MTK_FUNCTION(6, "NDQS_C"),
> +               MTK_FUNCTION(7, "DBG_MON_B[13]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(24, "EINT24"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 24),
> +               MTK_FUNCTION(0, "GPIO24"),
> +               MTK_FUNCTION(3, "ANT_SEL1"),
> +               MTK_FUNCTION(4, "UCTS2"),
> +               MTK_FUNCTION(5, "PWM_A"),
> +               MTK_FUNCTION(6, "I2S0_MCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[0]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(25, "EINT25"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 25),
> +               MTK_FUNCTION(0, "GPIO25"),
> +               MTK_FUNCTION(3, "ANT_SEL0"),
> +               MTK_FUNCTION(4, "URTS2"),
> +               MTK_FUNCTION(5, "PWM_B"),
> +               MTK_FUNCTION(6, "I2S_8CH_MCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[1]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(26, "PWRAP_SPI0_MI"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 26),
> +               MTK_FUNCTION(0, "GPIO26"),
> +               MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
> +               MTK_FUNCTION(2, "PWRAP_SPI0_MI")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(27, "PWRAP_SPI0_MO"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 27),
> +               MTK_FUNCTION(0, "GPIO27"),
> +               MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
> +               MTK_FUNCTION(2, "PWRAP_SPI0_MO")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(28, "PWRAP_INT"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 28),
> +               MTK_FUNCTION(0, "GPIO28"),
> +               MTK_FUNCTION(1, "I2S0_MCK"),
> +               MTK_FUNCTION(4, "I2S_8CH_MCK"),
> +               MTK_FUNCTION(5, "I2S2_MCK"),
> +               MTK_FUNCTION(6, "I2S3_MCK")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(29, "PWRAP_SPI0_CK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 29),
> +               MTK_FUNCTION(0, "GPIO29"),
> +               MTK_FUNCTION(1, "PWRAP_SPI0_CK")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(30, "PWRAP_SPI0_CSN"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 30),
> +               MTK_FUNCTION(0, "GPIO30"),
> +               MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(31, "RTC32K_CK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 31),
> +               MTK_FUNCTION(0, "GPIO31"),
> +               MTK_FUNCTION(1, "RTC32K_CK")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(32, "WATCHDOG"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 32),
> +               MTK_FUNCTION(0, "GPIO32"),
> +               MTK_FUNCTION(1, "WATCHDOG")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(33, "SRCLKENA"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 33),
> +               MTK_FUNCTION(0, "GPIO33"),
> +               MTK_FUNCTION(1, "SRCLKENA0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(34, "URXD2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 34),
> +               MTK_FUNCTION(0, "GPIO34"),
> +               MTK_FUNCTION(1, "URXD2"),
> +               MTK_FUNCTION(3, "UTXD2"),
> +               MTK_FUNCTION(4, "DBG_SCL"),
> +               MTK_FUNCTION(6, "I2S2_MCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[0]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(35, "UTXD2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 35),
> +               MTK_FUNCTION(0, "GPIO35"),
> +               MTK_FUNCTION(1, "UTXD2"),
> +               MTK_FUNCTION(3, "URXD2"),
> +               MTK_FUNCTION(4, "DBG_SDA"),
> +               MTK_FUNCTION(6, "I2S3_MCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[1]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(36, "MRG_CLK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 36),
> +               MTK_FUNCTION(0, "GPIO36"),
> +               MTK_FUNCTION(1, "MRG_CLK"),
> +               MTK_FUNCTION(3, "I2S0_BCK"),
> +               MTK_FUNCTION(4, "I2S3_BCK"),
> +               MTK_FUNCTION(5, "PCM0_CLK"),
> +               MTK_FUNCTION(6, "IR"),
> +               MTK_FUNCTION(7, "DBG_MON_A[2]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(37, "MRG_SYNC"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 37),
> +               MTK_FUNCTION(0, "GPIO37"),
> +               MTK_FUNCTION(1, "MRG_SYNC"),
> +               MTK_FUNCTION(3, "I2S0_LRCK"),
> +               MTK_FUNCTION(4, "I2S3_LRCK"),
> +               MTK_FUNCTION(5, "PCM0_SYNC"),
> +               MTK_FUNCTION(6, "EXT_COL"),
> +               MTK_FUNCTION(7, "DBG_MON_A[3]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(38, "MRG_DI"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 38),
> +               MTK_FUNCTION(0, "GPIO38"),
> +               MTK_FUNCTION(1, "MRG_DI"),
> +               MTK_FUNCTION(3, "I2S0_DI"),
> +               MTK_FUNCTION(4, "I2S3_DO"),
> +               MTK_FUNCTION(5, "PCM0_DI"),
> +               MTK_FUNCTION(6, "EXT_MDIO"),
> +               MTK_FUNCTION(7, "DBG_MON_A[4]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(39, "MRG_DO"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 39),
> +               MTK_FUNCTION(0, "GPIO39"),
> +               MTK_FUNCTION(1, "MRG_DO"),
> +               MTK_FUNCTION(3, "I2S0_MCK"),
> +               MTK_FUNCTION(4, "I2S3_MCK"),
> +               MTK_FUNCTION(5, "PCM0_DO"),
> +               MTK_FUNCTION(6, "EXT_MDC"),
> +               MTK_FUNCTION(7, "DBG_MON_A[5]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(40, "KPROW0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 40),
> +               MTK_FUNCTION(0, "GPIO40"),
> +               MTK_FUNCTION(1, "KPROW0"),
> +               MTK_FUNCTION(7, "DBG_MON_B[4]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(41, "KPROW1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 41),
> +               MTK_FUNCTION(0, "GPIO41"),
> +               MTK_FUNCTION(1, "KPROW1"),
> +               MTK_FUNCTION(2, "IDDIG"),
> +               MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
> +               MTK_FUNCTION(7, "DBG_MON_B[5]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(42, "KPCOL0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 42),
> +               MTK_FUNCTION(0, "GPIO42"),
> +               MTK_FUNCTION(1, "KPCOL0"),
> +               MTK_FUNCTION(7, "DBG_MON_B[6]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(43, "KPCOL1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 43),
> +               MTK_FUNCTION(0, "GPIO43"),
> +               MTK_FUNCTION(1, "KPCOL1"),
> +               MTK_FUNCTION(2, "USB_DRVVBUS"),
> +               MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
> +               MTK_FUNCTION(4, "TSF_IN"),
> +               MTK_FUNCTION(7, "DBG_MON_B[7]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(44, "JTMS"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 44),
> +               MTK_FUNCTION(0, "GPIO44"),
> +               MTK_FUNCTION(1, "JTMS"),
> +               MTK_FUNCTION(2, "CONN_MCU_TMS"),
> +               MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(45, "JTCK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 45),
> +               MTK_FUNCTION(0, "GPIO45"),
> +               MTK_FUNCTION(1, "JTCK"),
> +               MTK_FUNCTION(2, "CONN_MCU_TCK"),
> +               MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(46, "JTDI"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 46),
> +               MTK_FUNCTION(0, "GPIO46"),
> +               MTK_FUNCTION(1, "JTDI"),
> +               MTK_FUNCTION(2, "CONN_MCU_TDI")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(47, "JTDO"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 47),
> +               MTK_FUNCTION(0, "GPIO47"),
> +               MTK_FUNCTION(1, "JTDO"),
> +               MTK_FUNCTION(2, "CONN_MCU_TDO")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(48, "SPI_CS"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 48),
> +               MTK_FUNCTION(0, "GPIO48"),
> +               MTK_FUNCTION(1, "SPI_CSB"),
> +               MTK_FUNCTION(3, "I2S0_DI"),
> +               MTK_FUNCTION(4, "I2S2_BCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[23]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(49, "SPI_CK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 49),
> +               MTK_FUNCTION(0, "GPIO49"),
> +               MTK_FUNCTION(1, "SPI_CLK"),
> +               MTK_FUNCTION(3, "I2S0_LRCK"),
> +               MTK_FUNCTION(4, "I2S2_DI"),
> +               MTK_FUNCTION(7, "DBG_MON_A[24]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(50, "SPI_MI"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 50),
> +               MTK_FUNCTION(0, "GPIO50"),
> +               MTK_FUNCTION(1, "SPI_MI"),
> +               MTK_FUNCTION(2, "SPI_MO"),
> +               MTK_FUNCTION(3, "I2S0_BCK"),
> +               MTK_FUNCTION(4, "I2S2_LRCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[25]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(51, "SPI_MO"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 51),
> +               MTK_FUNCTION(0, "GPIO51"),
> +               MTK_FUNCTION(1, "SPI_MO"),
> +               MTK_FUNCTION(2, "SPI_MI"),
> +               MTK_FUNCTION(3, "I2S0_MCK"),
> +               MTK_FUNCTION(4, "I2S2_MCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[26]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(52, "SDA1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 52),
> +               MTK_FUNCTION(0, "GPIO52"),
> +               MTK_FUNCTION(1, "SDA1_0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(53, "SCL1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 53),
> +               MTK_FUNCTION(0, "GPIO53"),
> +               MTK_FUNCTION(1, "SCL1_0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(54, "GPIO54"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 54),
> +               MTK_FUNCTION(0, "GPIO54"),
> +               MTK_FUNCTION(2, "PWM_B"),
> +               MTK_FUNCTION(7, "DBG_MON_B[2]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(55, "I2S_DATA_IN"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 55),
> +               MTK_FUNCTION(0, "GPIO55"),
> +               MTK_FUNCTION(1, "I2S0_DI"),
> +               MTK_FUNCTION(2, "UCTS0"),
> +               MTK_FUNCTION(3, "I2S3_DO"),
> +               MTK_FUNCTION(4, "I2S_8CH_DO1"),
> +               MTK_FUNCTION(5, "PWM_A"),
> +               MTK_FUNCTION(6, "I2S2_BCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[28]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(56, "I2S_LRCK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 56),
> +               MTK_FUNCTION(0, "GPIO56"),
> +               MTK_FUNCTION(1, "I2S0_LRCK"),
> +               MTK_FUNCTION(3, "I2S3_LRCK"),
> +               MTK_FUNCTION(4, "I2S_8CH_LRCK"),
> +               MTK_FUNCTION(5, "PWM_B"),
> +               MTK_FUNCTION(6, "I2S2_DI"),
> +               MTK_FUNCTION(7, "DBG_MON_A[29]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(57, "I2S_BCK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 57),
> +               MTK_FUNCTION(0, "GPIO57"),
> +               MTK_FUNCTION(1, "I2S0_BCK"),
> +               MTK_FUNCTION(2, "URTS0"),
> +               MTK_FUNCTION(3, "I2S3_BCK"),
> +               MTK_FUNCTION(4, "I2S_8CH_BCK"),
> +               MTK_FUNCTION(5, "PWM_C"),
> +               MTK_FUNCTION(6, "I2S2_LRCK"),
> +               MTK_FUNCTION(7, "DBG_MON_A[30]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(58, "SDA0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 58),
> +               MTK_FUNCTION(0, "GPIO58"),
> +               MTK_FUNCTION(1, "SDA0_0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(59, "SCL0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 59),
> +               MTK_FUNCTION(0, "GPIO59"),
> +               MTK_FUNCTION(1, "SCL0_0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(60, "SDA2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 60),
> +               MTK_FUNCTION(0, "GPIO60"),
> +               MTK_FUNCTION(1, "SDA2_0"),
> +               MTK_FUNCTION(2, "PWM_B")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(61, "SCL2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 61),
> +               MTK_FUNCTION(0, "GPIO61"),
> +               MTK_FUNCTION(1, "SCL2_0"),
> +               MTK_FUNCTION(2, "PWM_C")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(62, "URXD0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 62),
> +               MTK_FUNCTION(0, "GPIO62"),
> +               MTK_FUNCTION(1, "URXD0"),
> +               MTK_FUNCTION(2, "UTXD0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(63, "UTXD0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 63),
> +               MTK_FUNCTION(0, "GPIO63"),
> +               MTK_FUNCTION(1, "UTXD0"),
> +               MTK_FUNCTION(2, "URXD0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(64, "URXD1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 64),
> +               MTK_FUNCTION(0, "GPIO64"),
> +               MTK_FUNCTION(1, "URXD1"),
> +               MTK_FUNCTION(2, "UTXD1"),
> +               MTK_FUNCTION(7, "DBG_MON_A[27]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(65, "UTXD1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 65),
> +               MTK_FUNCTION(0, "GPIO65"),
> +               MTK_FUNCTION(1, "UTXD1"),
> +               MTK_FUNCTION(2, "URXD1"),
> +               MTK_FUNCTION(7, "DBG_MON_A[31]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(66, "LCM_RST"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 66),
> +               MTK_FUNCTION(0, "GPIO66"),
> +               MTK_FUNCTION(1, "LCM_RST"),
> +               MTK_FUNCTION(3, "I2S0_MCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[3]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(67, "GPIO67"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 67),
> +               MTK_FUNCTION(0, "GPIO67"),
> +               MTK_FUNCTION(3, "I2S_8CH_MCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[14]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(68, "MSDC2_CMD"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 68),
> +               MTK_FUNCTION(0, "GPIO68"),
> +               MTK_FUNCTION(1, "MSDC2_CMD"),
> +               MTK_FUNCTION(2, "I2S_8CH_DO4"),
> +               MTK_FUNCTION(3, "SDA1_0"),
> +               MTK_FUNCTION(5, "USB_SDA"),
> +               MTK_FUNCTION(6, "I2S3_BCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[15]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(69, "MSDC2_CLK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 69),
> +               MTK_FUNCTION(0, "GPIO69"),
> +               MTK_FUNCTION(1, "MSDC2_CLK"),
> +               MTK_FUNCTION(2, "I2S_8CH_DO3"),
> +               MTK_FUNCTION(3, "SCL1_0"),
> +               MTK_FUNCTION(5, "USB_SCL"),
> +               MTK_FUNCTION(6, "I2S3_LRCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[16]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(70, "MSDC2_DAT0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 70),
> +               MTK_FUNCTION(0, "GPIO70"),
> +               MTK_FUNCTION(1, "MSDC2_DAT0"),
> +               MTK_FUNCTION(2, "I2S_8CH_DO2"),
> +               MTK_FUNCTION(5, "UTXD0"),
> +               MTK_FUNCTION(6, "I2S3_DO"),
> +               MTK_FUNCTION(7, "DBG_MON_B[17]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(71, "MSDC2_DAT1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 71),
> +               MTK_FUNCTION(0, "GPIO71"),
> +               MTK_FUNCTION(1, "MSDC2_DAT1"),
> +               MTK_FUNCTION(2, "I2S_8CH_DO1"),
> +               MTK_FUNCTION(3, "PWM_A"),
> +               MTK_FUNCTION(4, "I2S3_MCK"),
> +               MTK_FUNCTION(5, "URXD0"),
> +               MTK_FUNCTION(6, "PWM_B"),
> +               MTK_FUNCTION(7, "DBG_MON_B[18]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(72, "MSDC2_DAT2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 72),
> +               MTK_FUNCTION(0, "GPIO72"),
> +               MTK_FUNCTION(1, "MSDC2_DAT2"),
> +               MTK_FUNCTION(2, "I2S_8CH_LRCK"),
> +               MTK_FUNCTION(3, "SDA2_0"),
> +               MTK_FUNCTION(5, "UTXD1"),
> +               MTK_FUNCTION(6, "PWM_C"),
> +               MTK_FUNCTION(7, "DBG_MON_B[19]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(73, "MSDC2_DAT3"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 73),
> +               MTK_FUNCTION(0, "GPIO73"),
> +               MTK_FUNCTION(1, "MSDC2_DAT3"),
> +               MTK_FUNCTION(2, "I2S_8CH_BCK"),
> +               MTK_FUNCTION(3, "SCL2_0"),
> +               MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
> +               MTK_FUNCTION(5, "URXD1"),
> +               MTK_FUNCTION(6, "PWM_A"),
> +               MTK_FUNCTION(7, "DBG_MON_B[20]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(74, "TDN3"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 74),
> +               MTK_FUNCTION(0, "GPIO74"),
> +               MTK_FUNCTION(1, "TDN3")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(75, "TDP3"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 75),
> +               MTK_FUNCTION(0, "GPIO75"),
> +               MTK_FUNCTION(1, "TDP3")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(76, "TDN2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 76),
> +               MTK_FUNCTION(0, "GPIO76"),
> +               MTK_FUNCTION(1, "TDN2")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(77, "TDP2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 77),
> +               MTK_FUNCTION(0, "GPIO77"),
> +               MTK_FUNCTION(1, "TDP2")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(78, "TCN"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 78),
> +               MTK_FUNCTION(0, "GPIO78"),
> +               MTK_FUNCTION(1, "TCN")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(79, "TCP"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 79),
> +               MTK_FUNCTION(0, "GPIO79"),
> +               MTK_FUNCTION(1, "TCP")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(80, "TDN1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 80),
> +               MTK_FUNCTION(0, "GPIO80"),
> +               MTK_FUNCTION(1, "TDN1")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(81, "TDP1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 81),
> +               MTK_FUNCTION(0, "GPIO81"),
> +               MTK_FUNCTION(1, "TDP1")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(82, "TDN0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 82),
> +               MTK_FUNCTION(0, "GPIO82"),
> +               MTK_FUNCTION(1, "TDN0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(83, "TDP0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 83),
> +               MTK_FUNCTION(0, "GPIO83"),
> +               MTK_FUNCTION(1, "TDP0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(84, "RDN0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 84),
> +               MTK_FUNCTION(0, "GPIO84"),
> +               MTK_FUNCTION(1, "RDN0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(85, "RDP0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 85),
> +               MTK_FUNCTION(0, "GPIO85"),
> +               MTK_FUNCTION(1, "RDP0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(86, "RDN1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 86),
> +               MTK_FUNCTION(0, "GPIO86"),
> +               MTK_FUNCTION(1, "RDN1")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(87, "RDP1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 87),
> +               MTK_FUNCTION(0, "GPIO87"),
> +               MTK_FUNCTION(1, "RDP1")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(88, "RCN"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 88),
> +               MTK_FUNCTION(0, "GPIO88"),
> +               MTK_FUNCTION(1, "RCN")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(89, "RCP"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 89),
> +               MTK_FUNCTION(0, "GPIO89"),
> +               MTK_FUNCTION(1, "RCP")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(90, "RDN2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 90),
> +               MTK_FUNCTION(0, "GPIO90"),
> +               MTK_FUNCTION(1, "RDN2"),
> +               MTK_FUNCTION(2, "CMDAT8")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(91, "RDP2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 91),
> +               MTK_FUNCTION(0, "GPIO91"),
> +               MTK_FUNCTION(1, "RDP2"),
> +               MTK_FUNCTION(2, "CMDAT9")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(92, "RDN3"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 92),
> +               MTK_FUNCTION(0, "GPIO92"),
> +               MTK_FUNCTION(1, "RDN3"),
> +               MTK_FUNCTION(2, "CMDAT4")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(93, "RDP3"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 93),
> +               MTK_FUNCTION(0, "GPIO93"),
> +               MTK_FUNCTION(1, "RDP3"),
> +               MTK_FUNCTION(2, "CMDAT5")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(94, "RCN_A"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 94),
> +               MTK_FUNCTION(0, "GPIO94"),
> +               MTK_FUNCTION(1, "RCN_A"),
> +               MTK_FUNCTION(2, "CMDAT6")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(95, "RCP_A"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 95),
> +               MTK_FUNCTION(0, "GPIO95"),
> +               MTK_FUNCTION(1, "RCP_A"),
> +               MTK_FUNCTION(2, "CMDAT7")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(96, "RDN1_A"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 96),
> +               MTK_FUNCTION(0, "GPIO96"),
> +               MTK_FUNCTION(1, "RDN1_A"),
> +               MTK_FUNCTION(2, "CMDAT2"),
> +               MTK_FUNCTION(3, "CMCSD2")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(97, "RDP1_A"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 97),
> +               MTK_FUNCTION(0, "GPIO97"),
> +               MTK_FUNCTION(1, "RDP1_A"),
> +               MTK_FUNCTION(2, "CMDAT3"),
> +               MTK_FUNCTION(3, "CMCSD3")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(98, "RDN0_A"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 98),
> +               MTK_FUNCTION(0, "GPIO98"),
> +               MTK_FUNCTION(1, "RDN0_A"),
> +               MTK_FUNCTION(2, "CMHSYNC")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(99, "RDP0_A"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 99),
> +               MTK_FUNCTION(0, "GPIO99"),
> +               MTK_FUNCTION(1, "RDP0_A"),
> +               MTK_FUNCTION(2, "CMVSYNC")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(100, "CMDAT0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 100),
> +               MTK_FUNCTION(0, "GPIO100"),
> +               MTK_FUNCTION(1, "CMDAT0"),
> +               MTK_FUNCTION(2, "CMCSD0"),
> +               MTK_FUNCTION(3, "ANT_SEL2"),
> +               MTK_FUNCTION(5, "TDM_RX_MCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[21]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(101, "CMDAT1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 101),
> +               MTK_FUNCTION(0, "GPIO101"),
> +               MTK_FUNCTION(1, "CMDAT1"),
> +               MTK_FUNCTION(2, "CMCSD1"),
> +               MTK_FUNCTION(3, "ANT_SEL3"),
> +               MTK_FUNCTION(4, "CMFLASH"),
> +               MTK_FUNCTION(5, "TDM_RX_BCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[22]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(102, "CMMCLK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 102),
> +               MTK_FUNCTION(0, "GPIO102"),
> +               MTK_FUNCTION(1, "CMMCLK"),
> +               MTK_FUNCTION(3, "ANT_SEL4"),
> +               MTK_FUNCTION(5, "TDM_RX_LRCK"),
> +               MTK_FUNCTION(7, "DBG_MON_B[23]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(103, "CMPCLK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 103),
> +               MTK_FUNCTION(0, "GPIO103"),
> +               MTK_FUNCTION(1, "CMPCLK"),
> +               MTK_FUNCTION(2, "CMCSK"),
> +               MTK_FUNCTION(3, "ANT_SEL5"),
> +               MTK_FUNCTION(5, " TDM_RX_DI"),
> +               MTK_FUNCTION(7, "DBG_MON_B[24]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(104, "MSDC1_CMD"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 104),
> +               MTK_FUNCTION(0, "GPIO104"),
> +               MTK_FUNCTION(1, "MSDC1_CMD"),
> +               MTK_FUNCTION(4, "SQICS"),
> +               MTK_FUNCTION(7, "DBG_MON_B[25]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(105, "MSDC1_CLK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 105),
> +               MTK_FUNCTION(0, "GPIO105"),
> +               MTK_FUNCTION(1, "MSDC1_CLK"),
> +               MTK_FUNCTION(4, "SQISO"),
> +               MTK_FUNCTION(7, "DBG_MON_B[26]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(106, "MSDC1_DAT0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 106),
> +               MTK_FUNCTION(0, "GPIO106"),
> +               MTK_FUNCTION(1, "MSDC1_DAT0"),
> +               MTK_FUNCTION(4, "SQISI"),
> +               MTK_FUNCTION(7, "DBG_MON_B[27]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(107, "MSDC1_DAT1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 107),
> +               MTK_FUNCTION(0, "GPIO107"),
> +               MTK_FUNCTION(1, "MSDC1_DAT1"),
> +               MTK_FUNCTION(4, "SQIWP"),
> +               MTK_FUNCTION(7, "DBG_MON_B[28]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(108, "MSDC1_DAT2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 108),
> +               MTK_FUNCTION(0, "GPIO108"),
> +               MTK_FUNCTION(1, "MSDC1_DAT2"),
> +               MTK_FUNCTION(4, "SQIRST"),
> +               MTK_FUNCTION(7, "DBG_MON_B[29]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(109, "MSDC1_DAT3"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 109),
> +               MTK_FUNCTION(0, "GPIO109"),
> +               MTK_FUNCTION(1, "MSDC1_DAT3"),
> +               MTK_FUNCTION(4, "SQICK"), /* WIP */
> +               MTK_FUNCTION(7, "DBG_MON_B[30]")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(110, "MSDC0_DAT7"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 110),
> +               MTK_FUNCTION(0, "GPIO110"),
> +               MTK_FUNCTION(1, "MSDC0_DAT7"),
> +               MTK_FUNCTION(4, "NLD7")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(111, "MSDC0_DAT6"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 111),
> +               MTK_FUNCTION(0, "GPIO111"),
> +               MTK_FUNCTION(1, "MSDC0_DAT6"),
> +               MTK_FUNCTION(4, "NLD6")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(112, "MSDC0_DAT5"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 112),
> +               MTK_FUNCTION(0, "GPIO112"),
> +               MTK_FUNCTION(1, "MSDC0_DAT5"),
> +               MTK_FUNCTION(4, "NLD4")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(113, "MSDC0_DAT4"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 113),
> +               MTK_FUNCTION(0, "GPIO113"),
> +               MTK_FUNCTION(1, "MSDC0_DAT4"),
> +               MTK_FUNCTION(4, "NLD3")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(114, "MSDC0_RSTB"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 114),
> +               MTK_FUNCTION(0, "GPIO114"),
> +               MTK_FUNCTION(1, "MSDC0_RSTB"),
> +               MTK_FUNCTION(4, "NLD0")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(115, "MSDC0_CMD"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 115),
> +               MTK_FUNCTION(0, "GPIO115"),
> +               MTK_FUNCTION(1, "MSDC0_CMD"),
> +               MTK_FUNCTION(4, "NALE")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(116, "MSDC0_CLK"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 116),
> +               MTK_FUNCTION(0, "GPIO116"),
> +               MTK_FUNCTION(1, "MSDC0_CLK"),
> +               MTK_FUNCTION(4, "NWEB")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(117, "MSDC0_DAT3"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 117),
> +               MTK_FUNCTION(0, "GPIO117"),
> +               MTK_FUNCTION(1, "MSDC0_DAT3"),
> +               MTK_FUNCTION(4, "NLD1")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(118, "MSDC0_DAT2"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 118),
> +               MTK_FUNCTION(0, "GPIO118"),
> +               MTK_FUNCTION(1, "MSDC0_DAT2"),
> +               MTK_FUNCTION(4, "NLD5")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(119, "MSDC0_DAT1"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 119),
> +               MTK_FUNCTION(0, "GPIO119"),
> +               MTK_FUNCTION(1, "MSDC0_DAT1"),
> +               MTK_FUNCTION(4, "NLD8")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(120, "MSDC0_DAT0"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 120),
> +               MTK_FUNCTION(0, "GPIO120"),
> +               MTK_FUNCTION(1, "MSDC0_DAT0"),
> +               MTK_FUNCTION(4, "WATCHDOG"),
> +               MTK_FUNCTION(5, "NLD2")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(121, "GPIO121"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 121),
> +               MTK_FUNCTION(0, "GPIO121")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(122, "GPIO122"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 122),
> +               MTK_FUNCTION(0, "GPIO122")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(123, "GPIO123"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 123),
> +               MTK_FUNCTION(0, "GPIO123")
> +       ),
> +       MTK_PIN(
> +               PINCTRL_PIN(124, "GPIO124"),
> +               NULL, "mt8516",
> +               MTK_EINT_FUNCTION(0, 124),
> +               MTK_FUNCTION(0, "GPIO124")
> +       ),
> +};
> +
> +#endif /* __PINCTRL_MTK_MT8516_H */
> --
> 2.20.1
>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support for MT8516
  2019-03-23 21:16 ` [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support " Fabien Parent
  2019-03-28 19:11   ` Rob Herring
@ 2019-04-08 20:44   ` Linus Walleij
  2019-04-16  9:12     ` Matthias Brugger
  1 sibling, 1 reply; 70+ messages in thread
From: Linus Walleij @ 2019-04-08 20:44 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Rob Herring, Mark Rutland, Sean Wang,
	Ryder Lee, hsin-hsiung.wang, wenzhen.yu, Chaotian Jing, Yong Mao,
	jjian.zhou,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	linux-kernel, linux-i2c, Linux ARM,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, linux-serial, linux-spi, LINUXWATCHDOG,
	linux-clk, stephane.leprovost

On Sat, Mar 23, 2019 at 10:17 PM Fabien Parent <fparent@baylibre.com> wrote:

> Add binding documentation of pinctrl-mt65xx for MT8516 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>

Patch applied with Rob's ACK.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 03/24] dt-bindings: pwrap: mediatek: add pwrap support for MT8516
  2019-03-23 21:15 ` [PATCH 03/24] dt-bindings: pwrap: mediatek: add pwrap support for MT8516 Fabien Parent
  2019-03-28 19:09   ` Rob Herring
@ 2019-04-12 17:44   ` Matthias Brugger
  1 sibling, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-12 17:44 UTC (permalink / raw)
  To: Fabien Parent, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 23/03/2019 22:15, Fabien Parent wrote:
> Add binding documentation of pwrap for MT8516 SoCs.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
>  1 file changed, 1 insertion(+)

applied to v5.1-next/soc

Thanks!

> 
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> index 5a2ef1726e2a..7a32404c6114 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
> @@ -25,6 +25,7 @@ Required properties in pwrap device node.
>  	"mediatek,mt8135-pwrap" for MT8135 SoCs
>  	"mediatek,mt8173-pwrap" for MT8173 SoCs
>  	"mediatek,mt8183-pwrap" for MT8183 SoCs
> +	"mediatek,mt8516-pwrap" for MT8516 SoCs
>  - interrupts: IRQ for pwrap in SOC
>  - reg-names: Must include the following entries:
>    "pwrap": Main registers base
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 04/24] soc: mediatek: pwrap: add missing check on rstc
  2019-03-23 21:15 ` [PATCH 04/24] soc: mediatek: pwrap: add missing check on rstc Fabien Parent
@ 2019-04-12 17:44   ` Matthias Brugger
  0 siblings, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-12 17:44 UTC (permalink / raw)
  To: Fabien Parent, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 23/03/2019 22:15, Fabien Parent wrote:
> The variable rstc is set only when the SoC PWRAP have the
> PWRAP_CAP_RESET capability. Check whether rstc is set before
> using it to avoid errors.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  drivers/soc/mediatek/mtk-pmic-wrap.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

applied to v5.1-next/soc

Thanks!

> 
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index 8236a6c87e19..b3ba2301f569 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -1478,7 +1478,8 @@ static int pwrap_init(struct pmic_wrapper *wrp)
>  {
>  	int ret;
>  
> -	reset_control_reset(wrp->rstc);
> +	if (wrp->rstc)
> +		reset_control_reset(wrp->rstc);
>  	if (wrp->rstc_bridge)
>  		reset_control_reset(wrp->rstc_bridge);
>  
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 05/24] soc: mediatek: pwrap: add support for MT8516 pwrap
  2019-03-23 21:15 ` [PATCH 05/24] soc: mediatek: pwrap: add support for MT8516 pwrap Fabien Parent
@ 2019-04-12 17:44   ` Matthias Brugger
  0 siblings, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-12 17:44 UTC (permalink / raw)
  To: Fabien Parent, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 23/03/2019 22:15, Fabien Parent wrote:
> Add the code to support the pwrap IP on the MediaTek MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  drivers/soc/mediatek/mtk-pmic-wrap.c | 106 +++++++++++++++++++++++++++
>  1 file changed, 106 insertions(+)

applied to v5.1-next/soc

Thanks!

> 
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index b3ba2301f569..73f0be0567bd 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -381,6 +381,10 @@ enum pwrap_regs {
>  	PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
>  	PWRAP_GPSINF_0_STA,
>  	PWRAP_GPSINF_1_STA,
> +
> +	/* MT8516 only regs */
> +	PWRAP_OP_TYPE,
> +	PWRAP_MSB_FIRST,
>  };
>  
>  static int mt2701_regs[] = {
> @@ -852,6 +856,91 @@ static int mt8183_regs[] = {
>  	[PWRAP_WACS2_VLDCLR] =			0xC28,
>  };
>  
> +static int mt8516_regs[] = {
> +	[PWRAP_MUX_SEL] =		0x0,
> +	[PWRAP_WRAP_EN] =		0x4,
> +	[PWRAP_DIO_EN] =		0x8,
> +	[PWRAP_SIDLY] =			0xc,
> +	[PWRAP_RDDMY] =			0x10,
> +	[PWRAP_SI_CK_CON] =		0x14,
> +	[PWRAP_CSHEXT_WRITE] =		0x18,
> +	[PWRAP_CSHEXT_READ] =		0x1c,
> +	[PWRAP_CSLEXT_START] =		0x20,
> +	[PWRAP_CSLEXT_END] =		0x24,
> +	[PWRAP_STAUPD_PRD] =		0x28,
> +	[PWRAP_STAUPD_GRPEN] =		0x2c,
> +	[PWRAP_STAUPD_MAN_TRIG] =	0x40,
> +	[PWRAP_STAUPD_STA] =		0x44,
> +	[PWRAP_WRAP_STA] =		0x48,
> +	[PWRAP_HARB_INIT] =		0x4c,
> +	[PWRAP_HARB_HPRIO] =		0x50,
> +	[PWRAP_HIPRIO_ARB_EN] =		0x54,
> +	[PWRAP_HARB_STA0] =		0x58,
> +	[PWRAP_HARB_STA1] =		0x5c,
> +	[PWRAP_MAN_EN] =		0x60,
> +	[PWRAP_MAN_CMD] =		0x64,
> +	[PWRAP_MAN_RDATA] =		0x68,
> +	[PWRAP_MAN_VLDCLR] =		0x6c,
> +	[PWRAP_WACS0_EN] =		0x70,
> +	[PWRAP_INIT_DONE0] =		0x74,
> +	[PWRAP_WACS0_CMD] =		0x78,
> +	[PWRAP_WACS0_RDATA] =		0x7c,
> +	[PWRAP_WACS0_VLDCLR] =		0x80,
> +	[PWRAP_WACS1_EN] =		0x84,
> +	[PWRAP_INIT_DONE1] =		0x88,
> +	[PWRAP_WACS1_CMD] =		0x8c,
> +	[PWRAP_WACS1_RDATA] =		0x90,
> +	[PWRAP_WACS1_VLDCLR] =		0x94,
> +	[PWRAP_WACS2_EN] =		0x98,
> +	[PWRAP_INIT_DONE2] =		0x9c,
> +	[PWRAP_WACS2_CMD] =		0xa0,
> +	[PWRAP_WACS2_RDATA] =		0xa4,
> +	[PWRAP_WACS2_VLDCLR] =		0xa8,
> +	[PWRAP_INT_EN] =		0xac,
> +	[PWRAP_INT_FLG_RAW] =		0xb0,
> +	[PWRAP_INT_FLG] =		0xb4,
> +	[PWRAP_INT_CLR] =		0xb8,
> +	[PWRAP_SIG_ADR] =		0xbc,
> +	[PWRAP_SIG_MODE] =		0xc0,
> +	[PWRAP_SIG_VALUE] =		0xc4,
> +	[PWRAP_SIG_ERRVAL] =		0xc8,
> +	[PWRAP_CRC_EN] =		0xcc,
> +	[PWRAP_TIMER_EN] =		0xd0,
> +	[PWRAP_TIMER_STA] =		0xd4,
> +	[PWRAP_WDT_UNIT] =		0xd8,
> +	[PWRAP_WDT_SRC_EN] =		0xdc,
> +	[PWRAP_WDT_FLG] =		0xe0,
> +	[PWRAP_DEBUG_INT_SEL] =		0xe4,
> +	[PWRAP_DVFS_ADR0] =		0xe8,
> +	[PWRAP_DVFS_WDATA0] =		0xec,
> +	[PWRAP_DVFS_ADR1] =		0xf0,
> +	[PWRAP_DVFS_WDATA1] =		0xf4,
> +	[PWRAP_DVFS_ADR2] =		0xf8,
> +	[PWRAP_DVFS_WDATA2] =		0xfc,
> +	[PWRAP_DVFS_ADR3] =		0x100,
> +	[PWRAP_DVFS_WDATA3] =		0x104,
> +	[PWRAP_DVFS_ADR4] =		0x108,
> +	[PWRAP_DVFS_WDATA4] =		0x10c,
> +	[PWRAP_DVFS_ADR5] =		0x110,
> +	[PWRAP_DVFS_WDATA5] =		0x114,
> +	[PWRAP_DVFS_ADR6] =		0x118,
> +	[PWRAP_DVFS_WDATA6] =		0x11c,
> +	[PWRAP_DVFS_ADR7] =		0x120,
> +	[PWRAP_DVFS_WDATA7] =		0x124,
> +	[PWRAP_SPMINF_STA] =		0x128,
> +	[PWRAP_CIPHER_KEY_SEL] =	0x12c,
> +	[PWRAP_CIPHER_IV_SEL] =		0x130,
> +	[PWRAP_CIPHER_EN] =		0x134,
> +	[PWRAP_CIPHER_RDY] =		0x138,
> +	[PWRAP_CIPHER_MODE] =		0x13c,
> +	[PWRAP_CIPHER_SWRST] =		0x140,
> +	[PWRAP_DCM_EN] =		0x144,
> +	[PWRAP_DCM_DBC_PRD] =		0x148,
> +	[PWRAP_SW_RST] =		0x168,
> +	[PWRAP_OP_TYPE] =		0x16c,
> +	[PWRAP_MSB_FIRST] =		0x170,
> +};
> +
>  enum pmic_type {
>  	PMIC_MT6323,
>  	PMIC_MT6351,
> @@ -869,6 +958,7 @@ enum pwrap_type {
>  	PWRAP_MT8135,
>  	PWRAP_MT8173,
>  	PWRAP_MT8183,
> +	PWRAP_MT8516,
>  };
>  
>  struct pmic_wrapper;
> @@ -1297,6 +1387,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
>  	case PWRAP_MT6765:
>  	case PWRAP_MT6797:
>  	case PWRAP_MT8173:
> +	case PWRAP_MT8516:
>  		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
>  		break;
>  	case PWRAP_MT7622:
> @@ -1765,6 +1856,18 @@ static const struct pmic_wrapper_type pwrap_mt8183 = {
>  	.init_soc_specific = pwrap_mt8183_init_soc_specific,
>  };
>  
> +static struct pmic_wrapper_type pwrap_mt8516 = {
> +	.regs = mt8516_regs,
> +	.type = PWRAP_MT8516,
> +	.arb_en_all = 0xff,
> +	.int_en_all = ~(u32)(BIT(31) | BIT(2)),
> +	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
> +	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
> +	.caps = PWRAP_CAP_DCM,
> +	.init_reg_clock = pwrap_mt2701_init_reg_clock,
> +	.init_soc_specific = NULL,
> +};
> +
>  static const struct of_device_id of_pwrap_match_tbl[] = {
>  	{
>  		.compatible = "mediatek,mt2701-pwrap",
> @@ -1787,6 +1890,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
>  	}, {
>  		.compatible = "mediatek,mt8183-pwrap",
>  		.data = &pwrap_mt8183,
> +	}, {
> +		.compatible = "mediatek,mt8516-pwrap",
> +		.data = &pwrap_mt8516,
>  	}, {
>  		/* sentinel */
>  	}
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516
  2019-03-23 21:16 ` [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516 Fabien Parent
  2019-03-28 19:12   ` Rob Herring
@ 2019-04-16  7:54   ` Matthias Brugger
  2019-04-16  8:09     ` Daniel Lezcano
  1 sibling, 1 reply; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  7:54 UTC (permalink / raw)
  To: Fabien Parent, robh+dt, mark.rutland, Daniel Lezcano
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of mtk-timer for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
>  1 file changed, 1 insertion(+)

applied to v5.1-next/dts64

Daniel let me know if you want to take it through your tree and I drop the patch.

> 
> diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> index ff7c567a7972..74c3eadad844 100644
> --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
> @@ -17,6 +17,7 @@ Required properties:
>  	* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
>  	* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
>  	* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
> +	* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
>  	* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
>  
>  	For those SoCs that use SYST
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-03-23 21:16 ` [PATCH 19/24] dt-bindings: spi: spi-mt65xx: " Fabien Parent
  2019-03-28 19:12   ` Rob Herring
@ 2019-04-16  7:55   ` Matthias Brugger
  2019-04-16  8:25     ` lei liu
  2019-04-16 14:28     ` Mark Brown
  1 sibling, 2 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  7:55 UTC (permalink / raw)
  To: Fabien Parent, robh+dt, mark.rutland, Mark Brown
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of spi-mt65xx for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
>  1 file changed, 1 insertion(+)
> 


applied to v5.1-next/dts64

Mark let me know if you want to take it through your tree and I drop the patch.

> diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> index 69c356767cf8..69ac5976b952 100644
> --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> @@ -10,6 +10,7 @@ Required properties:
>      - mediatek,mt8135-spi: for mt8135 platforms
>      - mediatek,mt8173-spi: for mt8173 platforms
>      - mediatek,mt8183-spi: for mt8183 platforms
> +    - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
>  
>  - #address-cells: should be 1.
>  
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 20/24] dt-bindings: serial: mtk-uart: add support for MT8516
  2019-03-23 21:16 ` [PATCH 20/24] dt-bindings: serial: mtk-uart: " Fabien Parent
  2019-03-28 19:12   ` Rob Herring
@ 2019-04-16  7:56   ` Matthias Brugger
  1 sibling, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  7:56 UTC (permalink / raw)
  To: Fabien Parent, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of mtk-uart for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
>  1 file changed, 1 insertion(+)
> 


applied to v5.1-next/dts64

Thanks.

> diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> index 742cb470595b..1af981f7a33b 100644
> --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
> +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
> @@ -16,6 +16,7 @@ Required properties:
>    * "mediatek,mt8127-uart" for MT8127 compatible UARTS
>    * "mediatek,mt8135-uart" for MT8135 compatible UARTS
>    * "mediatek,mt8173-uart" for MT8173 compatible UARTS
> +  * "mediatek,mt8516-uart" for MT8516 compatible UARTS
>    * "mediatek,mt6577-uart" for MT6577 and all of the above
>  
>  - reg: The base address of the UART register bank.
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 21/24] dt-bindings: irq: mtk,sysirq: add support for MT8516
  2019-03-23 21:16 ` [PATCH 21/24] dt-bindings: irq: mtk,sysirq: " Fabien Parent
  2019-03-28 19:13   ` Rob Herring
@ 2019-04-16  7:57   ` Matthias Brugger
  1 sibling, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  7:57 UTC (permalink / raw)
  To: Fabien Parent, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of mediatek,sysirq for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  .../bindings/interrupt-controller/mediatek,sysirq.txt          | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

applied to v5.1-next/dts64

Thanks
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> index c5d589108a94..deaaba70d548 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
> @@ -1,10 +1,11 @@
> -+Mediatek MT65xx/MT67xx/MT81xx sysirq
> ++Mediatek MT65xx/MT67xx/MT81xx/MT85xx sysirq
>  
>  Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
>  interrupt.
>  
>  Required properties:
>  - compatible: should be
> +	"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
>  	"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
>  	"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
>  	"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
  2019-03-23 21:16 ` [PATCH 22/24] dt-bindings: i2c: i2c-mtk: " Fabien Parent
  2019-03-28 19:13   ` Rob Herring
@ 2019-04-16  7:58   ` Matthias Brugger
  2019-04-16  8:14     ` Wolfram Sang
  2019-04-16 11:05   ` Wolfram Sang
  2 siblings, 1 reply; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  7:58 UTC (permalink / raw)
  To: Fabien Parent, robh+dt, mark.rutland, Wolfram Sang
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 23/03/2019 22:16, Fabien Parent wrote:
> Add binding documentation of i2c-mtk for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
>  1 file changed, 1 insertion(+)
> 


applied to v5.1-next/dts64

Wolfram let me know if you want to take it through your tree and I drop the patch.

> diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> index ee4c32454198..aac7b56f251f 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> @@ -12,6 +12,7 @@ Required properties:
>        "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
>        "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
>        "mediatek,mt8173-i2c": for MediaTek MT8173
> +      "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
>    - reg: physical base address of the controller and dma base, length of memory
>      mapped region.
>    - interrupts: interrupt number to the cpu.
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 23/24] arm64: dts: mediatek: add dtsi for MT8516
  2019-03-28 19:22   ` Rob Herring
@ 2019-04-16  8:04     ` Matthias Brugger
  0 siblings, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  8:04 UTC (permalink / raw)
  To: Rob Herring, Fabien Parent
  Cc: Mark Rutland, Sean Wang, Ryder Lee, Hsin-Hsiung Wang, Wenzhen Yu,
	Chaotian Jing, Yong Mao, jjian.zhou, devicetree, linux-kernel,
	Linux I2C,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, open list:SERIAL DRIVERS, linux-spi,
	LINUX-WATCHDOG, linux-clk, stephane.leprovost



On 28/03/2019 20:22, Rob Herring wrote:
> On Sat, Mar 23, 2019 at 4:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>>
>> The MT8516 SoC provides the following peripherals: GPIO, UART, USB2,
>> SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, Timers, IR, Ethernet, and
>> Audio (I2S, SPDIF, TDM).
>>
>> This commit is adding the basic dtsi file with the support of the
>> following IOs: GPIO, UART, SPI, eMMC, I2C, Timers.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> ---
>>  arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h | 663 ++++++++++++++++++
>>  arch/arm64/boot/dts/mediatek/mt8516.dtsi      | 409 +++++++++++
>>  2 files changed, 1072 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8516-pinfunc.h
>>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8516.dtsi
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> 

Fabien, before taking this through my tree, I'd like to see the drivers merged.
Can you please resubmit taking into account the outcome of get_maintainers.pl
script. From my experience it is easier to send one series per driver, as it
makes the amount of emails every maintainer gets more manageable.

Regards,
Matthias

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516
  2019-04-16  7:54   ` Matthias Brugger
@ 2019-04-16  8:09     ` Daniel Lezcano
  0 siblings, 0 replies; 70+ messages in thread
From: Daniel Lezcano @ 2019-04-16  8:09 UTC (permalink / raw)
  To: Matthias Brugger, Fabien Parent, robh+dt, mark.rutland
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost

On 16/04/2019 09:54, Matthias Brugger wrote:
> 
> 
> On 23/03/2019 22:16, Fabien Parent wrote:
>> Add binding documentation of mtk-timer for MT8516 SoC.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> ---
>>  Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
>>  1 file changed, 1 insertion(+)
> 
> applied to v5.1-next/dts64
> 
> Daniel let me know if you want to take it through your tree and I drop the patch.

It is ok.

Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>

>> diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
>> index ff7c567a7972..74c3eadad844 100644
>> --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
>> +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
>> @@ -17,6 +17,7 @@ Required properties:
>>  	* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
>>  	* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
>>  	* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
>> +	* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
>>  	* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
>>  
>>  	For those SoCs that use SYST
>>


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
  2019-04-16  7:58   ` Matthias Brugger
@ 2019-04-16  8:14     ` Wolfram Sang
  2019-04-16  8:53       ` Matthias Brugger
  0 siblings, 1 reply; 70+ messages in thread
From: Wolfram Sang @ 2019-04-16  8:14 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Fabien Parent, robh+dt, mark.rutland, sean.wang, ryder.lee,
	hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao,
	jjian.zhou, devicetree, linux-kernel, linux-i2c,
	linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
	linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost

[-- Attachment #1: Type: text/plain, Size: 624 bytes --]

On Tue, Apr 16, 2019 at 09:58:09AM +0200, Matthias Brugger wrote:
> 
> 
> On 23/03/2019 22:16, Fabien Parent wrote:
> > Add binding documentation of i2c-mtk for MT8516 SoC.
> > 
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> >  Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> 
> 
> applied to v5.1-next/dts64
> 
> Wolfram let me know if you want to take it through your tree and I drop the patch.

I'd like to take it via my tree to reduce conflicts. It already needs
rebasing on top of i2c/for-next because of Qii's MT8183 patches.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-04-16  7:55   ` Matthias Brugger
@ 2019-04-16  8:25     ` lei liu
  2019-04-16  8:52       ` Matthias Brugger
  2019-04-18  8:05       ` Fabien Parent
  2019-04-16 14:28     ` Mark Brown
  1 sibling, 2 replies; 70+ messages in thread
From: lei liu @ 2019-04-16  8:25 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Fabien Parent, robh+dt, mark.rutland, Mark Brown,
	linux-arm-kernel, devicetree, ryder.lee, linux-watchdog,
	jjian.zhou, wenzhen.yu, stephane.leprovost, sean.wang, linux-mmc,
	linux-kernel, yong.mao, linux-spi, linux-gpio, linux-mediatek,
	hsin-hsiung.wang, linux-serial, linux-clk, chaotian.jing,
	linux-i2c

On Tue, 2019-04-16 at 09:55 +0200, Matthias Brugger wrote:
> 
> On 23/03/2019 22:16, Fabien Parent wrote:
> > Add binding documentation of spi-mt65xx for MT8516 SoC.
> > 
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> >  Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> 
> 
> applied to v5.1-next/dts64
> 
> Mark let me know if you want to take it through your tree and I drop the patch.
> 
> > diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > index 69c356767cf8..69ac5976b952 100644
> > --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > @@ -10,6 +10,7 @@ Required properties:
> >      - mediatek,mt8135-spi: for mt8135 platforms
> >      - mediatek,mt8173-spi: for mt8173 platforms
> >      - mediatek,mt8183-spi: for mt8183 platforms
> > +    - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
Hi Fabien,
mt8516 SPI design comes from mt2712 and it's different from mt2701. Here
it should compatible with mt2712.

> >  
> >  - #address-cells: should be 1.
> >  
> > 
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek



^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-04-16  8:25     ` lei liu
@ 2019-04-16  8:52       ` Matthias Brugger
  2019-04-18  8:05       ` Fabien Parent
  1 sibling, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  8:52 UTC (permalink / raw)
  To: lei liu
  Cc: Fabien Parent, robh+dt, mark.rutland, Mark Brown,
	linux-arm-kernel, devicetree, ryder.lee, linux-watchdog,
	jjian.zhou, wenzhen.yu, stephane.leprovost, sean.wang, linux-mmc,
	linux-kernel, yong.mao, linux-spi, linux-gpio, linux-mediatek,
	hsin-hsiung.wang, linux-serial, linux-clk, chaotian.jing,
	linux-i2c



On 16/04/2019 10:25, lei liu wrote:
> On Tue, 2019-04-16 at 09:55 +0200, Matthias Brugger wrote:
>>
>> On 23/03/2019 22:16, Fabien Parent wrote:
>>> Add binding documentation of spi-mt65xx for MT8516 SoC.
>>>
>>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>>> ---
>>>  Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>
>>
>> applied to v5.1-next/dts64
>>
>> Mark let me know if you want to take it through your tree and I drop the patch.
>>
>>> diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
>>> index 69c356767cf8..69ac5976b952 100644
>>> --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
>>> +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
>>> @@ -10,6 +10,7 @@ Required properties:
>>>      - mediatek,mt8135-spi: for mt8135 platforms
>>>      - mediatek,mt8173-spi: for mt8173 platforms
>>>      - mediatek,mt8183-spi: for mt8183 platforms
>>> +    - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
> Hi Fabien,
> mt8516 SPI design comes from mt2712 and it's different from mt2701. Here
> it should compatible with mt2712.
> 

Ok, please resend. I dropped the patch for now.

>>>  
>>>  - #address-cells: should be 1.
>>>  
>>>
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> 
> 

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
  2019-04-16  8:14     ` Wolfram Sang
@ 2019-04-16  8:53       ` Matthias Brugger
  0 siblings, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  8:53 UTC (permalink / raw)
  To: Wolfram Sang
  Cc: Fabien Parent, robh+dt, mark.rutland, sean.wang, ryder.lee,
	hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao,
	jjian.zhou, devicetree, linux-kernel, linux-i2c,
	linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
	linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 16/04/2019 10:14, Wolfram Sang wrote:
> On Tue, Apr 16, 2019 at 09:58:09AM +0200, Matthias Brugger wrote:
>> 
>> 
>> On 23/03/2019 22:16, Fabien Parent wrote:
>>> Add binding documentation of i2c-mtk for MT8516 SoC.
>>> 
>>> Signed-off-by: Fabien Parent <fparent@baylibre.com> --- 
>>> Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 + 1 file changed,
>>> 1 insertion(+)
>>> 
>> 
>> 
>> applied to v5.1-next/dts64
>> 
>> Wolfram let me know if you want to take it through your tree and I drop
>> the patch.
> 
> I'd like to take it via my tree to reduce conflicts. It already needs 
> rebasing on top of i2c/for-next because of Qii's MT8183 patches.
> 

Ok, dropped, the patch is all yours :)

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support for MT8516
  2019-04-08 20:44   ` Linus Walleij
@ 2019-04-16  9:12     ` Matthias Brugger
  2019-04-23 11:01       ` Linus Walleij
  0 siblings, 1 reply; 70+ messages in thread
From: Matthias Brugger @ 2019-04-16  9:12 UTC (permalink / raw)
  To: Linus Walleij, Fabien Parent
  Cc: Rob Herring, Mark Rutland, Sean Wang, Ryder Lee,
	hsin-hsiung.wang, wenzhen.yu, Chaotian Jing, Yong Mao,
	jjian.zhou,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	linux-kernel, linux-i2c, Linux ARM,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, linux-serial, linux-spi, LINUXWATCHDOG,
	linux-clk, stephane.leprovost

Hi Linus,

On 08/04/2019 22:44, Linus Walleij wrote:
> On Sat, Mar 23, 2019 at 10:17 PM Fabien Parent <fparent@baylibre.com> wrote:
> 
>> Add binding documentation of pinctrl-mt65xx for MT8516 SoC.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> 
> Patch applied with Rob's ACK.
> 

I don't see this in your for-next branch. Did the patch got lost?

Regards,
Matthias

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 22/24] dt-bindings: i2c: i2c-mtk: add support for MT8516
  2019-03-23 21:16 ` [PATCH 22/24] dt-bindings: i2c: i2c-mtk: " Fabien Parent
  2019-03-28 19:13   ` Rob Herring
  2019-04-16  7:58   ` Matthias Brugger
@ 2019-04-16 11:05   ` Wolfram Sang
  2 siblings, 0 replies; 70+ messages in thread
From: Wolfram Sang @ 2019-04-16 11:05 UTC (permalink / raw)
  To: Fabien Parent
  Cc: matthias.bgg, robh+dt, mark.rutland, sean.wang, ryder.lee,
	hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao,
	jjian.zhou, devicetree, linux-kernel, linux-i2c,
	linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
	linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost

[-- Attachment #1: Type: text/plain, Size: 213 bytes --]

On Sat, Mar 23, 2019 at 10:16:10PM +0100, Fabien Parent wrote:
> Add binding documentation of i2c-mtk for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>

Applied to for-next, thanks!


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-04-16  7:55   ` Matthias Brugger
  2019-04-16  8:25     ` lei liu
@ 2019-04-16 14:28     ` Mark Brown
  2019-04-17  8:19       ` Matthias Brugger
  1 sibling, 1 reply; 70+ messages in thread
From: Mark Brown @ 2019-04-16 14:28 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Fabien Parent, robh+dt, mark.rutland, sean.wang, ryder.lee,
	hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao,
	jjian.zhou, devicetree, linux-kernel, linux-i2c,
	linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
	linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost

[-- Attachment #1: Type: text/plain, Size: 509 bytes --]

On Tue, Apr 16, 2019 at 09:55:41AM +0200, Matthias Brugger wrote:
> On 23/03/2019 22:16, Fabien Parent wrote:
> > Add binding documentation of spi-mt65xx for MT8516 SoC.

> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > ---
> >  Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
> >  1 file changed, 1 insertion(+)

> applied to v5.1-next/dts64

> Mark let me know if you want to take it through your tree and I drop the patch.

Yes, DT bindings generally get reviewed in the subsystem :(

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-04-16 14:28     ` Mark Brown
@ 2019-04-17  8:19       ` Matthias Brugger
  0 siblings, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-17  8:19 UTC (permalink / raw)
  To: Mark Brown
  Cc: Fabien Parent, robh+dt, mark.rutland, sean.wang, ryder.lee,
	hsin-hsiung.wang, wenzhen.yu, chaotian.jing, yong.mao,
	jjian.zhou, devicetree, linux-kernel, linux-i2c,
	linux-arm-kernel, linux-mediatek, linux-mmc, linux-gpio,
	linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost



On 16/04/2019 16:28, Mark Brown wrote:
> On Tue, Apr 16, 2019 at 09:55:41AM +0200, Matthias Brugger wrote:
>> On 23/03/2019 22:16, Fabien Parent wrote:
>>> Add binding documentation of spi-mt65xx for MT8516 SoC.
> 
>>> Signed-off-by: Fabien Parent <fparent@baylibre.com> --- 
>>> Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 + 1 file
>>> changed, 1 insertion(+)
> 
>> applied to v5.1-next/dts64
> 
>> Mark let me know if you want to take it through your tree and I drop the
>> patch.
> 
> Yes, DT bindings generally get reviewed in the subsystem :(
> 

I already dropped it due to some comments from Lei Liu:
https://patchwork.kernel.org/patch/10867251/

Regards,
Matthias

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-04-16  8:25     ` lei liu
  2019-04-16  8:52       ` Matthias Brugger
@ 2019-04-18  8:05       ` Fabien Parent
  2019-04-18  8:18         ` lei liu
  1 sibling, 1 reply; 70+ messages in thread
From: Fabien Parent @ 2019-04-18  8:05 UTC (permalink / raw)
  To: lei liu
  Cc: Matthias Brugger, Rob Herring, Mark Rutland, Mark Brown,
	linux-arm-kernel, devicetree, ryder.lee, linux-watchdog,
	jjian.zhou, wenzhen.yu, Stephane Le Provost, sean.wang,
	linux-mmc, linux-kernel, yong.mao, linux-spi, linux-gpio,
	linux-mediatek, hsin-hsiung.wang, linux-serial, linux-clk,
	Chaotian Jing, linux-i2c

On Tue, Apr 16, 2019 at 10:25 AM lei liu <leilk.liu@mediatek.com> wrote:
>
> On Tue, 2019-04-16 at 09:55 +0200, Matthias Brugger wrote:
> >
> > On 23/03/2019 22:16, Fabien Parent wrote:
> > > Add binding documentation of spi-mt65xx for MT8516 SoC.
> > >
> > > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > > ---
> > >  Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> >
> >
> > applied to v5.1-next/dts64
> >
> > Mark let me know if you want to take it through your tree and I drop the patch.
> >
> > > diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > > index 69c356767cf8..69ac5976b952 100644
> > > --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > > +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > > @@ -10,6 +10,7 @@ Required properties:
> > >      - mediatek,mt8135-spi: for mt8135 platforms
> > >      - mediatek,mt8173-spi: for mt8173 platforms
> > >      - mediatek,mt8183-spi: for mt8183 platforms
> > > +    - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
> Hi Fabien,
> mt8516 SPI design comes from mt2712 and it's different from mt2701. Here
> it should compatible with mt2712.

Ok, thanks. I will retry with the mt2712 compatible.

> > >
> > >  - #address-cells: should be 1.
> > >
> > >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
>

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 19/24] dt-bindings: spi: spi-mt65xx: add support for MT8516
  2019-04-18  8:05       ` Fabien Parent
@ 2019-04-18  8:18         ` lei liu
  0 siblings, 0 replies; 70+ messages in thread
From: lei liu @ 2019-04-18  8:18 UTC (permalink / raw)
  To: Fabien Parent
  Cc: Matthias Brugger, Rob Herring, Mark Rutland, Mark Brown,
	linux-arm-kernel, devicetree, ryder.lee, linux-watchdog,
	jjian.zhou, wenzhen.yu, Stephane Le Provost, sean.wang,
	linux-mmc, linux-kernel, yong.mao, linux-spi, linux-gpio,
	linux-mediatek, hsin-hsiung.wang, linux-serial, linux-clk,
	Chaotian Jing, linux-i2c

On Thu, 2019-04-18 at 10:05 +0200, Fabien Parent wrote:
> On Tue, Apr 16, 2019 at 10:25 AM lei liu <leilk.liu@mediatek.com> wrote:
> >
> > On Tue, 2019-04-16 at 09:55 +0200, Matthias Brugger wrote:
> > >
> > > On 23/03/2019 22:16, Fabien Parent wrote:
> > > > Add binding documentation of spi-mt65xx for MT8516 SoC.
> > > >
> > > > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > > > ---
> > > >  Documentation/devicetree/bindings/spi/spi-mt65xx.txt | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > >
> > >
> > > applied to v5.1-next/dts64
> > >
> > > Mark let me know if you want to take it through your tree and I drop the patch.
> > >
> > > > diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > > > index 69c356767cf8..69ac5976b952 100644
> > > > --- a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > > > +++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt
> > > > @@ -10,6 +10,7 @@ Required properties:
> > > >      - mediatek,mt8135-spi: for mt8135 platforms
> > > >      - mediatek,mt8173-spi: for mt8173 platforms
> > > >      - mediatek,mt8183-spi: for mt8183 platforms
> > > > +    - "mediatek,mt8516-spi", "mediatek,mt2701-spi": for mt8516 platforms
> > Hi Fabien,
> > mt8516 SPI design comes from mt2712 and it's different from mt2701. Here
> > it should compatible with mt2712.
> 
> Ok, thanks. I will retry with the mt2712 compatible.
> 

Hi, I already send mt8516 spi patch and it's applied by Mark. Please
don't do it again. Thanks.

> > > >
> > > >  - #address-cells: should be 1.
> > > >
> > > >
> > >
> > > _______________________________________________
> > > Linux-mediatek mailing list
> > > Linux-mediatek@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-mediatek
> >
> >



^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support for MT8516
  2019-04-16  9:12     ` Matthias Brugger
@ 2019-04-23 11:01       ` Linus Walleij
  2019-04-23 14:24         ` Matthias Brugger
  0 siblings, 1 reply; 70+ messages in thread
From: Linus Walleij @ 2019-04-23 11:01 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: Fabien Parent, Rob Herring, Mark Rutland, Sean Wang, Ryder Lee,
	hsin-hsiung.wang, wenzhen.yu, Chaotian Jing, Yong Mao,
	jjian.zhou,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	linux-kernel, linux-i2c, Linux ARM,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, linux-serial, linux-spi, LINUXWATCHDOG,
	linux-clk, stephane.leprovost

On Tue, Apr 16, 2019 at 11:12 AM Matthias Brugger
<matthias.bgg@gmail.com> wrote:

> Hi Linus,
>
> On 08/04/2019 22:44, Linus Walleij wrote:
> > On Sat, Mar 23, 2019 at 10:17 PM Fabien Parent <fparent@baylibre.com> wrote:
> >
> >> Add binding documentation of pinctrl-mt65xx for MT8516 SoC.
> >>
> >> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> >
> > Patch applied with Rob's ACK.
> >
>
> I don't see this in your for-next branch. Did the patch got lost?

I usually push the devel branch to be tested by the build robots
and then mix down the for-next branch.

Recent week(s) the build robot was not responding so it got delayed.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support for MT8516
  2019-04-23 11:01       ` Linus Walleij
@ 2019-04-23 14:24         ` Matthias Brugger
  0 siblings, 0 replies; 70+ messages in thread
From: Matthias Brugger @ 2019-04-23 14:24 UTC (permalink / raw)
  To: Linus Walleij
  Cc: Fabien Parent, Rob Herring, Mark Rutland, Sean Wang, Ryder Lee,
	hsin-hsiung.wang, wenzhen.yu, Chaotian Jing, Yong Mao,
	jjian.zhou,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	linux-kernel, linux-i2c, Linux ARM,
	moderated list:ARM/Mediatek SoC support, linux-mmc,
	open list:GPIO SUBSYSTEM, linux-serial, linux-spi, LINUXWATCHDOG,
	linux-clk, stephane.leprovost



On 23/04/2019 13:01, Linus Walleij wrote:
> On Tue, Apr 16, 2019 at 11:12 AM Matthias Brugger
> <matthias.bgg@gmail.com> wrote:
> 
>> Hi Linus,
>>
>> On 08/04/2019 22:44, Linus Walleij wrote:
>>> On Sat, Mar 23, 2019 at 10:17 PM Fabien Parent <fparent@baylibre.com> wrote:
>>>
>>>> Add binding documentation of pinctrl-mt65xx for MT8516 SoC.
>>>>
>>>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>>>
>>> Patch applied with Rob's ACK.
>>>
>>
>> I don't see this in your for-next branch. Did the patch got lost?
> 
> I usually push the devel branch to be tested by the build robots
> and then mix down the for-next branch.
> 
> Recent week(s) the build robot was not responding so it got delayed.
> 

I don't see it in the devel branch [1]. Can you please double check?

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 11/24] dt-bindings: mediatek: topckgen: add support for MT8516
  2019-03-23 21:15 ` [PATCH 11/24] dt-bindings: mediatek: topckgen: " Fabien Parent
  2019-03-28 19:09   ` Rob Herring
@ 2019-04-25 21:34   ` Stephen Boyd
  1 sibling, 0 replies; 70+ messages in thread
From: Stephen Boyd @ 2019-04-25 21:34 UTC (permalink / raw)
  To: Fabien Parent, mark.rutland, matthias.bgg, robh+dt
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Quoting Fabien Parent (2019-03-23 14:15:59)
> Add binding documentation of topckgen for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---

Applied to clk-next


^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 12/24] dt-bindings: mediatek: infracfg: add support for MT8516
  2019-03-23 21:16 ` [PATCH 12/24] dt-bindings: mediatek: infracfg: " Fabien Parent
  2019-03-28 19:10   ` Rob Herring
@ 2019-04-25 21:34   ` Stephen Boyd
  1 sibling, 0 replies; 70+ messages in thread
From: Stephen Boyd @ 2019-04-25 21:34 UTC (permalink / raw)
  To: Fabien Parent, mark.rutland, matthias.bgg, robh+dt
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Quoting Fabien Parent (2019-03-23 14:16:00)
> Add binding documentation of infracfg for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---

Applied to clk-next


^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 13/24] dt-bindings: mediatek: apmixedsys: add support for MT8516
  2019-03-23 21:16 ` [PATCH 13/24] dt-bindings: mediatek: apmixedsys: " Fabien Parent
  2019-03-28 19:11   ` Rob Herring
@ 2019-04-25 21:35   ` Stephen Boyd
  1 sibling, 0 replies; 70+ messages in thread
From: Stephen Boyd @ 2019-04-25 21:35 UTC (permalink / raw)
  To: Fabien Parent, mark.rutland, matthias.bgg, robh+dt
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Quoting Fabien Parent (2019-03-23 14:16:01)
> Add binding documentation of apmixedsys for MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---

Applied to clk-next


^ permalink raw reply	[flat|nested] 70+ messages in thread

* Re: [PATCH 14/24] clk: mediatek: add clock driver for MT8516
  2019-03-23 21:16 ` [PATCH 14/24] clk: mediatek: add clock driver " Fabien Parent
@ 2019-04-25 21:39   ` Stephen Boyd
  0 siblings, 0 replies; 70+ messages in thread
From: Stephen Boyd @ 2019-04-25 21:39 UTC (permalink / raw)
  To: Fabien Parent, mark.rutland, matthias.bgg, robh+dt
  Cc: sean.wang, ryder.lee, hsin-hsiung.wang, wenzhen.yu,
	chaotian.jing, yong.mao, jjian.zhou, devicetree, linux-kernel,
	linux-i2c, linux-arm-kernel, linux-mediatek, linux-mmc,
	linux-gpio, linux-serial, linux-spi, linux-watchdog, linux-clk,
	stephane.leprovost, Fabien Parent

Quoting Fabien Parent (2019-03-23 14:16:02)
> Add the clock driver for the MT8516 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---

Applied to clk-next


^ permalink raw reply	[flat|nested] 70+ messages in thread

end of thread, back to index

Thread overview: 70+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-23 21:15 [PATCH 00/24] arm64: mediatek: add support for Pumpkin MT8516 board Fabien Parent
2019-03-23 21:15 ` [PATCH 01/24] dt-bindings: regulator: add support for MT6392 Fabien Parent
2019-03-28 19:17   ` Rob Herring
2019-03-23 21:15 ` [PATCH 02/24] regulator: mt6392: Add support for MT6392 regulator Fabien Parent
2019-03-23 21:15 ` [PATCH 03/24] dt-bindings: pwrap: mediatek: add pwrap support for MT8516 Fabien Parent
2019-03-28 19:09   ` Rob Herring
2019-04-12 17:44   ` Matthias Brugger
2019-03-23 21:15 ` [PATCH 04/24] soc: mediatek: pwrap: add missing check on rstc Fabien Parent
2019-04-12 17:44   ` Matthias Brugger
2019-03-23 21:15 ` [PATCH 05/24] soc: mediatek: pwrap: add support for MT8516 pwrap Fabien Parent
2019-04-12 17:44   ` Matthias Brugger
2019-03-23 21:15 ` [PATCH 06/24] mfd: mt6397: Add support for MT6397 pmic Fabien Parent
2019-03-23 21:15 ` [PATCH 07/24] arm64: dts: mt6392: Add PMIC mt6392 dtsi Fabien Parent
2019-03-28 19:18   ` Rob Herring
2019-03-23 21:15 ` [PATCH 08/24] dt-bindings: mmc: mtk-sd: add mtk-sd support for MT8516 Fabien Parent
2019-03-23 21:15 ` [PATCH 09/24] mmc: mtk-sd: check for valid optional memory resource Fabien Parent
2019-03-24  3:34   ` Yingjoe Chen
2019-03-24 15:18     ` Fabien Parent
2019-03-23 21:15 ` [PATCH 10/24] mmc: mtk-sd: add support for MT8516 Fabien Parent
2019-03-23 21:15 ` [PATCH 11/24] dt-bindings: mediatek: topckgen: " Fabien Parent
2019-03-28 19:09   ` Rob Herring
2019-04-25 21:34   ` Stephen Boyd
2019-03-23 21:16 ` [PATCH 12/24] dt-bindings: mediatek: infracfg: " Fabien Parent
2019-03-28 19:10   ` Rob Herring
2019-04-25 21:34   ` Stephen Boyd
2019-03-23 21:16 ` [PATCH 13/24] dt-bindings: mediatek: apmixedsys: " Fabien Parent
2019-03-28 19:11   ` Rob Herring
2019-04-25 21:35   ` Stephen Boyd
2019-03-23 21:16 ` [PATCH 14/24] clk: mediatek: add clock driver " Fabien Parent
2019-04-25 21:39   ` Stephen Boyd
2019-03-23 21:16 ` [PATCH 15/24] dt-bindings: pinctrl: pinctrl-mt65xx: add support " Fabien Parent
2019-03-28 19:11   ` Rob Herring
2019-04-08 20:44   ` Linus Walleij
2019-04-16  9:12     ` Matthias Brugger
2019-04-23 11:01       ` Linus Walleij
2019-04-23 14:24         ` Matthias Brugger
2019-03-23 21:16 ` [PATCH 16/24] pinctrl: mediatek: Add MT8516 Pinctrl driver Fabien Parent
2019-04-01 21:02   ` Sean Wang
2019-03-23 21:16 ` [PATCH 17/24] dt-bindings: wdog: mtk-wdt: add support for MT851 Fabien Parent
2019-03-24 15:13   ` Guenter Roeck
2019-03-28 19:13   ` Rob Herring
2019-03-23 21:16 ` [PATCH 18/24] dt-bindings: timer: mtk-timer: add support for MT8516 Fabien Parent
2019-03-28 19:12   ` Rob Herring
2019-04-16  7:54   ` Matthias Brugger
2019-04-16  8:09     ` Daniel Lezcano
2019-03-23 21:16 ` [PATCH 19/24] dt-bindings: spi: spi-mt65xx: " Fabien Parent
2019-03-28 19:12   ` Rob Herring
2019-04-16  7:55   ` Matthias Brugger
2019-04-16  8:25     ` lei liu
2019-04-16  8:52       ` Matthias Brugger
2019-04-18  8:05       ` Fabien Parent
2019-04-18  8:18         ` lei liu
2019-04-16 14:28     ` Mark Brown
2019-04-17  8:19       ` Matthias Brugger
2019-03-23 21:16 ` [PATCH 20/24] dt-bindings: serial: mtk-uart: " Fabien Parent
2019-03-28 19:12   ` Rob Herring
2019-04-16  7:56   ` Matthias Brugger
2019-03-23 21:16 ` [PATCH 21/24] dt-bindings: irq: mtk,sysirq: " Fabien Parent
2019-03-28 19:13   ` Rob Herring
2019-04-16  7:57   ` Matthias Brugger
2019-03-23 21:16 ` [PATCH 22/24] dt-bindings: i2c: i2c-mtk: " Fabien Parent
2019-03-28 19:13   ` Rob Herring
2019-04-16  7:58   ` Matthias Brugger
2019-04-16  8:14     ` Wolfram Sang
2019-04-16  8:53       ` Matthias Brugger
2019-04-16 11:05   ` Wolfram Sang
2019-03-23 21:16 ` [PATCH 23/24] arm64: dts: mediatek: add dtsi " Fabien Parent
2019-03-28 19:22   ` Rob Herring
2019-04-16  8:04     ` Matthias Brugger
2019-03-23 21:16 ` [PATCH 24/24] arm64: dts: mediatek: add pumpkin board dts Fabien Parent

Linux-Watchdog Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-watchdog/0 linux-watchdog/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-watchdog linux-watchdog/ https://lore.kernel.org/linux-watchdog \
		linux-watchdog@vger.kernel.org linux-watchdog@archiver.kernel.org
	public-inbox-index linux-watchdog

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-watchdog


AGPL code for this site: git clone https://public-inbox.org/ public-inbox