[PATCH V6 0/7] dt-bindinds/dts: support i.MX8ULP

[PATCH V6 0/7] dt-bindinds/dts: support i.MX8ULP

[Peng Fan (OSS)]

From: Peng Fan <peng.fan@nxp.com>

V6:
 Rebase to avoid conflict.

V5:
 only fix patch 8/8 'arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board'
  - Correct bus-width to 8 for eMMC
  - Drop pinctrl enet which no user
 Drop patch 1/9 in V4, since in merged in linux-next
 Add A-b/R-b tag

V4:
 https://lists.infradead.org/pipermail/linux-arm-kernel/2021-November/696020.html

I just pick-up Jacky's work, rebase and send out V4 based on
Jacky's V3 patchset.

If you prefer to split the patchset and send single patches, I could
resend one by one.

Note: the V3 has a gpio bindings patch, it has been separated and
sent to gpio list in a single one per Linus requested.

This patchset is to add i.MX8ULP in dt-bindings, introduce
basic i.MX8ULP dtsi and basic evk board support.

The detailed version changes are in each patch.

There is checkpatch error in patch 8, but that is for device tree macro
and we could use use "(xx)".

In V4, the changes are in patch 8, 9 when rebasing to linux-next/master
,fix build errors after the clk driver in tree and drop a few nodes
that not have bindings.

Tested with CONFIG_CLK_IMX8ULP and CONFIG_PINCTRL_IMX8ULP enabled.

V3:
 https://lore.kernel.org/linux-arm-kernel/20210625011355.3468586-6-ping.bai@nxp.com/T/
Jacky Bai (7):
  dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string
  dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string
  dt-bindings: timer: tpm-timer: Add imx8ulp compatible string
  dt-bindings: watchdog: imx7ulp-wdt: Add imx8ulp compatible string
  dt-bindings: arm: fsl: Add binding for imx8ulp evk
  arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp
  arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board

 .../devicetree/bindings/arm/fsl.yaml          |   6 +
 .../bindings/i2c/i2c-imx-lpi2c.yaml           |   1 +
 .../bindings/serial/fsl-lpuart.yaml           |   4 +-
 .../bindings/timer/nxp,tpm-timer.yaml         |   6 +-
 .../bindings/watchdog/fsl-imx7ulp-wdt.yaml    |   7 +-
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts |  64 ++
 .../boot/dts/freescale/imx8ulp-pinfunc.h      | 978 ++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 396 +++++++
 9 files changed, 1459 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
 create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
 create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi

-- 
2.25.1

[PATCH V6 1/7] dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string

[Peng Fan (OSS)]

From: Jacky Bai <ping.bai@nxp.com>

Add the compatible for i.MX8ULP.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

 - v6 changes:
   rebase

 - v5 changes:
   no

 - v4 changes:
   no

 - v3 changes:
   no

 - v2 changes:
   no

 Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
index fe0c89edf7c1..a4bc57d044a0 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
@@ -21,6 +21,7 @@ properties:
           - enum:
               - fsl,imx8qxp-lpi2c
               - fsl,imx8qm-lpi2c
+              - fsl,imx8ulp-lpi2c
           - const: fsl,imx7ulp-lpi2c
 
   reg:
-- 
2.25.1

[PATCH V6 2/7] dt-bindings: serial: fsl-lpuart: Add imx8ulp compatible string

[Peng Fan (OSS)]

From: Jacky Bai <ping.bai@nxp.com>

The lpuart on i.MX8ULP is derived from i.MX7ULP, it uses two compatible
strings, so update the compatible string for i.MX8ULP.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

 - v6 changes:
   rebase

 - v5 changes:
   no

 - v4 changes:
   no

 - v3 changes:
   no

 - v2 changes:
   refine the commit messages

 Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
index a90c971b4f1f..e7ac63dd1469 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
@@ -22,7 +22,9 @@ properties:
           - fsl,imx7ulp-lpuart
           - fsl,imx8qm-lpuart
       - items:
-          - const: fsl,imx8qxp-lpuart
+          - enum:
+              - fsl,imx8qxp-lpuart
+              - fsl,imx8ulp-lpuart
           - const: fsl,imx7ulp-lpuart
 
   reg:
-- 
2.25.1

[PATCH V6 3/7] dt-bindings: timer: tpm-timer: Add imx8ulp compatible string

[Peng Fan (OSS)]

From: Jacky Bai <ping.bai@nxp.com>

The tpm timer on i.MX8ULP is derived from i.MX7ULP, it use two
compatible strings, so update the compatible string for it.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

 - v6 changes:
   rebase

 - v5 changes:
   no

 - v4 changes:
   no

 - v3 changes:
   no

 - v2 changes:
   refine the commit messages


 Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
index edd9585f6726..f69773a8e4b9 100644
--- a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml
@@ -19,7 +19,11 @@ description: |
 
 properties:
   compatible:
-    const: fsl,imx7ulp-tpm
+    oneOf:
+      - const: fsl,imx7ulp-tpm
+      - items:
+          - const: fsl,imx8ulp-tpm
+          - const: fsl,imx7ulp-tpm
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH V6 4/7] dt-bindings: watchdog: imx7ulp-wdt: Add imx8ulp compatible string

[Peng Fan (OSS)]

From: Jacky Bai <ping.bai@nxp.com>

The wdog on i.MX8ULP is derived from i.MX7ULP, it uses two compatible
strings, so update the compatible string for i.MX8ULP.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
 - v6 changes:
   rebase

 - v5 changes:
   no

 - v4 changes:
   no

 - v3 changes:
   no

 - v2 changes:
   refine the commit message

 .../devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml      | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
index 51d6d482bbc2..fb603a20e396 100644
--- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
@@ -14,8 +14,11 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - fsl,imx7ulp-wdt
+    oneOf:
+      - const: fsl,imx7ulp-wdt
+      - items:
+          - const: fsl,imx8ulp-wdt
+          - const: fsl,imx7ulp-wdt
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH V6 5/7] dt-bindings: arm: fsl: Add binding for imx8ulp evk

[Peng Fan (OSS)]

From: Jacky Bai <ping.bai@nxp.com>

Add the dt binding for i.MX8ULP EVK board.

i.MX 8ULP is part of the ULP family with emphasis on extreme
low-power techniques using the 28 nm fully depleted silicon on
insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
based on asymmetric architecture, however will add a third DSP
domain for advanced voice/audio capability and a Graphics domain
where it is possible to access graphics resources from the
application side or the realtime side.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

 - v6 changes:
   rebase

 - v5 changes:
   no

 - v4 changes:
   no

 - v3 changes:
   no

 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0b595b26061f..42b5dd546aee 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -834,6 +834,12 @@ properties:
           - const: toradex,colibri-imx8x
           - const: fsl,imx8qxp
 
+      - description: i.MX8ULP based Boards
+        items:
+          - enum:
+              - fsl,imx8ulp-evk           # i.MX8ULP EVK Board
+          - const: fsl,imx8ulp
+
       - description:
           Freescale Vybrid Platform Device Tree Bindings
 
-- 
2.25.1

[PATCH V6 7/7] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board

[Peng Fan (OSS)]

From: Jacky Bai <ping.bai@nxp.com>

Add the basic dts file for i.MX8ULP EVK board.
Only the necessary devices for minimal system boot up are enabled:
enet, emmc, usb, console uart.

some of the devices' pin status may lost during low power mode,
so additional sleep pinctrl properties are included by default.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 - v6
  Rebase

 - v5
  Fix eMMC bus width
  Drop pinctrl enet

 - v4
  Fix memory node
  Drop usb and fec nodes

 - v3 changes:
   no

 - v2 changes:
   add the memory node place holder
   update the license

 arch/arm64/boot/dts/freescale/Makefile        |  1 +
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 64 +++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a14a6173b765..c64616192794 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
 
 dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
 dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
new file mode 100644
index 000000000000..33e84c4e9ed8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp.dtsi"
+
+/ {
+	model = "NXP i.MX8ULP EVK";
+	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
+
+	chosen {
+		stdout-path = &lpuart5;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0 0x80000000>;
+	};
+};
+
+&lpuart5 {
+	/* console */
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_lpuart5>;
+	pinctrl-1 = <&pinctrl_lpuart5>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc0>;
+	pinctrl-1 = <&pinctrl_usdhc0>;
+	non-removable;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart5: lpuart5grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
+			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
+		>;
+	};
+
+	pinctrl_usdhc0: usdhc0grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
+			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
+			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
+			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
+			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
+			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
+			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
+			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
+			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
+			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
+			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
+		>;
+	};
+};
-- 
2.25.1

Re: [PATCH V6 1/7] dt-bindings: i2c: imx-lpi2c: Add imx8ulp compatible string

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 369 bytes --]

On Fri, Nov 26, 2021 at 03:39:56PM +0800, Peng Fan (OSS) wrote:
> From: Jacky Bai <ping.bai@nxp.com>
> 
> Add the compatible for i.MX8ULP.
> 
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied to for-next, thanks!


[-- Attachment #2: signature.asc --]
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Re: [PATCH V6 3/7] dt-bindings: timer: tpm-timer: Add imx8ulp compatible string

[Daniel Lezcano]

On 26/11/2021 08:39, Peng Fan (OSS) wrote:
> From: Jacky Bai <ping.bai@nxp.com>
> 
> The tpm timer on i.MX8ULP is derived from i.MX7ULP, it use two
> compatible strings, so update the compatible string for it.
> 
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied, thanks


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Re: [PATCH V6 6/7] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp

[Shawn Guo]

On Fri, Nov 26, 2021 at 03:40:01PM +0800, Peng Fan (OSS) wrote:
> From: Jacky Bai <ping.bai@nxp.com>
> 
> Add the basic dtsi support for i.MX8ULP.
> 
> i.MX 8ULP is part of the ULP family with emphasis on extreme
> low-power techniques using the 28 nm fully depleted silicon on
> insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
> based on asymmetric architecture, however will add a third DSP
> domain for advanced voice/audio capability and a Graphics domain
> where it is possible to access graphics resources from the
> application side or the realtime side.
> 
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> 
>   - v6
>    rebase
> 
>   - v5
>    Add R-b tag
>    
>   - v4
>    Fix build error after rebase
>    Drop usb nodes and alias, drop fec node
> 
>   - v3 changes:
>     no
>  
>   - v2 changes:
>     update the license
>     update the compatible property for usb related node
> 
> 
>  .../boot/dts/freescale/imx8ulp-pinfunc.h      | 978 ++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 396 +++++++
>  2 files changed, 1374 insertions(+)
>  create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi

<snip>

> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> new file mode 100644
> index 000000000000..fb8714379026
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -0,0 +1,396 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +#include <dt-bindings/clock/imx8ulp-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx8ulp-pinfunc.h"
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		gpio0 = &gpiod;
> +		gpio1 = &gpioe;
> +		gpio2 = &gpiof;
> +		mmc0 = &usdhc0;
> +		mmc1 = &usdhc1;
> +		mmc2 = &usdhc2;
> +		serial0 = &lpuart4;
> +		serial1 = &lpuart5;
> +		serial2 = &lpuart6;
> +		serial3 = &lpuart7;
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		A35_0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&A35_L2>;
> +		};
> +
> +		A35_1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a35";
> +			reg = <0x0 0x1>;
> +			enable-method = "psci";
> +			next-level-cache = <&A35_L2>;
> +		};
> +
> +		A35_L2: l2-cache0 {
> +			compatible = "cache";
> +		};
> +	};
> +
> +	gic: interrupt-controller@2d400000 {
> +		compatible = "arm,gic-v3";
> +		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
> +		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> +	};
> +
> +	frosc: clock-frosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <192000000>;
> +		clock-output-names = "frosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	lposc: clock-lposc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <1000000>;
> +		clock-output-names = "lposc";
> +		#clock-cells = <0>;
> +	};
> +
> +	rosc: clock-rosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32768>;
> +		clock-output-names = "rosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	sosc: clock-sosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <24000000>;
> +		clock-output-names = "sosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	soc@0 {

Why do we need unit-address @0 here?

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x0 0x0 0x40000000>;
> +
> +		per_bridge3: bus@29000000 {
> +			compatible = "simple-bus";
> +			reg = <0x29000000 0x800000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			wdog3: watchdog@292a0000 {
> +				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
> +				reg = <0x292a0000 0x10000>;
> +				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
> +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
> +				timeout-sec = <40>;
> +			};
> +
> +			cgc1: clock-controller@292c0000 {
> +				compatible = "fsl,imx8ulp-cgc1";
> +				reg = <0x292c0000 0x10000>;
> +				clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> +				clock-names = "rosc", "sosc", "frosc", "lposc";
> +				#clock-cells = <1>;
> +			};
> +
> +			pcc3: clock-controller@292d0000 {
> +				compatible = "fsl,imx8ulp-pcc3";
> +				reg = <0x292d0000 0x10000>;
> +				#clock-cells = <1>;
> +			};
> +
> +			tpm5: tpm@29340000 {
> +				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
> +				reg = <0x29340000 0x1000>;
> +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
> +					 <&pcc3 IMX8ULP_CLK_TPM5>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
> +			lpi2c4: i2c@29370000 {
> +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> +				reg = <0x29370000 0x10000>;
> +				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
> +					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
> +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <48000000>;
> +				status = "disabled";
> +			};
> +
> +			lpi2c5: i2c@29380000 {
> +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> +				reg = <0x29380000 0x10000>;
> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
> +					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
> +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <48000000>;
> +				status = "disabled";
> +			};
> +
> +			lpuart4: serial@29390000 {
> +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> +				reg = <0x29390000 0x1000>;
> +				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			lpuart5: serial@293a0000 {
> +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> +				reg = <0x293a0000 0x1000>;
> +				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			lpspi4: spi@293b0000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
> +				reg = <0x293b0000 0x10000>;
> +				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
> +					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
> +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <16000000>;
> +				status = "disabled";
> +			};
> +
> +			lpspi5: spi@293c0000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
> +				reg = <0x293c0000 0x10000>;
> +				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
> +					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
> +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <16000000>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		per_bridge4: bus@29800000 {
> +			compatible = "simple-bus";
> +			reg = <0x29800000 0x800000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			pcc4: clock-controller@29800000 {
> +				compatible = "fsl,imx8ulp-pcc4";
> +				reg = <0x29800000 0x10000>;
> +				#clock-cells = <1>;
> +			};
> +
> +			lpi2c6: i2c@29840000 {
> +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> +				reg = <0x29840000 0x10000>;
> +				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
> +					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
> +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <48000000>;
> +				status = "disabled";
> +			};
> +
> +			lpi2c7: i2c@29850000 {
> +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> +				reg = <0x29850000 0x10000>;
> +				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
> +					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
> +				clock-names = "per", "ipg";
> +				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
> +				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
> +				assigned-clock-rates = <48000000>;
> +				status = "disabled";
> +			};
> +
> +			lpuart6: serial@29860000 {
> +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> +				reg = <0x29860000 0x1000>;
> +				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			lpuart7: serial@29870000 {
> +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> +				reg = <0x29870000 0x1000>;
> +				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
> +				clock-names = "ipg";
> +				status = "disabled";
> +			};
> +
> +			iomuxc1: pinctrl@298c0000 {
> +				compatible = "fsl,imx8ulp-iomuxc1";

I know this binding is already landed.  Just curious why there is a
suffix number in the compatible.

Shawn

> +				reg = <0x298c0000 0x10000>;
> +			};
> +
> +			usdhc0: mmc@298d0000 {
> +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> +				reg = <0x298d0000 0x10000>;
> +				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> +					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
> +					 <&pcc4 IMX8ULP_CLK_USDHC0>;
> +				clock-names = "ipg", "ahb", "per";
> +				fsl,tuning-start-tap = <20>;
> +				fsl,tuning-step= <2>;
> +				bus-width = <4>;
> +				status = "disabled";
> +			};
> +
> +			usdhc1: mmc@298e0000 {
> +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> +				reg = <0x298e0000 0x10000>;
> +				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> +					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
> +					 <&pcc4 IMX8ULP_CLK_USDHC1>;
> +				clock-names = "ipg", "ahb", "per";
> +				fsl,tuning-start-tap = <20>;
> +				fsl,tuning-step= <2>;
> +				bus-width = <4>;
> +				status = "disabled";
> +			};
> +
> +			usdhc2: mmc@298f0000 {
> +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> +				reg = <0x298f0000 0x10000>;
> +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> +					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
> +					 <&pcc4 IMX8ULP_CLK_USDHC2>;
> +				clock-names = "ipg", "ahb", "per";
> +				fsl,tuning-start-tap = <20>;
> +				fsl,tuning-step= <2>;
> +				bus-width = <4>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		gpioe: gpio@2d000000 {
> +				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> +				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
> +					 <&pcc4 IMX8ULP_CLK_PCTLE>;
> +				clock-names = "gpio", "port";
> +				gpio-ranges = <&iomuxc1 0 32 24>;
> +		};
> +
> +		gpiof: gpio@2d010000 {
> +				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> +				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
> +					 <&pcc4 IMX8ULP_CLK_PCTLF>;
> +				clock-names = "gpio", "port";
> +				gpio-ranges = <&iomuxc1 0 64 32>;
> +		};
> +
> +		per_bridge5: bus@2d800000 {
> +			compatible = "simple-bus";
> +			reg = <0x2d800000 0x800000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			cgc2: clock-controller@2da60000 {
> +				compatible = "fsl,imx8ulp-cgc2";
> +				reg = <0x2da60000 0x10000>;
> +				clocks = <&sosc>, <&frosc>;
> +				clock-names = "sosc", "frosc";
> +				#clock-cells = <1>;
> +			};
> +
> +			pcc5: clock-controller@2da70000 {
> +				compatible = "fsl,imx8ulp-pcc5";
> +				reg = <0x2da70000 0x10000>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +
> +		gpiod: gpio@2e200000 {
> +			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> +			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
> +				 <&pcc5 IMX8ULP_CLK_RGPIOD>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 0 24>;
> +		};
> +	};
> +};
> -- 
> 2.25.1
> 

RE: [PATCH V6 6/7] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp

[Peng Fan]

Hi Shawn,

> Subject: Re: [PATCH V6 6/7] arm64: dts: imx8ulp: Add the basic dtsi file for
> imx8ulp
> 
> On Fri, Nov 26, 2021 at 03:40:01PM +0800, Peng Fan (OSS) wrote:
> > From: Jacky Bai <ping.bai@nxp.com>
> >
> > Add the basic dtsi support for i.MX8ULP.
> >
> > i.MX 8ULP is part of the ULP family with emphasis on extreme low-power
> > techniques using the 28 nm fully depleted silicon on insulator
> > process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric
> > architecture, however will add a third DSP domain for advanced
> > voice/audio capability and a Graphics domain where it is possible to
> > access graphics resources from the application side or the realtime
> > side.
> >
> > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> >
> >   - v6
> >    rebase
> >
> >   - v5
> >    Add R-b tag
> >
> >   - v4
> >    Fix build error after rebase
> >    Drop usb nodes and alias, drop fec node
> >
> >   - v3 changes:
> >     no
> >
> >   - v2 changes:
> >     update the license
> >     update the compatible property for usb related node
> >
> >
> >  .../boot/dts/freescale/imx8ulp-pinfunc.h      | 978
> ++++++++++++++++++
> >  arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 396 +++++++
> >  2 files changed, 1374 insertions(+)
> >  create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> 
> <snip>
> 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > new file mode 100644
> > index 000000000000..fb8714379026
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > @@ -0,0 +1,396 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2021 NXP
> > + */
> > +
> > +#include <dt-bindings/clock/imx8ulp-clock.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +#include "imx8ulp-pinfunc.h"
> > +
> > +/ {
> > +	interrupt-parent = <&gic>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	aliases {
> > +		gpio0 = &gpiod;
> > +		gpio1 = &gpioe;
> > +		gpio2 = &gpiof;
> > +		mmc0 = &usdhc0;
> > +		mmc1 = &usdhc1;
> > +		mmc2 = &usdhc2;
> > +		serial0 = &lpuart4;
> > +		serial1 = &lpuart5;
> > +		serial2 = &lpuart6;
> > +		serial3 = &lpuart7;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <2>;
> > +		#size-cells = <0>;
> > +
> > +		A35_0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x0 0x0>;
> > +			enable-method = "psci";
> > +			next-level-cache = <&A35_L2>;
> > +		};
> > +
> > +		A35_1: cpu@1 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a35";
> > +			reg = <0x0 0x1>;
> > +			enable-method = "psci";
> > +			next-level-cache = <&A35_L2>;
> > +		};
> > +
> > +		A35_L2: l2-cache0 {
> > +			compatible = "cache";
> > +		};
> > +	};
> > +
> > +	gic: interrupt-controller@2d400000 {
> > +		compatible = "arm,gic-v3";
> > +		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
> > +		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base)
> */
> > +		#interrupt-cells = <3>;
> > +		interrupt-controller;
> > +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +	};
> > +
> > +	psci {
> > +		compatible = "arm,psci-1.0";
> > +		method = "smc";
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical
> Secure */
> > +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical
> Non-Secure */
> > +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> > +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> > +	};
> > +
> > +	frosc: clock-frosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <192000000>;
> > +		clock-output-names = "frosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	lposc: clock-lposc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <1000000>;
> > +		clock-output-names = "lposc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	rosc: clock-rosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <32768>;
> > +		clock-output-names = "rosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	sosc: clock-sosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <24000000>;
> > +		clock-output-names = "sosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	soc@0 {
> 
> Why do we need unit-address @0 here?

I found there is patch which adds unit address, so I think we need @0 here.
commit 951c1d37f691027f149bbc58bbf0c207450a3654
Author: Fabio Estevam <festevam@gmail.com>
Date:   Tue May 28 16:00:21 2019 -0300

    arm64: dts: imx8mm: Pass a unit name for the 'soc' node

    The 'soc' name needs a unit name to match its 'ranges' property.

    Pass the unit name in order to fix the following dtc build warning
    with W=1:

    arch/arm64/boot/dts/freescale/imx8mm.dtsi:203.6-754.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name

    This also aligns with imx8mq.dtsi.

    Signed-off-by: Fabio Estevam <festevam@gmail.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>

> 
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		ranges = <0x0 0x0 0x0 0x40000000>;
> > +
> > +		per_bridge3: bus@29000000 {
> > +			compatible = "simple-bus";
> > +			reg = <0x29000000 0x800000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +
> > +			wdog3: watchdog@292a0000 {
> > +				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
> > +				reg = <0x292a0000 0x10000>;
> > +				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
> > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
> > +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_SOSC_DIV2>;
> > +				timeout-sec = <40>;
> > +			};
> > +
> > +			cgc1: clock-controller@292c0000 {
> > +				compatible = "fsl,imx8ulp-cgc1";
> > +				reg = <0x292c0000 0x10000>;
> > +				clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> > +				clock-names = "rosc", "sosc", "frosc", "lposc";
> > +				#clock-cells = <1>;
> > +			};
> > +
> > +			pcc3: clock-controller@292d0000 {
> > +				compatible = "fsl,imx8ulp-pcc3";
> > +				reg = <0x292d0000 0x10000>;
> > +				#clock-cells = <1>;
> > +			};
> > +
> > +			tpm5: tpm@29340000 {
> > +				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
> > +				reg = <0x29340000 0x1000>;
> > +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
> > +					 <&pcc3 IMX8ULP_CLK_TPM5>;
> > +				clock-names = "ipg", "per";
> > +				status = "disabled";
> > +			};
> > +
> > +			lpi2c4: i2c@29370000 {
> > +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +				reg = <0x29370000 0x10000>;
> > +				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
> > +					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
> > +				clock-names = "per", "ipg";
> > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
> > +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> > +				assigned-clock-rates = <48000000>;
> > +				status = "disabled";
> > +			};
> > +
> > +			lpi2c5: i2c@29380000 {
> > +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +				reg = <0x29380000 0x10000>;
> > +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
> > +					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
> > +				clock-names = "per", "ipg";
> > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
> > +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> > +				assigned-clock-rates = <48000000>;
> > +				status = "disabled";
> > +			};
> > +
> > +			lpuart4: serial@29390000 {
> > +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> > +				reg = <0x29390000 0x1000>;
> > +				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
> > +				clock-names = "ipg";
> > +				status = "disabled";
> > +			};
> > +
> > +			lpuart5: serial@293a0000 {
> > +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> > +				reg = <0x293a0000 0x1000>;
> > +				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
> > +				clock-names = "ipg";
> > +				status = "disabled";
> > +			};
> > +
> > +			lpspi4: spi@293b0000 {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
> > +				reg = <0x293b0000 0x10000>;
> > +				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
> > +					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
> > +				clock-names = "per", "ipg";
> > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
> > +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> > +				assigned-clock-rates = <16000000>;
> > +				status = "disabled";
> > +			};
> > +
> > +			lpspi5: spi@293c0000 {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
> > +				reg = <0x293c0000 0x10000>;
> > +				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
> > +					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
> > +				clock-names = "per", "ipg";
> > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
> > +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> > +				assigned-clock-rates = <16000000>;
> > +				status = "disabled";
> > +			};
> > +		};
> > +
> > +		per_bridge4: bus@29800000 {
> > +			compatible = "simple-bus";
> > +			reg = <0x29800000 0x800000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +
> > +			pcc4: clock-controller@29800000 {
> > +				compatible = "fsl,imx8ulp-pcc4";
> > +				reg = <0x29800000 0x10000>;
> > +				#clock-cells = <1>;
> > +			};
> > +
> > +			lpi2c6: i2c@29840000 {
> > +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +				reg = <0x29840000 0x10000>;
> > +				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
> > +					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
> > +				clock-names = "per", "ipg";
> > +				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
> > +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> > +				assigned-clock-rates = <48000000>;
> > +				status = "disabled";
> > +			};
> > +
> > +			lpi2c7: i2c@29850000 {
> > +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +				reg = <0x29850000 0x10000>;
> > +				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
> > +					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
> > +				clock-names = "per", "ipg";
> > +				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
> > +				assigned-clock-parents = <&cgc1
> IMX8ULP_CLK_XBAR_DIVBUS>;
> > +				assigned-clock-rates = <48000000>;
> > +				status = "disabled";
> > +			};
> > +
> > +			lpuart6: serial@29860000 {
> > +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> > +				reg = <0x29860000 0x1000>;
> > +				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
> > +				clock-names = "ipg";
> > +				status = "disabled";
> > +			};
> > +
> > +			lpuart7: serial@29870000 {
> > +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> > +				reg = <0x29870000 0x1000>;
> > +				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
> > +				clock-names = "ipg";
> > +				status = "disabled";
> > +			};
> > +
> > +			iomuxc1: pinctrl@298c0000 {
> > +				compatible = "fsl,imx8ulp-iomuxc1";
> 
> I know this binding is already landed.  Just curious why there is a suffix
> number in the compatible.

There is two iomuxc, one is for M33, one is for A35.
Similar with i.MX7ULP,  we use a suffix here.

Thanks,
Peng.

> 
> Shawn
> 
> > +				reg = <0x298c0000 0x10000>;
> > +			};
> > +
> > +			usdhc0: mmc@298d0000 {
> > +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> > +				reg = <0x298d0000 0x10000>;
> > +				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> > +					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
> > +					 <&pcc4 IMX8ULP_CLK_USDHC0>;
> > +				clock-names = "ipg", "ahb", "per";
> > +				fsl,tuning-start-tap = <20>;
> > +				fsl,tuning-step= <2>;
> > +				bus-width = <4>;
> > +				status = "disabled";
> > +			};
> > +
> > +			usdhc1: mmc@298e0000 {
> > +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> > +				reg = <0x298e0000 0x10000>;
> > +				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> > +					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
> > +					 <&pcc4 IMX8ULP_CLK_USDHC1>;
> > +				clock-names = "ipg", "ahb", "per";
> > +				fsl,tuning-start-tap = <20>;
> > +				fsl,tuning-step= <2>;
> > +				bus-width = <4>;
> > +				status = "disabled";
> > +			};
> > +
> > +			usdhc2: mmc@298f0000 {
> > +				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
> > +				reg = <0x298f0000 0x10000>;
> > +				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
> > +					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
> > +					 <&pcc4 IMX8ULP_CLK_USDHC2>;
> > +				clock-names = "ipg", "ahb", "per";
> > +				fsl,tuning-start-tap = <20>;
> > +				fsl,tuning-step= <2>;
> > +				bus-width = <4>;
> > +				status = "disabled";
> > +			};
> > +		};
> > +
> > +		gpioe: gpio@2d000000 {
> > +				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> > +				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
> > +				gpio-controller;
> > +				#gpio-cells = <2>;
> > +				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> > +				interrupt-controller;
> > +				#interrupt-cells = <2>;
> > +				clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
> > +					 <&pcc4 IMX8ULP_CLK_PCTLE>;
> > +				clock-names = "gpio", "port";
> > +				gpio-ranges = <&iomuxc1 0 32 24>;
> > +		};
> > +
> > +		gpiof: gpio@2d010000 {
> > +				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> > +				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
> > +				gpio-controller;
> > +				#gpio-cells = <2>;
> > +				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> > +				interrupt-controller;
> > +				#interrupt-cells = <2>;
> > +				clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
> > +					 <&pcc4 IMX8ULP_CLK_PCTLF>;
> > +				clock-names = "gpio", "port";
> > +				gpio-ranges = <&iomuxc1 0 64 32>;
> > +		};
> > +
> > +		per_bridge5: bus@2d800000 {
> > +			compatible = "simple-bus";
> > +			reg = <0x2d800000 0x800000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +
> > +			cgc2: clock-controller@2da60000 {
> > +				compatible = "fsl,imx8ulp-cgc2";
> > +				reg = <0x2da60000 0x10000>;
> > +				clocks = <&sosc>, <&frosc>;
> > +				clock-names = "sosc", "frosc";
> > +				#clock-cells = <1>;
> > +			};
> > +
> > +			pcc5: clock-controller@2da70000 {
> > +				compatible = "fsl,imx8ulp-pcc5";
> > +				reg = <0x2da70000 0x10000>;
> > +				#clock-cells = <1>;
> > +			};
> > +		};
> > +
> > +		gpiod: gpio@2e200000 {
> > +			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
> > +			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
> > +			gpio-controller;
> > +			#gpio-cells = <2>;
> > +			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-controller;
> > +			#interrupt-cells = <2>;
> > +			clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
> > +				 <&pcc5 IMX8ULP_CLK_RGPIOD>;
> > +			clock-names = "gpio", "port";
> > +			gpio-ranges = <&iomuxc1 0 0 24>;
> > +		};
> > +	};
> > +};
> > --
> > 2.25.1
> >

Re: [PATCH V6 6/7] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp

[Shawn Guo]

On Mon, Dec 06, 2021 at 03:01:12AM +0000, Peng Fan wrote:
> Hi Shawn,
> 
> > Subject: Re: [PATCH V6 6/7] arm64: dts: imx8ulp: Add the basic dtsi file for
> > imx8ulp
> > 
> > On Fri, Nov 26, 2021 at 03:40:01PM +0800, Peng Fan (OSS) wrote:
> > > From: Jacky Bai <ping.bai@nxp.com>
> > >
> > > Add the basic dtsi support for i.MX8ULP.
> > >
> > > i.MX 8ULP is part of the ULP family with emphasis on extreme low-power
> > > techniques using the 28 nm fully depleted silicon on insulator
> > > process. Like i.MX 7ULP, i.MX 8ULP continues to be based on asymmetric
> > > architecture, however will add a third DSP domain for advanced
> > > voice/audio capability and a Graphics domain where it is possible to
> > > access graphics resources from the application side or the realtime
> > > side.
> > >
> > > Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> > > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > ---
> > >
> > >   - v6
> > >    rebase
> > >
> > >   - v5
> > >    Add R-b tag
> > >
> > >   - v4
> > >    Fix build error after rebase
> > >    Drop usb nodes and alias, drop fec node
> > >
> > >   - v3 changes:
> > >     no
> > >
> > >   - v2 changes:
> > >     update the license
> > >     update the compatible property for usb related node
> > >
> > >
> > >  .../boot/dts/freescale/imx8ulp-pinfunc.h      | 978
> > ++++++++++++++++++
> > >  arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 396 +++++++
> > >  2 files changed, 1374 insertions(+)
> > >  create mode 100755 arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h
> > >  create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > 
> > <snip>
> > 
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > > new file mode 100644
> > > index 000000000000..fb8714379026
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > > @@ -0,0 +1,396 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + * Copyright 2021 NXP
> > > + */
> > > +
> > > +#include <dt-bindings/clock/imx8ulp-clock.h>
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > +#include "imx8ulp-pinfunc.h"
> > > +
> > > +/ {
> > > +	interrupt-parent = <&gic>;
> > > +	#address-cells = <2>;
> > > +	#size-cells = <2>;
> > > +
> > > +	aliases {
> > > +		gpio0 = &gpiod;
> > > +		gpio1 = &gpioe;
> > > +		gpio2 = &gpiof;
> > > +		mmc0 = &usdhc0;
> > > +		mmc1 = &usdhc1;
> > > +		mmc2 = &usdhc2;
> > > +		serial0 = &lpuart4;
> > > +		serial1 = &lpuart5;
> > > +		serial2 = &lpuart6;
> > > +		serial3 = &lpuart7;
> > > +	};
> > > +
> > > +	cpus {
> > > +		#address-cells = <2>;
> > > +		#size-cells = <0>;
> > > +
> > > +		A35_0: cpu@0 {
> > > +			device_type = "cpu";
> > > +			compatible = "arm,cortex-a35";
> > > +			reg = <0x0 0x0>;
> > > +			enable-method = "psci";
> > > +			next-level-cache = <&A35_L2>;
> > > +		};
> > > +
> > > +		A35_1: cpu@1 {
> > > +			device_type = "cpu";
> > > +			compatible = "arm,cortex-a35";
> > > +			reg = <0x0 0x1>;
> > > +			enable-method = "psci";
> > > +			next-level-cache = <&A35_L2>;
> > > +		};
> > > +
> > > +		A35_L2: l2-cache0 {
> > > +			compatible = "cache";
> > > +		};
> > > +	};
> > > +
> > > +	gic: interrupt-controller@2d400000 {
> > > +		compatible = "arm,gic-v3";
> > > +		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
> > > +		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base)
> > */
> > > +		#interrupt-cells = <3>;
> > > +		interrupt-controller;
> > > +		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > > +	};
> > > +
> > > +	psci {
> > > +		compatible = "arm,psci-1.0";
> > > +		method = "smc";
> > > +	};
> > > +
> > > +	timer {
> > > +		compatible = "arm,armv8-timer";
> > > +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical
> > Secure */
> > > +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical
> > Non-Secure */
> > > +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> > > +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> > > +	};
> > > +
> > > +	frosc: clock-frosc {
> > > +		compatible = "fixed-clock";
> > > +		clock-frequency = <192000000>;
> > > +		clock-output-names = "frosc";
> > > +		#clock-cells = <0>;
> > > +	};
> > > +
> > > +	lposc: clock-lposc {
> > > +		compatible = "fixed-clock";
> > > +		clock-frequency = <1000000>;
> > > +		clock-output-names = "lposc";
> > > +		#clock-cells = <0>;
> > > +	};
> > > +
> > > +	rosc: clock-rosc {
> > > +		compatible = "fixed-clock";
> > > +		clock-frequency = <32768>;
> > > +		clock-output-names = "rosc";
> > > +		#clock-cells = <0>;
> > > +	};
> > > +
> > > +	sosc: clock-sosc {
> > > +		compatible = "fixed-clock";
> > > +		clock-frequency = <24000000>;
> > > +		clock-output-names = "sosc";
> > > +		#clock-cells = <0>;
> > > +	};
> > > +
> > > +	soc@0 {
> > 
> > Why do we need unit-address @0 here?
> 
> I found there is patch which adds unit address, so I think we need @0 here.

Ah, okay, I will have to keep reminding myself that ranges requires
unit-address as well.

> commit 951c1d37f691027f149bbc58bbf0c207450a3654
> Author: Fabio Estevam <festevam@gmail.com>
> Date:   Tue May 28 16:00:21 2019 -0300
> 
>     arm64: dts: imx8mm: Pass a unit name for the 'soc' node
> 
>     The 'soc' name needs a unit name to match its 'ranges' property.
> 
>     Pass the unit name in order to fix the following dtc build warning
>     with W=1:
> 
>     arch/arm64/boot/dts/freescale/imx8mm.dtsi:203.6-754.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
> 
>     This also aligns with imx8mq.dtsi.
> 
>     Signed-off-by: Fabio Estevam <festevam@gmail.com>
>     Signed-off-by: Shawn Guo <shawnguo@kernel.org>
> 
> > 
> > > +		compatible = "simple-bus";
> > > +		#address-cells = <1>;
> > > +		#size-cells = <1>;
> > > +		ranges = <0x0 0x0 0x0 0x40000000>;
> > > +
> > > +		per_bridge3: bus@29000000 {
> > > +			compatible = "simple-bus";
> > > +			reg = <0x29000000 0x800000>;
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			ranges;
> > > +
> > > +			wdog3: watchdog@292a0000 {
> > > +				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
> > > +				reg = <0x292a0000 0x10000>;
> > > +				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
> > > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
> > > +				assigned-clock-parents = <&cgc1
> > IMX8ULP_CLK_SOSC_DIV2>;
> > > +				timeout-sec = <40>;
> > > +			};
> > > +
> > > +			cgc1: clock-controller@292c0000 {
> > > +				compatible = "fsl,imx8ulp-cgc1";
> > > +				reg = <0x292c0000 0x10000>;
> > > +				clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
> > > +				clock-names = "rosc", "sosc", "frosc", "lposc";
> > > +				#clock-cells = <1>;
> > > +			};
> > > +
> > > +			pcc3: clock-controller@292d0000 {
> > > +				compatible = "fsl,imx8ulp-pcc3";
> > > +				reg = <0x292d0000 0x10000>;
> > > +				#clock-cells = <1>;
> > > +			};
> > > +
> > > +			tpm5: tpm@29340000 {
> > > +				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
> > > +				reg = <0x29340000 0x1000>;
> > > +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
> > > +					 <&pcc3 IMX8ULP_CLK_TPM5>;
> > > +				clock-names = "ipg", "per";
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpi2c4: i2c@29370000 {
> > > +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> > > +				reg = <0x29370000 0x10000>;
> > > +				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
> > > +					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
> > > +				clock-names = "per", "ipg";
> > > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
> > > +				assigned-clock-parents = <&cgc1
> > IMX8ULP_CLK_XBAR_DIVBUS>;
> > > +				assigned-clock-rates = <48000000>;
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpi2c5: i2c@29380000 {
> > > +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> > > +				reg = <0x29380000 0x10000>;
> > > +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
> > > +					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
> > > +				clock-names = "per", "ipg";
> > > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
> > > +				assigned-clock-parents = <&cgc1
> > IMX8ULP_CLK_XBAR_DIVBUS>;
> > > +				assigned-clock-rates = <48000000>;
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpuart4: serial@29390000 {
> > > +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> > > +				reg = <0x29390000 0x1000>;
> > > +				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
> > > +				clock-names = "ipg";
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpuart5: serial@293a0000 {
> > > +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> > > +				reg = <0x293a0000 0x1000>;
> > > +				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
> > > +				clock-names = "ipg";
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpspi4: spi@293b0000 {
> > > +				#address-cells = <1>;
> > > +				#size-cells = <0>;
> > > +				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
> > > +				reg = <0x293b0000 0x10000>;
> > > +				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
> > > +					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
> > > +				clock-names = "per", "ipg";
> > > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
> > > +				assigned-clock-parents = <&cgc1
> > IMX8ULP_CLK_XBAR_DIVBUS>;
> > > +				assigned-clock-rates = <16000000>;
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpspi5: spi@293c0000 {
> > > +				#address-cells = <1>;
> > > +				#size-cells = <0>;
> > > +				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
> > > +				reg = <0x293c0000 0x10000>;
> > > +				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
> > > +					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
> > > +				clock-names = "per", "ipg";
> > > +				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
> > > +				assigned-clock-parents = <&cgc1
> > IMX8ULP_CLK_XBAR_DIVBUS>;
> > > +				assigned-clock-rates = <16000000>;
> > > +				status = "disabled";
> > > +			};
> > > +		};
> > > +
> > > +		per_bridge4: bus@29800000 {
> > > +			compatible = "simple-bus";
> > > +			reg = <0x29800000 0x800000>;
> > > +			#address-cells = <1>;
> > > +			#size-cells = <1>;
> > > +			ranges;
> > > +
> > > +			pcc4: clock-controller@29800000 {
> > > +				compatible = "fsl,imx8ulp-pcc4";
> > > +				reg = <0x29800000 0x10000>;
> > > +				#clock-cells = <1>;
> > > +			};
> > > +
> > > +			lpi2c6: i2c@29840000 {
> > > +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> > > +				reg = <0x29840000 0x10000>;
> > > +				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
> > > +					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
> > > +				clock-names = "per", "ipg";
> > > +				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
> > > +				assigned-clock-parents = <&cgc1
> > IMX8ULP_CLK_XBAR_DIVBUS>;
> > > +				assigned-clock-rates = <48000000>;
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpi2c7: i2c@29850000 {
> > > +				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
> > > +				reg = <0x29850000 0x10000>;
> > > +				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
> > > +					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
> > > +				clock-names = "per", "ipg";
> > > +				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
> > > +				assigned-clock-parents = <&cgc1
> > IMX8ULP_CLK_XBAR_DIVBUS>;
> > > +				assigned-clock-rates = <48000000>;
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpuart6: serial@29860000 {
> > > +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> > > +				reg = <0x29860000 0x1000>;
> > > +				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
> > > +				clock-names = "ipg";
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			lpuart7: serial@29870000 {
> > > +				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
> > > +				reg = <0x29870000 0x1000>;
> > > +				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> > > +				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
> > > +				clock-names = "ipg";
> > > +				status = "disabled";
> > > +			};
> > > +
> > > +			iomuxc1: pinctrl@298c0000 {
> > > +				compatible = "fsl,imx8ulp-iomuxc1";
> > 
> > I know this binding is already landed.  Just curious why there is a suffix
> > number in the compatible.
> 
> There is two iomuxc, one is for M33, one is for A35.
> Similar with i.MX7ULP,  we use a suffix here.

Thanks for the info!

Shawn

Re: [PATCH V6 5/7] dt-bindings: arm: fsl: Add binding for imx8ulp evk

[Shawn Guo]

On Fri, Nov 26, 2021 at 03:40:00PM +0800, Peng Fan (OSS) wrote:
> From: Jacky Bai <ping.bai@nxp.com>
> 
> Add the dt binding for i.MX8ULP EVK board.
> 
> i.MX 8ULP is part of the ULP family with emphasis on extreme
> low-power techniques using the 28 nm fully depleted silicon on
> insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
> based on asymmetric architecture, however will add a third DSP
> domain for advanced voice/audio capability and a Graphics domain
> where it is possible to access graphics resources from the
> application side or the realtime side.
> 
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied, thanks!

Re: [PATCH V6 6/7] arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp

[Shawn Guo]

On Fri, Nov 26, 2021 at 03:40:01PM +0800, Peng Fan (OSS) wrote:
> From: Jacky Bai <ping.bai@nxp.com>
> 
> Add the basic dtsi support for i.MX8ULP.
> 
> i.MX 8ULP is part of the ULP family with emphasis on extreme
> low-power techniques using the 28 nm fully depleted silicon on
> insulator process. Like i.MX 7ULP, i.MX 8ULP continues to be
> based on asymmetric architecture, however will add a third DSP
> domain for advanced voice/audio capability and a Graphics domain
> where it is possible to access graphics resources from the
> application side or the realtime side.
> 
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>

Applied, thanks!

Re: [PATCH V6 7/7] arm64: dts: imx8ulp: Add the basic dts for imx8ulp evk board

[Shawn Guo]

On Fri, Nov 26, 2021 at 03:40:02PM +0800, Peng Fan (OSS) wrote:
> From: Jacky Bai <ping.bai@nxp.com>
> 
> Add the basic dts file for i.MX8ULP EVK board.
> Only the necessary devices for minimal system boot up are enabled:
> enet, emmc, usb, console uart.
> 
> some of the devices' pin status may lost during low power mode,
> so additional sleep pinctrl properties are included by default.
> 
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Applied, thanks!