* [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64
@ 2012-07-09 13:13 Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 01/11] arch/powerpc: Use hpt_va to compute virtual address Aneesh Kumar K.V
` (10 more replies)
0 siblings, 11 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
Hi,
This patchset include patches for supporting 64TB with ppc64. I haven't booted
this on hardware with 64TB memory yet. But they boot fine on real hardware with
less memory. Changes extend VSID bits to 38 bits for a 256MB segment
and 26 bits for 1TB segments.
Changes from V2:
* Fix few FIXMEs in the patchset. I have added them as separate patch for
easier review. That should help us to drop those changes if we don't agree.
Changes from V1:
* Drop the usage of structure (struct virt_addr) to carry virtual address.
We now represent virtual address via vpn which is virtual address shifted
right 12 bits.
Thanks,
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH -V3 01/11] arch/powerpc: Use hpt_va to compute virtual address
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-22 23:17 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 02/11] arch/powerpc: Simplify hpte_decode Aneesh Kumar K.V
` (9 subsequent siblings)
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Don't open code the same
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/platforms/cell/beat_htab.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index 943c9d3..b83077e 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -259,7 +259,7 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
u64 dummy0, dummy1;
vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
- va = (vsid << 28) | (ea & 0x0fffffff);
+ va = hpt_va(ea, vsid, MMU_SEGSIZE_256M);
raw_spin_lock(&beat_htab_lock);
slot = beat_lpar_hpte_find(va, psize);
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 02/11] arch/powerpc: Simplify hpte_decode
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 01/11] arch/powerpc: Use hpt_va to compute virtual address Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-22 23:26 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
` (8 subsequent siblings)
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This patch simplify hpte_decode for easy switching of virtual address to
virtual page number in the later patch
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_native_64.c | 49 ++++++++++++++++++++++----------------
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 90039bc..660b8bb 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -351,9 +351,10 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
int *psize, int *ssize, unsigned long *va)
{
+ unsigned long avpn, pteg, vpi;
unsigned long hpte_r = hpte->r;
unsigned long hpte_v = hpte->v;
- unsigned long avpn;
+ unsigned long vsid, seg_off;
int i, size, shift, penc;
if (!(hpte_v & HPTE_V_LARGE))
@@ -380,32 +381,38 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
}
/* This works for all page sizes, and for 256M and 1T segments */
+ *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
shift = mmu_psize_defs[size].shift;
- avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm) << 23;
-
- if (shift < 23) {
- unsigned long vpi, vsid, pteg;
- pteg = slot / HPTES_PER_GROUP;
- if (hpte_v & HPTE_V_SECONDARY)
- pteg = ~pteg;
- switch (hpte_v >> HPTE_V_SSIZE_SHIFT) {
- case MMU_SEGSIZE_256M:
- vpi = ((avpn >> 28) ^ pteg) & htab_hash_mask;
- break;
- case MMU_SEGSIZE_1T:
- vsid = avpn >> 40;
+ avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
+ pteg = slot / HPTES_PER_GROUP;
+ if (hpte_v & HPTE_V_SECONDARY)
+ pteg = ~pteg;
+
+ switch (*ssize) {
+ case MMU_SEGSIZE_256M:
+ /* We only have 28 - 23 bits of seg_off in avpn */
+ seg_off = (avpn & 0x1f) << 23;
+ vsid = avpn >> 5;
+ /* We can find more bits from the pteg value */
+ if (shift < 23) {
+ vpi = (vsid ^ pteg) & htab_hash_mask;
+ seg_off |= vpi << shift;
+ }
+ *va = vsid << SID_SHIFT | seg_off;
+ case MMU_SEGSIZE_1T:
+ /* We only have 40 - 23 bits of seg_off in avpn */
+ seg_off = (avpn & 0x1ffff) << 23;
+ vsid = avpn >> 17;
+ if (shift < 23) {
vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
- break;
- default:
- avpn = vpi = size = 0;
+ seg_off |= vpi << shift;
}
- avpn |= (vpi << mmu_psize_defs[size].shift);
+ *va = vsid << SID_SHIFT_1T | seg_off;
+ default:
+ *va = size = 0;
}
-
- *va = avpn;
*psize = size;
- *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
}
/*
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 01/11] arch/powerpc: Use hpt_va to compute virtual address Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 02/11] arch/powerpc: Simplify hpte_decode Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-09 22:41 ` Stephen Rothwell
` (2 more replies)
2012-07-09 13:13 ` [PATCH -V3 04/11] arch/powerpc: Rename va " Aneesh Kumar K.V
` (7 subsequent siblings)
10 siblings, 3 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This patch convert different functions to take virtual page number
instead of virtual address. Virtual page number is virtual address
shifted right by VPN_SHIFT (12) bits. This enable us to have an
address range of upto 76 bits.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 70 +++++++++++++++++----
arch/powerpc/include/asm/pte-hash64-64k.h | 18 +++---
arch/powerpc/kvm/book3s_64_mmu_host.c | 2 +-
arch/powerpc/mm/hash_low_64.S | 97 ++++++++++++++++++-----------
arch/powerpc/mm/hash_native_64.c | 36 ++++++++---
arch/powerpc/mm/hash_utils_64.c | 6 +-
arch/powerpc/mm/hugetlbpage-hash64.c | 2 +-
arch/powerpc/mm/tlb_hash64.c | 2 +-
arch/powerpc/platforms/cell/beat_htab.c | 2 +-
arch/powerpc/platforms/pseries/lpar.c | 20 +-----
10 files changed, 164 insertions(+), 91 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 1c65a59..1c984a6 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -14,6 +14,7 @@
#include <asm/asm-compat.h>
#include <asm/page.h>
+#include <asm/bug.h>
/*
* Segment table
@@ -154,9 +155,25 @@ struct mmu_psize_def
#define MMU_SEGSIZE_256M 0
#define MMU_SEGSIZE_1T 1
+/*
+ * encode page number shift.
+ * Inorder to fit the 78 bit va in a 64 bit variable we shift the va by
+ * 12 bits. This enable us to address upto 76 bit va.
+ * For hpt hash from a va we can ignore the page size bits of va and for
+ * hpte encoding we ignore upto 23 bits of va. So ignoring lower 12 bits ensure
+ * we work in all cases including 4k page size.
+ */
+#define VPN_SHIFT 12
#ifndef __ASSEMBLY__
+static inline int segment_shift(int ssize)
+{
+ if (ssize == MMU_SEGSIZE_256M)
+ return SID_SHIFT;
+ return SID_SHIFT_1T;
+}
+
/*
* The current system page and segment sizes
*/
@@ -180,6 +197,30 @@ extern unsigned long tce_alloc_start, tce_alloc_end;
extern int mmu_ci_restrictions;
/*
+ * This computes the AVPN and B fields of the first dword of a HPTE,
+ * for use when we want to match an existing PTE. The bottom 7 bits
+ * of the returned value are zero.
+ */
+static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
+ int ssize)
+{
+ unsigned long v;
+ /*
+ * The AVA field omits the low-order 23 bits of the 78 bits VA.
+ * These bits are not needed in the PTE, because the
+ * low-order b of these bits are part of the byte offset
+ * into the virtual page and, if b < 23, the high-order
+ * 23-b of these bits are always used in selecting the
+ * PTEGs to be searched
+ */
+ BUG_ON(VPN_SHIFT > 23);
+ v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
+ v <<= HPTE_V_AVPN_SHIFT;
+ v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
+ return v;
+}
+
+/*
* This function sets the AVPN and L fields of the HPTE appropriately
* for the page size
*/
@@ -187,11 +228,9 @@ static inline unsigned long hpte_encode_v(unsigned long va, int psize,
int ssize)
{
unsigned long v;
- v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
- v <<= HPTE_V_AVPN_SHIFT;
+ v = hpte_encode_avpn(va, psize, ssize);
if (psize != MMU_PAGE_4K)
v |= HPTE_V_LARGE;
- v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
return v;
}
@@ -216,14 +255,16 @@ static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
}
/*
- * Build a VA given VSID, EA and segment size
+ * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
*/
-static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
+static inline unsigned long hpt_vpn(unsigned long ea, unsigned long vsid,
int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return (vsid << 28) | (ea & 0xfffffffUL);
- return (vsid << 40) | (ea & 0xffffffffffUL);
+ unsigned long mask;
+ int s_shift = segment_shift(ssize);
+
+ mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
+ return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
}
/*
@@ -233,13 +274,20 @@ static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
int ssize)
{
+ int mask;
unsigned long hash, vsid;
+ BUG_ON(shift < VPN_SHIFT);
+
if (ssize == MMU_SEGSIZE_256M) {
- hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
+ mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
+ hash = ((va >> (SID_SHIFT - VPN_SHIFT)) & 0x0000007fffffffff) ^
+ (((va & mask) >> (shift - VPN_SHIFT)) & 0xffff);
} else {
- vsid = va >> 40;
- hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
+ mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
+ vsid = va >> (SID_SHIFT_1T - VPN_SHIFT);
+ hash = (vsid & 0xffffff) ^ ((vsid << 25) & 0x7fffffffff) ^
+ (((va & mask) >> (shift - VPN_SHIFT)) & 0xfffffff);
}
return hash & 0x7fffffffffUL;
}
diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
index 59247e8..eedf427 100644
--- a/arch/powerpc/include/asm/pte-hash64-64k.h
+++ b/arch/powerpc/include/asm/pte-hash64-64k.h
@@ -58,14 +58,16 @@
/* Trick: we set __end to va + 64k, which happens works for
* a 16M page as well as we want only one iteration
*/
-#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
- do { \
- unsigned long __end = va + PAGE_SIZE; \
- unsigned __split = (psize == MMU_PAGE_4K || \
- psize == MMU_PAGE_64K_AP); \
- shift = mmu_psize_defs[psize].shift; \
- for (index = 0; va < __end; index++, va += (1L << shift)) { \
- if (!__split || __rpte_sub_valid(rpte, index)) do { \
+#define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \
+ do { \
+ unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT)); \
+ unsigned __split = (psize == MMU_PAGE_4K || \
+ psize == MMU_PAGE_64K_AP); \
+ shift = mmu_psize_defs[psize].shift; \
+ for (index = 0; vpn < __end; index++, \
+ vpn += (1L << (shift - VPN_SHIFT))) { \
+ if (!__split || __rpte_sub_valid(rpte, index)) \
+ do {
#define pte_iterate_hashed_end() } while(0); } } while(0)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index 10fc8ec..9d184f1 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -117,7 +117,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
}
vsid = map->host_vsid;
- va = hpt_va(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
+ va = hpt_vpn(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
if (!orig_pte->may_write)
rflags |= HPTE_R_PP;
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index a242b5d..534cc26 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -71,7 +71,7 @@ _GLOBAL(__hash_page_4K)
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"
- * r29 is "va"
+ * r29 is vpn
* r28 is a hash value
* r27 is hashtab mask (maybe dynamic patched instead ?)
*/
@@ -119,10 +119,10 @@ BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- /* Calc va and put it in r29 */
- rldicr r29,r5,28,63-28
- rldicl r3,r3,0,36
- or r29,r3,r29
+ /* Calc vpn and put it in r29 */
+ sldi r29,r5,SID_SHIFT - VPN_SHIFT
+ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
+ or r29,r28,r29
/* Calculate hash value for primary slot and store it in r28 */
rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
@@ -130,14 +130,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
xor r28,r5,r0
b 4f
-3: /* Calc VA and hash in r29 and r28 for 1T segment */
- sldi r29,r5,40 /* vsid << 40 */
- clrldi r3,r3,24 /* ea & 0xffffffffff */
+3: /* Calc vpn and put it in r29 */
+ sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
+ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
+ or r29,r28,r29
+
+ /*
+ * calculate hash value for primary slot and
+ * store it in r28 for 1T segment
+ */
rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
clrldi r5,r5,40 /* vsid & 0xffffff */
rldicl r0,r3,64-12,36 /* (ea >> 12) & 0xfffffff */
xor r28,r28,r5
- or r29,r3,r29 /* VA */
xor r28,r28,r0 /* hash */
/* Convert linux PTE bits into HW equivalents */
@@ -193,7 +198,7 @@ htab_insert_pte:
/* Call ppc_md.hpte_insert */
ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
+ mr r4,r29 /* Retrieve vpn */
li r7,0 /* !bolted, !secondary */
li r8,MMU_PAGE_4K /* page size */
ld r9,STK_PARM(r9)(r1) /* segment size */
@@ -216,7 +221,7 @@ _GLOBAL(htab_call_hpte_insert1)
/* Call ppc_md.hpte_insert */
ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
+ mr r4,r29 /* Retrieve vpn */
li r7,HPTE_V_SECONDARY /* !bolted, secondary */
li r8,MMU_PAGE_4K /* page size */
ld r9,STK_PARM(r9)(r1) /* segment size */
@@ -286,7 +291,7 @@ htab_modify_pte:
add r3,r0,r3 /* add slot idx */
/* Call ppc_md.hpte_updatepp */
- mr r5,r29 /* va */
+ mr r5,r29 /* vpn */
li r6,MMU_PAGE_4K /* page size */
ld r7,STK_PARM(r9)(r1) /* segment size */
ld r8,STK_PARM(r8)(r1) /* get "local" param */
@@ -347,7 +352,7 @@ _GLOBAL(__hash_page_4K)
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"
- * r29 is "va"
+ * r29 is vpn
* r28 is a hash value
* r27 is hashtab mask (maybe dynamic patched instead ?)
* r26 is the hidx mask
@@ -402,10 +407,14 @@ BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- /* Calc va and put it in r29 */
- rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */
- rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */
- or r29,r3,r29 /* r29 = va */
+ /* Calc vpn and put it in r29 */
+ sldi r29,r5,SID_SHIFT - VPN_SHIFT
+ /*
+ * clrldi r3,r3,64 - SID_SHIFT --> ea & 0xfffffff
+ * srdi r28,r3,VPN_SHIFT
+ */
+ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
+ or r29,r28,r29
/* Calculate hash value for primary slot and store it in r28 */
rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
@@ -413,14 +422,23 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
xor r28,r5,r0
b 4f
-3: /* Calc VA and hash in r29 and r28 for 1T segment */
- sldi r29,r5,40 /* vsid << 40 */
- clrldi r3,r3,24 /* ea & 0xffffffffff */
+3: /* Calc vpn and put it in r29 */
+ sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
+ /*
+ * clrldi r3,r3,64 - SID_SHIFT_1T --> ea & 0xffffffffff
+ * srdi r28,r3,VPN_SHIFT
+ */
+ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
+ or r29,r28,r29
+
+ /*
+ * Calculate hash value for primary slot and
+ * store it in r28 for 1T segment
+ */
rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
clrldi r5,r5,40 /* vsid & 0xffffff */
rldicl r0,r3,64-12,36 /* (ea >> 12) & 0xfffffff */
xor r28,r28,r5
- or r29,r3,r29 /* VA */
xor r28,r28,r0 /* hash */
/* Convert linux PTE bits into HW equivalents */
@@ -496,7 +514,7 @@ htab_special_pfn:
/* Call ppc_md.hpte_insert */
ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
+ mr r4,r29 /* Retrieve vpn */
li r7,0 /* !bolted, !secondary */
li r8,MMU_PAGE_4K /* page size */
ld r9,STK_PARM(r9)(r1) /* segment size */
@@ -523,7 +541,7 @@ _GLOBAL(htab_call_hpte_insert1)
/* Call ppc_md.hpte_insert */
ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
+ mr r4,r29 /* Retrieve vpn */
li r7,HPTE_V_SECONDARY /* !bolted, secondary */
li r8,MMU_PAGE_4K /* page size */
ld r9,STK_PARM(r9)(r1) /* segment size */
@@ -555,7 +573,7 @@ _GLOBAL(htab_call_hpte_remove)
* useless now that the segment has been switched to 4k pages.
*/
htab_inval_old_hpte:
- mr r3,r29 /* virtual addr */
+ mr r3,r29 /* vpn */
mr r4,r31 /* PTE.pte */
li r5,0 /* PTE.hidx */
li r6,MMU_PAGE_64K /* psize */
@@ -628,7 +646,7 @@ htab_modify_pte:
add r3,r0,r3 /* add slot idx */
/* Call ppc_md.hpte_updatepp */
- mr r5,r29 /* va */
+ mr r5,r29 /* vpn */
li r6,MMU_PAGE_4K /* page size */
ld r7,STK_PARM(r9)(r1) /* segment size */
ld r8,STK_PARM(r8)(r1) /* get "local" param */
@@ -684,7 +702,7 @@ _GLOBAL(__hash_page_64K)
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"
- * r29 is "va"
+ * r29 is vpn
* r28 is a hash value
* r27 is hashtab mask (maybe dynamic patched instead ?)
*/
@@ -737,10 +755,10 @@ BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- /* Calc va and put it in r29 */
- rldicr r29,r5,28,63-28
- rldicl r3,r3,0,36
- or r29,r3,r29
+ /* Calc vpn and put it in r29 */
+ sldi r29,r5,SID_SHIFT - VPN_SHIFT
+ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
+ or r29,r28,r29
/* Calculate hash value for primary slot and store it in r28 */
rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
@@ -748,14 +766,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
xor r28,r5,r0
b 4f
-3: /* Calc VA and hash in r29 and r28 for 1T segment */
- sldi r29,r5,40 /* vsid << 40 */
- clrldi r3,r3,24 /* ea & 0xffffffffff */
+3: /* Calc vpn and put it in r29 */
+ sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
+ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
+ or r29,r28,r29
+
+ /*
+ * calculate hash value for primary slot and
+ * store it in r28 for 1T segment
+ */
rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
clrldi r5,r5,40 /* vsid & 0xffffff */
rldicl r0,r3,64-16,40 /* (ea >> 16) & 0xffffff */
xor r28,r28,r5
- or r29,r3,r29 /* VA */
xor r28,r28,r0 /* hash */
/* Convert linux PTE bits into HW equivalents */
@@ -814,7 +837,7 @@ ht64_insert_pte:
/* Call ppc_md.hpte_insert */
ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
+ mr r4,r29 /* Retrieve vpn */
li r7,0 /* !bolted, !secondary */
li r8,MMU_PAGE_64K
ld r9,STK_PARM(r9)(r1) /* segment size */
@@ -837,7 +860,7 @@ _GLOBAL(ht64_call_hpte_insert1)
/* Call ppc_md.hpte_insert */
ld r6,STK_PARM(r4)(r1) /* Retrieve new pp bits */
- mr r4,r29 /* Retrieve va */
+ mr r4,r29 /* Retrieve vpn */
li r7,HPTE_V_SECONDARY /* !bolted, secondary */
li r8,MMU_PAGE_64K
ld r9,STK_PARM(r9)(r1) /* segment size */
@@ -907,7 +930,7 @@ ht64_modify_pte:
add r3,r0,r3 /* add slot idx */
/* Call ppc_md.hpte_updatepp */
- mr r5,r29 /* va */
+ mr r5,r29 /* vpn */
li r6,MMU_PAGE_64K
ld r7,STK_PARM(r9)(r1) /* segment size */
ld r8,STK_PARM(r8)(r1) /* get "local" param */
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 660b8bb..308e29d 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -39,22 +39,33 @@
DEFINE_RAW_SPINLOCK(native_tlbie_lock);
-static inline void __tlbie(unsigned long va, int psize, int ssize)
+static inline void __tlbie(unsigned long vpn, int psize, int ssize)
{
+ unsigned long va;
unsigned int penc;
+ /*
+ * We need 14 to 65 bits of va for a tlibe of 4K page
+ * With vpn we ignore the lower VPN_SHIFT bits already.
+ * And top two bits are already ignored because we can
+ * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
+ * of 12.
+ */
+ BUG_ON((77 - 65) > VPN_SHIFT);
+ va = vpn << VPN_SHIFT;
+
/* clear top 16 bits, non SLS segment */
va &= ~(0xffffULL << 48);
switch (psize) {
case MMU_PAGE_4K:
- va &= ~0xffful;
va |= ssize << 8;
asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
: "memory");
break;
default:
+ /* We need 14 to 14 + i bits of va */
penc = mmu_psize_defs[psize].penc;
va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
va |= penc << 12;
@@ -67,21 +78,25 @@ static inline void __tlbie(unsigned long va, int psize, int ssize)
}
}
-static inline void __tlbiel(unsigned long va, int psize, int ssize)
+static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
{
+ unsigned long va;
unsigned int penc;
+ BUG_ON((77 - 65) > VPN_SHIFT);
+ va = vpn << VPN_SHIFT;
+
/* clear top 16 bits, non SLS segment */
va &= ~(0xffffULL << 48);
switch (psize) {
case MMU_PAGE_4K:
- va &= ~0xffful;
va |= ssize << 8;
asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
: : "r"(va) : "memory");
break;
default:
+ /* We need 14 to 14 + i bits of va */
penc = mmu_psize_defs[psize].penc;
va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
va |= penc << 12;
@@ -234,7 +249,7 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
want_v = hpte_encode_v(va, psize, ssize);
- DBG_LOW(" update(va=%016lx, avpnv=%016lx, hash=%016lx, newpp=%x)",
+ DBG_LOW(" update(va=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
va, want_v & HPTE_V_AVPN, slot, newpp);
native_lock_hpte(hptep);
@@ -300,7 +315,7 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
struct hash_pte *hptep;
vsid = get_kernel_vsid(ea, ssize);
- va = hpt_va(ea, vsid, ssize);
+ va = hpt_vpn(ea, vsid, ssize);
slot = native_hpte_find(va, psize, ssize);
if (slot == -1)
@@ -325,7 +340,7 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
local_irq_save(flags);
- DBG_LOW(" invalidate(va=%016lx, hash: %x)\n", va, slot);
+ DBG_LOW(" invalidate(va=%016lx, hash: %lx)\n", va, slot);
want_v = hpte_encode_v(va, psize, ssize);
native_lock_hpte(hptep);
@@ -399,7 +414,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
vpi = (vsid ^ pteg) & htab_hash_mask;
seg_off |= vpi << shift;
}
- *va = vsid << SID_SHIFT | seg_off;
+ *va = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
case MMU_SEGSIZE_1T:
/* We only have 40 - 23 bits of seg_off in avpn */
seg_off = (avpn & 0x1ffff) << 23;
@@ -408,7 +423,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
seg_off |= vpi << shift;
}
- *va = vsid << SID_SHIFT_1T | seg_off;
+ *va = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
default:
*va = size = 0;
}
@@ -425,9 +440,10 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
*/
static void native_hpte_clear(void)
{
+ unsigned long va = 0;
unsigned long slot, slots, flags;
struct hash_pte *hptep = htab_address;
- unsigned long hpte_v, va;
+ unsigned long hpte_v;
unsigned long pteg_count;
int psize, ssize;
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 377e5cb..975c7d1 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -192,7 +192,7 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
vaddr += step, paddr += step) {
unsigned long hash, hpteg;
unsigned long vsid = get_kernel_vsid(vaddr, ssize);
- unsigned long va = hpt_va(vaddr, vsid, ssize);
+ unsigned long va = hpt_vpn(vaddr, vsid, ssize);
unsigned long tprot = prot;
/* Make kernel text executable */
@@ -1208,7 +1208,7 @@ static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
{
unsigned long hash, hpteg;
unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
- unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
+ unsigned long va = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
int ret;
@@ -1229,7 +1229,7 @@ static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
{
unsigned long hash, hidx, slot;
unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
- unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
+ unsigned long va = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
spin_lock(&linear_map_hash_lock);
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index cc5c273..1331403 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -25,7 +25,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
/* Search the Linux page table for a match with va */
- va = hpt_va(ea, vsid, ssize);
+ va = hpt_vpn(ea, vsid, ssize);
/* At this point, we have a pte (old_pte) which can be used to build
* or update an HPTE. There are 2 cases:
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 31f1820..321c585 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -86,7 +86,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
- vaddr = hpt_va(addr, vsid, ssize);
+ vaddr = hpt_vpn(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
/*
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index b83077e..c8c7bf6 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -259,7 +259,7 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
u64 dummy0, dummy1;
vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
- va = hpt_va(ea, vsid, MMU_SEGSIZE_256M);
+ va = hpt_vpn(ea, vsid, MMU_SEGSIZE_256M);
raw_spin_lock(&beat_htab_lock);
slot = beat_lpar_hpte_find(va, psize);
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 5f3ef87..2127529 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -227,22 +227,6 @@ static void pSeries_lpar_hptab_clear(void)
}
/*
- * This computes the AVPN and B fields of the first dword of a HPTE,
- * for use when we want to match an existing PTE. The bottom 7 bits
- * of the returned value are zero.
- */
-static inline unsigned long hpte_encode_avpn(unsigned long va, int psize,
- int ssize)
-{
- unsigned long v;
-
- v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
- v <<= HPTE_V_AVPN_SHIFT;
- v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
- return v;
-}
-
-/*
* NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
* the low 3 bits of flags happen to line up. So no transform is needed.
* We can probably optimize here and assume the high bits of newpp are
@@ -326,7 +310,7 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
unsigned long lpar_rc, slot, vsid, va, flags;
vsid = get_kernel_vsid(ea, ssize);
- va = hpt_va(ea, vsid, ssize);
+ va = hpt_vpn(ea, vsid, ssize);
slot = pSeries_lpar_hpte_find(va, psize, ssize);
BUG_ON(slot == -1);
@@ -361,7 +345,7 @@ static void pSeries_lpar_hpte_removebolted(unsigned long ea,
unsigned long slot, vsid, va;
vsid = get_kernel_vsid(ea, ssize);
- va = hpt_va(ea, vsid, ssize);
+ va = hpt_vpn(ea, vsid, ssize);
slot = pSeries_lpar_hpte_find(va, psize, ssize);
BUG_ON(slot == -1);
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 04/11] arch/powerpc: Rename va to vpn
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
` (2 preceding siblings ...)
2012-07-09 13:13 ` [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-22 23:46 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate Aneesh Kumar K.V
` (6 subsequent siblings)
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Rename the variable to better reflect the values. No functional change
in this patch.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/kvm_book3s.h | 2 +-
arch/powerpc/include/asm/machdep.h | 6 +--
arch/powerpc/include/asm/mmu-hash64.h | 23 ++++----
arch/powerpc/include/asm/tlbflush.h | 4 +-
arch/powerpc/kvm/book3s_64_mmu_host.c | 15 +++---
arch/powerpc/mm/hash_native_64.c | 88 ++++++++++++++++---------------
arch/powerpc/mm/hash_utils_64.c | 22 ++++----
arch/powerpc/mm/hugetlbpage-hash64.c | 15 +++---
arch/powerpc/mm/tlb_hash64.c | 11 ++--
arch/powerpc/platforms/cell/beat_htab.c | 45 ++++++++--------
arch/powerpc/platforms/ps3/htab.c | 22 ++++----
arch/powerpc/platforms/pseries/lpar.c | 60 +++++++++++----------
12 files changed, 161 insertions(+), 152 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index f0e0c6a..7aefdb3 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -59,7 +59,7 @@ struct hpte_cache {
struct hlist_node list_vpte;
struct hlist_node list_vpte_long;
struct rcu_head rcu_head;
- u64 host_va;
+ u64 host_vpn;
u64 pfn;
ulong slot;
struct kvmppc_pte pte;
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 42ce570..cd63f1a 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -34,19 +34,19 @@ struct machdep_calls {
char *name;
#ifdef CONFIG_PPC64
void (*hpte_invalidate)(unsigned long slot,
- unsigned long va,
+ unsigned long vpn,
int psize, int ssize,
int local);
long (*hpte_updatepp)(unsigned long slot,
unsigned long newpp,
- unsigned long va,
+ unsigned long vpn,
int psize, int ssize,
int local);
void (*hpte_updateboltedpp)(unsigned long newpp,
unsigned long ea,
int psize, int ssize);
long (*hpte_insert)(unsigned long hpte_group,
- unsigned long va,
+ unsigned long vpn,
unsigned long prpn,
unsigned long rflags,
unsigned long vflags,
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 1c984a6..a085de2 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -224,11 +224,11 @@ static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
* This function sets the AVPN and L fields of the HPTE appropriately
* for the page size
*/
-static inline unsigned long hpte_encode_v(unsigned long va, int psize,
- int ssize)
+static inline unsigned long hpte_encode_v(unsigned long vpn,
+ int psize, int ssize)
{
unsigned long v;
- v = hpte_encode_avpn(va, psize, ssize);
+ v = hpte_encode_avpn(vpn, psize, ssize);
if (psize != MMU_PAGE_4K)
v |= HPTE_V_LARGE;
return v;
@@ -257,8 +257,8 @@ static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
/*
* Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
*/
-static inline unsigned long hpt_vpn(unsigned long ea, unsigned long vsid,
- int ssize)
+static inline unsigned long hpt_vpn(unsigned long ea,
+ unsigned long vsid, int ssize)
{
unsigned long mask;
int s_shift = segment_shift(ssize);
@@ -270,9 +270,8 @@ static inline unsigned long hpt_vpn(unsigned long ea, unsigned long vsid,
/*
* This hashes a virtual address
*/
-
-static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
- int ssize)
+static inline unsigned long hpt_hash(unsigned long vpn,
+ unsigned int shift, int ssize)
{
int mask;
unsigned long hash, vsid;
@@ -281,13 +280,13 @@ static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
if (ssize == MMU_SEGSIZE_256M) {
mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
- hash = ((va >> (SID_SHIFT - VPN_SHIFT)) & 0x0000007fffffffff) ^
- (((va & mask) >> (shift - VPN_SHIFT)) & 0xffff);
+ hash = ((vpn >> (SID_SHIFT - VPN_SHIFT)) & 0x0000007fffffffff) ^
+ (((vpn & mask) >> (shift - VPN_SHIFT)) & 0xffff);
} else {
mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
- vsid = va >> (SID_SHIFT_1T - VPN_SHIFT);
+ vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
hash = (vsid & 0xffffff) ^ ((vsid << 25) & 0x7fffffffff) ^
- (((va & mask) >> (shift - VPN_SHIFT)) & 0xfffffff);
+ (((vpn & mask) >> (shift - VPN_SHIFT)) & 0xfffffff);
}
return hash & 0x7fffffffffUL;
}
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index 81143fc..fc02d1d 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -95,7 +95,7 @@ struct ppc64_tlb_batch {
unsigned long index;
struct mm_struct *mm;
real_pte_t pte[PPC64_TLB_BATCH_NR];
- unsigned long vaddr[PPC64_TLB_BATCH_NR];
+ unsigned long vpn[PPC64_TLB_BATCH_NR];
unsigned int psize;
int ssize;
};
@@ -127,7 +127,7 @@ static inline void arch_leave_lazy_mmu_mode(void)
#define arch_flush_lazy_mmu_mode() do {} while (0)
-extern void flush_hash_page(unsigned long va, real_pte_t pte, int psize,
+extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
int ssize, int local);
extern void flush_hash_range(unsigned long number, int local);
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index 9d184f1..f910e24 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -80,8 +80,9 @@ static struct kvmppc_sid_map *find_sid_vsid(struct kvm_vcpu *vcpu, u64 gvsid)
int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
{
+ unsigned long vpn;
pfn_t hpaddr;
- ulong hash, hpteg, va;
+ ulong hash, hpteg;
u64 vsid;
int ret;
int rflags = 0x192;
@@ -117,7 +118,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
}
vsid = map->host_vsid;
- va = hpt_vpn(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
+ vpn = hpt_vpn(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
if (!orig_pte->may_write)
rflags |= HPTE_R_PP;
@@ -127,7 +128,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
if (!orig_pte->may_execute)
rflags |= HPTE_R_N;
- hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M);
+ hash = hpt_hash(vpn, PTE_SIZE, MMU_SEGSIZE_256M);
map_again:
hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
@@ -139,7 +140,8 @@ map_again:
goto out;
}
- ret = ppc_md.hpte_insert(hpteg, va, hpaddr, rflags, vflags, MMU_PAGE_4K, MMU_SEGSIZE_256M);
+ ret = ppc_md.hpte_insert(hpteg, vpn, hpaddr, rflags, vflags,
+ MMU_PAGE_4K, MMU_SEGSIZE_256M);
if (ret < 0) {
/* If we couldn't map a primary PTE, try a secondary */
@@ -150,7 +152,8 @@ map_again:
} else {
struct hpte_cache *pte = kvmppc_mmu_hpte_cache_next(vcpu);
- trace_kvm_book3s_64_mmu_map(rflags, hpteg, va, hpaddr, orig_pte);
+ trace_kvm_book3s_64_mmu_map(rflags, hpteg,
+ vpn, hpaddr, orig_pte);
/* The ppc_md code may give us a secondary entry even though we
asked for a primary. Fix up. */
@@ -160,7 +163,7 @@ map_again:
}
pte->slot = hpteg + (ret & 7);
- pte->host_va = va;
+ pte->host_vpn = vpn;
pte->pte = *orig_pte;
pte->pfn = hpaddr >> PAGE_SHIFT;
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 308e29d..b019f2d 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -109,7 +109,7 @@ static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
}
-static inline void tlbie(unsigned long va, int psize, int ssize, int local)
+static inline void tlbie(unsigned long vpn, int psize, int ssize, int local)
{
unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
@@ -120,10 +120,10 @@ static inline void tlbie(unsigned long va, int psize, int ssize, int local)
raw_spin_lock(&native_tlbie_lock);
asm volatile("ptesync": : :"memory");
if (use_local) {
- __tlbiel(va, psize, ssize);
+ __tlbiel(vpn, psize, ssize);
asm volatile("ptesync": : :"memory");
} else {
- __tlbie(va, psize, ssize);
+ __tlbie(vpn, psize, ssize);
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
if (lock_tlbie && !use_local)
@@ -149,7 +149,7 @@ static inline void native_unlock_hpte(struct hash_pte *hptep)
clear_bit_unlock(HPTE_LOCK_BIT, word);
}
-static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
+static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
unsigned long pa, unsigned long rflags,
unsigned long vflags, int psize, int ssize)
{
@@ -158,9 +158,9 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
int i;
if (!(vflags & HPTE_V_BOLTED)) {
- DBG_LOW(" insert(group=%lx, va=%016lx, pa=%016lx,"
+ DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
" rflags=%lx, vflags=%lx, psize=%d)\n",
- hpte_group, va, pa, rflags, vflags, psize);
+ hpte_group, vpn, pa, rflags, vflags, psize);
}
for (i = 0; i < HPTES_PER_GROUP; i++) {
@@ -178,7 +178,7 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
if (i == HPTES_PER_GROUP)
return -1;
- hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
+ hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
hpte_r = hpte_encode_r(pa, psize) | rflags;
if (!(vflags & HPTE_V_BOLTED)) {
@@ -240,17 +240,17 @@ static long native_hpte_remove(unsigned long hpte_group)
}
static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
- unsigned long va, int psize, int ssize,
+ unsigned long vpn, int psize, int ssize,
int local)
{
struct hash_pte *hptep = htab_address + slot;
unsigned long hpte_v, want_v;
int ret = 0;
- want_v = hpte_encode_v(va, psize, ssize);
+ want_v = hpte_encode_v(vpn, psize, ssize);
- DBG_LOW(" update(va=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
- va, want_v & HPTE_V_AVPN, slot, newpp);
+ DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
+ vpn, want_v & HPTE_V_AVPN, slot, newpp);
native_lock_hpte(hptep);
@@ -269,12 +269,12 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
native_unlock_hpte(hptep);
/* Ensure it is out of the tlb too. */
- tlbie(va, psize, ssize, local);
+ tlbie(vpn, psize, ssize, local);
return ret;
}
-static long native_hpte_find(unsigned long va, int psize, int ssize)
+static long native_hpte_find(unsigned long vpn, int psize, int ssize)
{
struct hash_pte *hptep;
unsigned long hash;
@@ -282,8 +282,8 @@ static long native_hpte_find(unsigned long va, int psize, int ssize)
long slot;
unsigned long want_v, hpte_v;
- hash = hpt_hash(va, mmu_psize_defs[psize].shift, ssize);
- want_v = hpte_encode_v(va, psize, ssize);
+ hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
+ want_v = hpte_encode_v(vpn, psize, ssize);
/* Bolted mappings are only ever in the primary group */
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
@@ -310,14 +310,15 @@ static long native_hpte_find(unsigned long va, int psize, int ssize)
static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
int psize, int ssize)
{
- unsigned long vsid, va;
+ unsigned long vpn;
+ unsigned long vsid;
long slot;
struct hash_pte *hptep;
vsid = get_kernel_vsid(ea, ssize);
- va = hpt_vpn(ea, vsid, ssize);
+ vpn = hpt_vpn(ea, vsid, ssize);
- slot = native_hpte_find(va, psize, ssize);
+ slot = native_hpte_find(vpn, psize, ssize);
if (slot == -1)
panic("could not find page to bolt\n");
hptep = htab_address + slot;
@@ -327,10 +328,10 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
(newpp & (HPTE_R_PP | HPTE_R_N));
/* Ensure it is out of the tlb too. */
- tlbie(va, psize, ssize, 0);
+ tlbie(vpn, psize, ssize, 0);
}
-static void native_hpte_invalidate(unsigned long slot, unsigned long va,
+static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
int psize, int ssize, int local)
{
struct hash_pte *hptep = htab_address + slot;
@@ -340,9 +341,9 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
local_irq_save(flags);
- DBG_LOW(" invalidate(va=%016lx, hash: %lx)\n", va, slot);
+ DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
- want_v = hpte_encode_v(va, psize, ssize);
+ want_v = hpte_encode_v(vpn, psize, ssize);
native_lock_hpte(hptep);
hpte_v = hptep->v;
@@ -354,7 +355,7 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
hptep->v = 0;
/* Invalidate the TLB */
- tlbie(va, psize, ssize, local);
+ tlbie(vpn, psize, ssize, local);
local_irq_restore(flags);
}
@@ -364,7 +365,7 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
- int *psize, int *ssize, unsigned long *va)
+ int *psize, int *ssize, unsigned long *vpn)
{
unsigned long avpn, pteg, vpi;
unsigned long hpte_r = hpte->r;
@@ -414,7 +415,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
vpi = (vsid ^ pteg) & htab_hash_mask;
seg_off |= vpi << shift;
}
- *va = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
+ *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
case MMU_SEGSIZE_1T:
/* We only have 40 - 23 bits of seg_off in avpn */
seg_off = (avpn & 0x1ffff) << 23;
@@ -423,9 +424,9 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
seg_off |= vpi << shift;
}
- *va = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
+ *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
default:
- *va = size = 0;
+ *vpn = size = 0;
}
*psize = size;
}
@@ -440,7 +441,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
*/
static void native_hpte_clear(void)
{
- unsigned long va = 0;
+ unsigned long vpn = 0;
unsigned long slot, slots, flags;
struct hash_pte *hptep = htab_address;
unsigned long hpte_v;
@@ -471,9 +472,9 @@ static void native_hpte_clear(void)
* already hold the native_tlbie_lock.
*/
if (hpte_v & HPTE_V_VALID) {
- hpte_decode(hptep, slot, &psize, &ssize, &va);
+ hpte_decode(hptep, slot, &psize, &ssize, &vpn);
hptep->v = 0;
- __tlbie(va, psize, ssize);
+ __tlbie(vpn, psize, ssize);
}
}
@@ -488,7 +489,8 @@ static void native_hpte_clear(void)
*/
static void native_flush_hash_range(unsigned long number, int local)
{
- unsigned long va, hash, index, hidx, shift, slot;
+ unsigned long vpn;
+ unsigned long hash, index, hidx, shift, slot;
struct hash_pte *hptep;
unsigned long hpte_v;
unsigned long want_v;
@@ -502,18 +504,18 @@ static void native_flush_hash_range(unsigned long number, int local)
local_irq_save(flags);
for (i = 0; i < number; i++) {
- va = batch->vaddr[i];
+ vpn = batch->vpn[i];
pte = batch->pte[i];
- pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
- hash = hpt_hash(va, shift, ssize);
+ pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
+ hash = hpt_hash(vpn, shift, ssize);
hidx = __rpte_to_hidx(pte, index);
if (hidx & _PTEIDX_SECONDARY)
hash = ~hash;
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
slot += hidx & _PTEIDX_GROUP_IX;
hptep = htab_address + slot;
- want_v = hpte_encode_v(va, psize, ssize);
+ want_v = hpte_encode_v(vpn, psize, ssize);
native_lock_hpte(hptep);
hpte_v = hptep->v;
if (!HPTE_V_COMPARE(hpte_v, want_v) ||
@@ -528,12 +530,12 @@ static void native_flush_hash_range(unsigned long number, int local)
mmu_psize_defs[psize].tlbiel && local) {
asm volatile("ptesync":::"memory");
for (i = 0; i < number; i++) {
- va = batch->vaddr[i];
+ vpn = batch->vpn[i];
pte = batch->pte[i];
- pte_iterate_hashed_subpages(pte, psize, va, index,
- shift) {
- __tlbiel(va, psize, ssize);
+ pte_iterate_hashed_subpages(pte, psize,
+ vpn, index, shift) {
+ __tlbiel(vpn, psize, ssize);
} pte_iterate_hashed_end();
}
asm volatile("ptesync":::"memory");
@@ -545,12 +547,12 @@ static void native_flush_hash_range(unsigned long number, int local)
asm volatile("ptesync":::"memory");
for (i = 0; i < number; i++) {
- va = batch->vaddr[i];
+ vpn = batch->vpn[i];
pte = batch->pte[i];
- pte_iterate_hashed_subpages(pte, psize, va, index,
- shift) {
- __tlbie(va, psize, ssize);
+ pte_iterate_hashed_subpages(pte, psize,
+ vpn, index, shift) {
+ __tlbie(vpn, psize, ssize);
} pte_iterate_hashed_end();
}
asm volatile("eieio; tlbsync; ptesync":::"memory");
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 975c7d1..0d8c4b8 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -192,18 +192,18 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
vaddr += step, paddr += step) {
unsigned long hash, hpteg;
unsigned long vsid = get_kernel_vsid(vaddr, ssize);
- unsigned long va = hpt_vpn(vaddr, vsid, ssize);
+ unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
unsigned long tprot = prot;
/* Make kernel text executable */
if (overlaps_kernel_text(vaddr, vaddr + step))
tprot &= ~HPTE_R_N;
- hash = hpt_hash(va, shift, ssize);
+ hash = hpt_hash(vpn, shift, ssize);
hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
BUG_ON(!ppc_md.hpte_insert);
- ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
+ ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
HPTE_V_BOLTED, psize, ssize);
if (ret < 0)
@@ -1153,21 +1153,21 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
/* WARNING: This is called from hash_low_64.S, if you change this prototype,
* do not forget to update the assembly call site !
*/
-void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
+void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
int local)
{
unsigned long hash, index, shift, hidx, slot;
- DBG_LOW("flush_hash_page(va=%016lx)\n", va);
- pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
- hash = hpt_hash(va, shift, ssize);
+ DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
+ pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
+ hash = hpt_hash(vpn, shift, ssize);
hidx = __rpte_to_hidx(pte, index);
if (hidx & _PTEIDX_SECONDARY)
hash = ~hash;
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
slot += hidx & _PTEIDX_GROUP_IX;
DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
- ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
+ ppc_md.hpte_invalidate(slot, vpn, psize, ssize, local);
} pte_iterate_hashed_end();
}
@@ -1181,7 +1181,7 @@ void flush_hash_range(unsigned long number, int local)
&__get_cpu_var(ppc64_tlb_batch);
for (i = 0; i < number; i++)
- flush_hash_page(batch->vaddr[i], batch->pte[i],
+ flush_hash_page(batch->vpn[i], batch->pte[i],
batch->psize, batch->ssize, local);
}
}
@@ -1208,7 +1208,7 @@ static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
{
unsigned long hash, hpteg;
unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
- unsigned long va = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
+ unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
int ret;
@@ -1229,7 +1229,7 @@ static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
{
unsigned long hash, hidx, slot;
unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
- unsigned long va = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
+ unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
spin_lock(&linear_map_hash_lock);
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index 1331403..cecad34 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -18,14 +18,15 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
pte_t *ptep, unsigned long trap, int local, int ssize,
unsigned int shift, unsigned int mmu_psize)
{
+ unsigned long vpn;
unsigned long old_pte, new_pte;
- unsigned long va, rflags, pa, sz;
+ unsigned long rflags, pa, sz;
long slot;
BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
/* Search the Linux page table for a match with va */
- va = hpt_vpn(ea, vsid, ssize);
+ vpn = hpt_vpn(ea, vsid, ssize);
/* At this point, we have a pte (old_pte) which can be used to build
* or update an HPTE. There are 2 cases:
@@ -69,19 +70,19 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
/* There MIGHT be an HPTE for this pte */
unsigned long hash, slot;
- hash = hpt_hash(va, shift, ssize);
+ hash = hpt_hash(vpn, shift, ssize);
if (old_pte & _PAGE_F_SECOND)
hash = ~hash;
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
slot += (old_pte & _PAGE_F_GIX) >> 12;
- if (ppc_md.hpte_updatepp(slot, rflags, va, mmu_psize,
+ if (ppc_md.hpte_updatepp(slot, rflags, vpn, mmu_psize,
ssize, local) == -1)
old_pte &= ~_PAGE_HPTEFLAGS;
}
if (likely(!(old_pte & _PAGE_HASHPTE))) {
- unsigned long hash = hpt_hash(va, shift, ssize);
+ unsigned long hash = hpt_hash(vpn, shift, ssize);
unsigned long hpte_group;
pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
@@ -101,14 +102,14 @@ repeat:
_PAGE_COHERENT | _PAGE_GUARDED));
/* Insert into the hash table, primary slot */
- slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags, 0,
+ slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
mmu_psize, ssize);
/* Primary is full, try the secondary */
if (unlikely(slot == -1)) {
hpte_group = ((~hash & htab_hash_mask) *
HPTES_PER_GROUP) & ~0x7UL;
- slot = ppc_md.hpte_insert(hpte_group, va, pa, rflags,
+ slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
HPTE_V_SECONDARY,
mmu_psize, ssize);
if (slot == -1) {
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 321c585..ae758b3 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -42,8 +42,9 @@ DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
+ unsigned long vpn;
struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
- unsigned long vsid, vaddr;
+ unsigned long vsid;
unsigned int psize;
int ssize;
real_pte_t rpte;
@@ -86,7 +87,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
- vaddr = hpt_vpn(addr, vsid, ssize);
+ vpn = hpt_vpn(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
/*
@@ -96,7 +97,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
* and decide to use local invalidates instead...
*/
if (!batch->active) {
- flush_hash_page(vaddr, rpte, psize, ssize, 0);
+ flush_hash_page(vpn, rpte, psize, ssize, 0);
put_cpu_var(ppc64_tlb_batch);
return;
}
@@ -122,7 +123,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
batch->ssize = ssize;
}
batch->pte[i] = rpte;
- batch->vaddr[i] = vaddr;
+ batch->vpn[i] = vpn;
batch->index = ++i;
if (i >= PPC64_TLB_BATCH_NR)
__flush_tlb_pending(batch);
@@ -146,7 +147,7 @@ void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
if (cpumask_equal(mm_cpumask(batch->mm), tmp))
local = 1;
if (i == 1)
- flush_hash_page(batch->vaddr[0], batch->pte[0],
+ flush_hash_page(batch->vpn[0], batch->pte[0],
batch->psize, batch->ssize, local);
else
flush_hash_range(i, local);
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index c8c7bf6..0f6f839 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -88,7 +88,7 @@ static inline unsigned int beat_read_mask(unsigned hpte_group)
}
static long beat_lpar_hpte_insert(unsigned long hpte_group,
- unsigned long va, unsigned long pa,
+ unsigned long vpn, unsigned long pa,
unsigned long rflags, unsigned long vflags,
int psize, int ssize)
{
@@ -103,7 +103,7 @@ static long beat_lpar_hpte_insert(unsigned long hpte_group,
"rflags=%lx, vflags=%lx, psize=%d)\n",
hpte_group, va, pa, rflags, vflags, psize);
- hpte_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M) |
+ hpte_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M) |
vflags | HPTE_V_VALID;
hpte_r = hpte_encode_r(pa, psize) | rflags;
@@ -184,14 +184,14 @@ static void beat_lpar_hptab_clear(void)
*/
static long beat_lpar_hpte_updatepp(unsigned long slot,
unsigned long newpp,
- unsigned long va,
+ unsigned long vpn,
int psize, int ssize, int local)
{
unsigned long lpar_rc;
u64 dummy0, dummy1;
unsigned long want_v;
- want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+ want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
DBG_LOW(" update: "
"avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
@@ -220,15 +220,15 @@ static long beat_lpar_hpte_updatepp(unsigned long slot,
return 0;
}
-static long beat_lpar_hpte_find(unsigned long va, int psize)
+static long beat_lpar_hpte_find(unsigned long vpn, int psize)
{
unsigned long hash;
unsigned long i, j;
long slot;
unsigned long want_v, hpte_v;
- hash = hpt_hash(va, mmu_psize_defs[psize].shift, MMU_SEGSIZE_256M);
- want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+ hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, MMU_SEGSIZE_256M);
+ want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
for (j = 0; j < 2; j++) {
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
@@ -255,14 +255,15 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
unsigned long ea,
int psize, int ssize)
{
- unsigned long lpar_rc, slot, vsid, va;
+ unsigned long vpn;
+ unsigned long lpar_rc, slot, vsid;
u64 dummy0, dummy1;
vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
- va = hpt_vpn(ea, vsid, MMU_SEGSIZE_256M);
+ vpn = hpt_vpn(ea, vsid, MMU_SEGSIZE_256M);
raw_spin_lock(&beat_htab_lock);
- slot = beat_lpar_hpte_find(va, psize);
+ slot = beat_lpar_hpte_find(vpn, psize);
BUG_ON(slot == -1);
lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7,
@@ -272,7 +273,7 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
BUG_ON(lpar_rc != 0);
}
-static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
+static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
int psize, int ssize, int local)
{
unsigned long want_v;
@@ -282,7 +283,7 @@ static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
DBG_LOW(" inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
slot, va, psize, local);
- want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+ want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
raw_spin_lock_irqsave(&beat_htab_lock, flags);
dummy1 = beat_lpar_hpte_getword0(slot);
@@ -311,7 +312,7 @@ void __init hpte_init_beat(void)
}
static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
- unsigned long va, unsigned long pa,
+ unsigned long vpn, unsigned long pa,
unsigned long rflags, unsigned long vflags,
int psize, int ssize)
{
@@ -322,11 +323,11 @@ static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
return -1;
if (!(vflags & HPTE_V_BOLTED))
- DBG_LOW("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
+ DBG_LOW("hpte_insert(group=%lx, vpn=%016lx, pa=%016lx, "
"rflags=%lx, vflags=%lx, psize=%d)\n",
- hpte_group, va, pa, rflags, vflags, psize);
+ hpte_group, vpn, pa, rflags, vflags, psize);
- hpte_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M) |
+ hpte_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M) |
vflags | HPTE_V_VALID;
hpte_r = hpte_encode_r(pa, psize) | rflags;
@@ -364,14 +365,14 @@ static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
*/
static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
unsigned long newpp,
- unsigned long va,
+ unsigned long vpn,
int psize, int ssize, int local)
{
unsigned long lpar_rc;
unsigned long want_v;
unsigned long pss;
- want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+ want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc;
DBG_LOW(" update: "
@@ -392,16 +393,16 @@ static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
return 0;
}
-static void beat_lpar_hpte_invalidate_v3(unsigned long slot, unsigned long va,
+static void beat_lpar_hpte_invalidate_v3(unsigned long slot, unsigned long vpn,
int psize, int ssize, int local)
{
unsigned long want_v;
unsigned long lpar_rc;
unsigned long pss;
- DBG_LOW(" inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
- slot, va, psize, local);
- want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
+ DBG_LOW(" inval : slot=%lx, vpn=%016lx, psize: %d, local: %d\n",
+ slot, vpn, psize, local);
+ want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc;
lpar_rc = beat_invalidate_htab_entry3(0, slot, want_v, pss);
diff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c
index 3124cf7..d00d7b0 100644
--- a/arch/powerpc/platforms/ps3/htab.c
+++ b/arch/powerpc/platforms/ps3/htab.c
@@ -43,7 +43,7 @@ enum ps3_lpar_vas_id {
static DEFINE_SPINLOCK(ps3_htab_lock);
-static long ps3_hpte_insert(unsigned long hpte_group, unsigned long va,
+static long ps3_hpte_insert(unsigned long hpte_group, unsigned long vpn,
unsigned long pa, unsigned long rflags, unsigned long vflags,
int psize, int ssize)
{
@@ -61,7 +61,7 @@ static long ps3_hpte_insert(unsigned long hpte_group, unsigned long va,
*/
vflags &= ~HPTE_V_SECONDARY;
- hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
+ hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
hpte_r = hpte_encode_r(ps3_mm_phys_to_lpar(pa), psize) | rflags;
spin_lock_irqsave(&ps3_htab_lock, flags);
@@ -75,8 +75,8 @@ static long ps3_hpte_insert(unsigned long hpte_group, unsigned long va,
if (result) {
/* all entries bolted !*/
- pr_info("%s:result=%d va=%lx pa=%lx ix=%lx v=%llx r=%llx\n",
- __func__, result, va, pa, hpte_group, hpte_v, hpte_r);
+ pr_info("%s:result=%d vpn=%lx pa=%lx ix=%lx v=%llx r=%llx\n",
+ __func__, result, vpn, pa, hpte_group, hpte_v, hpte_r);
BUG();
}
@@ -107,7 +107,7 @@ static long ps3_hpte_remove(unsigned long hpte_group)
}
static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
- unsigned long va, int psize, int ssize, int local)
+ unsigned long vpn, int psize, int ssize, int local)
{
int result;
u64 hpte_v, want_v, hpte_rs;
@@ -115,7 +115,7 @@ static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
unsigned long flags;
long ret;
- want_v = hpte_encode_v(va, psize, ssize);
+ want_v = hpte_encode_v(vpn, psize, ssize);
spin_lock_irqsave(&ps3_htab_lock, flags);
@@ -125,8 +125,8 @@ static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
&hpte_rs);
if (result) {
- pr_info("%s: res=%d read va=%lx slot=%lx psize=%d\n",
- __func__, result, va, slot, psize);
+ pr_info("%s: res=%d read vpn=%lx slot=%lx psize=%d\n",
+ __func__, result, vpn, slot, psize);
BUG();
}
@@ -159,7 +159,7 @@ static void ps3_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
panic("ps3_hpte_updateboltedpp() not implemented");
}
-static void ps3_hpte_invalidate(unsigned long slot, unsigned long va,
+static void ps3_hpte_invalidate(unsigned long slot, unsigned long vpn,
int psize, int ssize, int local)
{
unsigned long flags;
@@ -170,8 +170,8 @@ static void ps3_hpte_invalidate(unsigned long slot, unsigned long va,
result = lv1_write_htab_entry(PS3_LPAR_VAS_ID_CURRENT, slot, 0, 0);
if (result) {
- pr_info("%s: res=%d va=%lx slot=%lx psize=%d\n",
- __func__, result, va, slot, psize);
+ pr_info("%s: res=%d vpn=%lx slot=%lx psize=%d\n",
+ __func__, result, vpn, slot, psize);
BUG();
}
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 2127529..8308b25 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -108,9 +108,9 @@ void vpa_init(int cpu)
}
static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
- unsigned long va, unsigned long pa,
- unsigned long rflags, unsigned long vflags,
- int psize, int ssize)
+ unsigned long vpn, unsigned long pa,
+ unsigned long rflags, unsigned long vflags,
+ int psize, int ssize)
{
unsigned long lpar_rc;
unsigned long flags;
@@ -118,11 +118,11 @@ static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
unsigned long hpte_v, hpte_r;
if (!(vflags & HPTE_V_BOLTED))
- pr_devel("hpte_insert(group=%lx, va=%016lx, pa=%016lx, "
- "rflags=%lx, vflags=%lx, psize=%d)\n",
- hpte_group, va, pa, rflags, vflags, psize);
+ pr_devel("hpte_insert(group=%lx, vpn=%016lx, "
+ "pa=%016lx, rflags=%lx, vflags=%lx, psize=%d)\n",
+ hpte_group, vpn, pa, rflags, vflags, psize);
- hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
+ hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
hpte_r = hpte_encode_r(pa, psize) | rflags;
if (!(vflags & HPTE_V_BOLTED))
@@ -234,14 +234,14 @@ static void pSeries_lpar_hptab_clear(void)
*/
static long pSeries_lpar_hpte_updatepp(unsigned long slot,
unsigned long newpp,
- unsigned long va,
+ unsigned long vpn,
int psize, int ssize, int local)
{
unsigned long lpar_rc;
unsigned long flags = (newpp & 7) | H_AVPN;
unsigned long want_v;
- want_v = hpte_encode_avpn(va, psize, ssize);
+ want_v = hpte_encode_avpn(vpn, psize, ssize);
pr_devel(" update: avpnv=%016lx, hash=%016lx, f=%lx, psize: %d ...",
want_v, slot, flags, psize);
@@ -279,15 +279,15 @@ static unsigned long pSeries_lpar_hpte_getword0(unsigned long slot)
return dword0;
}
-static long pSeries_lpar_hpte_find(unsigned long va, int psize, int ssize)
+static long pSeries_lpar_hpte_find(unsigned long vpn, int psize, int ssize)
{
unsigned long hash;
unsigned long i;
long slot;
unsigned long want_v, hpte_v;
- hash = hpt_hash(va, mmu_psize_defs[psize].shift, ssize);
- want_v = hpte_encode_avpn(va, psize, ssize);
+ hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
+ want_v = hpte_encode_avpn(vpn, psize, ssize);
/* Bolted entries are always in the primary group */
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
@@ -307,12 +307,13 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
unsigned long ea,
int psize, int ssize)
{
- unsigned long lpar_rc, slot, vsid, va, flags;
+ unsigned long vpn;
+ unsigned long lpar_rc, slot, vsid, flags;
vsid = get_kernel_vsid(ea, ssize);
- va = hpt_vpn(ea, vsid, ssize);
+ vpn = hpt_vpn(ea, vsid, ssize);
- slot = pSeries_lpar_hpte_find(va, psize, ssize);
+ slot = pSeries_lpar_hpte_find(vpn, psize, ssize);
BUG_ON(slot == -1);
flags = newpp & 7;
@@ -321,17 +322,17 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
BUG_ON(lpar_rc != H_SUCCESS);
}
-static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
+static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
int psize, int ssize, int local)
{
unsigned long want_v;
unsigned long lpar_rc;
unsigned long dummy1, dummy2;
- pr_devel(" inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
- slot, va, psize, local);
+ pr_devel(" inval : slot=%lx, vpn=%016lx, psize: %d, local: %d\n",
+ slot, vpn, psize, local);
- want_v = hpte_encode_avpn(va, psize, ssize);
+ want_v = hpte_encode_avpn(vpn, psize, ssize);
lpar_rc = plpar_pte_remove(H_AVPN, slot, want_v, &dummy1, &dummy2);
if (lpar_rc == H_NOT_FOUND)
return;
@@ -342,15 +343,16 @@ static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
static void pSeries_lpar_hpte_removebolted(unsigned long ea,
int psize, int ssize)
{
- unsigned long slot, vsid, va;
+ unsigned long vpn;
+ unsigned long slot, vsid;
vsid = get_kernel_vsid(ea, ssize);
- va = hpt_vpn(ea, vsid, ssize);
+ vpn = hpt_vpn(ea, vsid, ssize);
- slot = pSeries_lpar_hpte_find(va, psize, ssize);
+ slot = pSeries_lpar_hpte_find(vpn, psize, ssize);
BUG_ON(slot == -1);
- pSeries_lpar_hpte_invalidate(slot, va, psize, ssize, 0);
+ pSeries_lpar_hpte_invalidate(slot, vpn, psize, ssize, 0);
}
/* Flag bits for H_BULK_REMOVE */
@@ -366,12 +368,12 @@ static void pSeries_lpar_hpte_removebolted(unsigned long ea,
*/
static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
{
+ unsigned long vpn;
unsigned long i, pix, rc;
unsigned long flags = 0;
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
unsigned long param[9];
- unsigned long va;
unsigned long hash, index, shift, hidx, slot;
real_pte_t pte;
int psize, ssize;
@@ -383,21 +385,21 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
ssize = batch->ssize;
pix = 0;
for (i = 0; i < number; i++) {
- va = batch->vaddr[i];
+ vpn = batch->vpn[i];
pte = batch->pte[i];
- pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
- hash = hpt_hash(va, shift, ssize);
+ pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
+ hash = hpt_hash(vpn, shift, ssize);
hidx = __rpte_to_hidx(pte, index);
if (hidx & _PTEIDX_SECONDARY)
hash = ~hash;
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
slot += hidx & _PTEIDX_GROUP_IX;
if (!firmware_has_feature(FW_FEATURE_BULK_REMOVE)) {
- pSeries_lpar_hpte_invalidate(slot, va, psize,
+ pSeries_lpar_hpte_invalidate(slot, vpn, psize,
ssize, local);
} else {
param[pix] = HBR_REQUEST | HBR_AVPN | slot;
- param[pix+1] = hpte_encode_avpn(va, psize,
+ param[pix+1] = hpte_encode_avpn(vpn, psize,
ssize);
pix += 2;
if (pix == 8) {
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
` (3 preceding siblings ...)
2012-07-09 13:13 ` [PATCH -V3 04/11] arch/powerpc: Rename va " Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-22 23:56 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 06/11] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE Aneesh Kumar K.V
` (5 subsequent siblings)
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
ISA doc doesn't talk about this. As per ISA doc for a 4K page
tlbie RB RS
" The Abbreviated Virtual Address (AVA) field in register RB must
contain bits 14:65 of the virtual address translated by the TLB
entry to be invalidated."
That indicate we should not mask the top 16 bits. So remove the same.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_native_64.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index b019f2d..9bf8187 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -54,9 +54,6 @@ static inline void __tlbie(unsigned long vpn, int psize, int ssize)
BUG_ON((77 - 65) > VPN_SHIFT);
va = vpn << VPN_SHIFT;
- /* clear top 16 bits, non SLS segment */
- va &= ~(0xffffULL << 48);
-
switch (psize) {
case MMU_PAGE_4K:
va |= ssize << 8;
@@ -86,9 +83,6 @@ static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
BUG_ON((77 - 65) > VPN_SHIFT);
va = vpn << VPN_SHIFT;
- /* clear top 16 bits, non SLS segment */
- va &= ~(0xffffULL << 48);
-
switch (psize) {
case MMU_PAGE_4K:
va |= ssize << 8;
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 06/11] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
` (4 preceding siblings ...)
2012-07-09 13:13 ` [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-22 23:57 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 07/11] arch/powerpc: Increase the slice range to 64TB Aneesh Kumar K.V
` (4 subsequent siblings)
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
As we keep increasing PGTABLE_RANGE we need not increase the virual
map area for kernel.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/pgtable-ppc64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index c420561..8af1cf2 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -41,7 +41,7 @@
#else
#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
#endif
-#define KERN_VIRT_SIZE PGTABLE_RANGE
+#define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000)
/*
* The vmalloc space starts at the beginning of that region, and
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 07/11] arch/powerpc: Increase the slice range to 64TB
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
` (5 preceding siblings ...)
2012-07-09 13:13 ` [PATCH -V3 06/11] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-23 0:00 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 08/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit Aneesh Kumar K.V
` (3 subsequent siblings)
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This patch makes the high psizes mask as an unsigned char array
so that we can have more than 16TB. Currently we support upto
64TB
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 6 ++-
arch/powerpc/include/asm/page_64.h | 6 ++-
arch/powerpc/mm/hash_utils_64.c | 15 +++---
arch/powerpc/mm/slb_low.S | 35 ++++++++----
arch/powerpc/mm/slice.c | 95 +++++++++++++++++++++------------
5 files changed, 107 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index a085de2..35b74e8 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -463,7 +463,11 @@ typedef struct {
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
- u64 high_slices_psize; /* 4 bits per slice for now */
+ /*
+ * Right now we support 64TB and 4 bits for each
+ * 1TB slice we need 32 bytes for 64TB.
+ */
+ unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
#else
u16 sllp; /* SLB page size encoding */
#endif
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fed85e6..6c9bef4 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -82,7 +82,11 @@ extern u64 ppc64_pft_size;
struct slice_mask {
u16 low_slices;
- u16 high_slices;
+ /*
+ * This should be derived out of PGTABLE_RANGE. For the current
+ * max 64TB, u64 should be ok.
+ */
+ u64 high_slices;
};
struct mm_struct;
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 0d8c4b8..eb4a3ac 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -804,16 +804,19 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
#ifdef CONFIG_PPC_MM_SLICES
unsigned int get_paca_psize(unsigned long addr)
{
- unsigned long index, slices;
+ u64 lpsizes;
+ unsigned char *hpsizes;
+ unsigned long index, mask_index;
if (addr < SLICE_LOW_TOP) {
- slices = get_paca()->context.low_slices_psize;
+ lpsizes = get_paca()->context.low_slices_psize;
index = GET_LOW_SLICE_INDEX(addr);
- } else {
- slices = get_paca()->context.high_slices_psize;
- index = GET_HIGH_SLICE_INDEX(addr);
+ return (lpsizes >> (index * 4)) & 0xF;
}
- return (slices >> (index * 4)) & 0xF;
+ hpsizes = get_paca()->context.high_slices_psize;
+ index = GET_HIGH_SLICE_INDEX(addr) >> 1;
+ mask_index = GET_HIGH_SLICE_INDEX(addr) - (index << 1);
+ return (hpsizes[index] >> (mask_index * 4)) & 0xF;
}
#else
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index b9ee79ce..c355af6 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -108,17 +108,34 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
* between 4k and 64k standard page size
*/
#ifdef CONFIG_PPC_MM_SLICES
+ /* r10 have esid */
cmpldi r10,16
-
- /* Get the slice index * 4 in r11 and matching slice size mask in r9 */
- ld r9,PACALOWSLICESPSIZE(r13)
- sldi r11,r10,2
+ /* below SLICE_LOW_TOP */
blt 5f
- ld r9,PACAHIGHSLICEPSIZE(r13)
- srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
- andi. r11,r11,0x3c
-
-5: /* Extract the psize and multiply to get an array offset */
+ /*
+ * Handle hpsizes,
+ * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
+ * We use r10 here, later we restore it to esid.
+ * Can we use other register instead of r10 ?
+ */
+ srdi r10,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT) /* index */
+ srdi r11,r10,1 /* r11 is array index */
+ addi r9,r11,PACAHIGHSLICEPSIZE
+ lbzx r9,r9,r13 /* r9 is hpsizes[r11] */
+ sldi r11,r11,1
+ subf r11,r11,r10 /* mask_index = index - (array_index << 1) */
+ srdi r10,r3,28 /* restore r10 with esid */
+ b 6f
+5:
+ /*
+ * Handle lpsizes
+ * r9 is get_paca()->context.low_slices_psize, r11 is index
+ */
+ ld r9,PACALOWSLICESPSIZE(r13)
+ mr r11,r10
+6:
+ sldi r11,r11,2 /* index * 4 */
+ /* Extract the psize and multiply to get an array offset */
srd r9,r9,r11
andi. r9,r9,0xf
mulli r9,r9,MMUPSIZEDEFSIZE
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 73709f7..302a481 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -42,7 +42,7 @@ int _slice_debug = 1;
static void slice_print_mask(const char *label, struct slice_mask mask)
{
- char *p, buf[16 + 3 + 16 + 1];
+ char *p, buf[16 + 3 + 64 + 1];
int i;
if (!_slice_debug)
@@ -142,19 +142,24 @@ static struct slice_mask slice_mask_for_free(struct mm_struct *mm)
static struct slice_mask slice_mask_for_size(struct mm_struct *mm, int psize)
{
+ unsigned char *hpsizes;
+ int index, mask_index;
struct slice_mask ret = { 0, 0 };
unsigned long i;
- u64 psizes;
+ u64 lpsizes;
- psizes = mm->context.low_slices_psize;
+ lpsizes = mm->context.low_slices_psize;
for (i = 0; i < SLICE_NUM_LOW; i++)
- if (((psizes >> (i * 4)) & 0xf) == psize)
+ if (((lpsizes >> (i * 4)) & 0xf) == psize)
ret.low_slices |= 1u << i;
- psizes = mm->context.high_slices_psize;
- for (i = 0; i < SLICE_NUM_HIGH; i++)
- if (((psizes >> (i * 4)) & 0xf) == psize)
+ hpsizes = mm->context.high_slices_psize;
+ for (i = 0; i < SLICE_NUM_HIGH; i++) {
+ index = i >> 1;
+ mask_index = i - (index << 1);
+ if (((hpsizes[index] >> (mask_index * 4)) & 0xf) == psize)
ret.high_slices |= 1u << i;
+ }
return ret;
}
@@ -183,8 +188,10 @@ static void slice_flush_segments(void *parm)
static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psize)
{
+ int index, mask_index;
/* Write the new slice psize bits */
- u64 lpsizes, hpsizes;
+ unsigned char *hpsizes;
+ u64 lpsizes;
unsigned long i, flags;
slice_dbg("slice_convert(mm=%p, psize=%d)\n", mm, psize);
@@ -201,14 +208,18 @@ static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psiz
lpsizes = (lpsizes & ~(0xful << (i * 4))) |
(((unsigned long)psize) << (i * 4));
+ /* Assign the value back */
+ mm->context.low_slices_psize = lpsizes;
+
hpsizes = mm->context.high_slices_psize;
- for (i = 0; i < SLICE_NUM_HIGH; i++)
+ for (i = 0; i < SLICE_NUM_HIGH; i++) {
+ index = i >> 1;
+ mask_index = i - (index << 1);
if (mask.high_slices & (1u << i))
- hpsizes = (hpsizes & ~(0xful << (i * 4))) |
- (((unsigned long)psize) << (i * 4));
-
- mm->context.low_slices_psize = lpsizes;
- mm->context.high_slices_psize = hpsizes;
+ hpsizes[index] = (hpsizes[index] &
+ ~(0xf << (mask_index * 4))) |
+ (((unsigned long)psize) << (mask_index * 4));
+ }
slice_dbg(" lsps=%lx, hsps=%lx\n",
mm->context.low_slices_psize,
@@ -587,18 +598,19 @@ unsigned long arch_get_unmapped_area_topdown(struct file *filp,
unsigned int get_slice_psize(struct mm_struct *mm, unsigned long addr)
{
- u64 psizes;
- int index;
+ unsigned char *hpsizes;
+ int index, mask_index;
if (addr < SLICE_LOW_TOP) {
- psizes = mm->context.low_slices_psize;
+ u64 lpsizes;
+ lpsizes = mm->context.low_slices_psize;
index = GET_LOW_SLICE_INDEX(addr);
- } else {
- psizes = mm->context.high_slices_psize;
- index = GET_HIGH_SLICE_INDEX(addr);
+ return (lpsizes >> (index * 4)) & 0xf;
}
-
- return (psizes >> (index * 4)) & 0xf;
+ hpsizes = mm->context.high_slices_psize;
+ index = GET_HIGH_SLICE_INDEX(addr) >> 1;
+ mask_index = GET_HIGH_SLICE_INDEX(addr) - (index << 1);
+ return (hpsizes[index] >> (mask_index * 4)) & 0xf;
}
EXPORT_SYMBOL_GPL(get_slice_psize);
@@ -618,7 +630,9 @@ EXPORT_SYMBOL_GPL(get_slice_psize);
*/
void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
{
- unsigned long flags, lpsizes, hpsizes;
+ int index, mask_index;
+ unsigned char *hpsizes;
+ unsigned long flags, lpsizes;
unsigned int old_psize;
int i;
@@ -639,15 +653,21 @@ void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
if (((lpsizes >> (i * 4)) & 0xf) == old_psize)
lpsizes = (lpsizes & ~(0xful << (i * 4))) |
(((unsigned long)psize) << (i * 4));
+ /* Assign the value back */
+ mm->context.low_slices_psize = lpsizes;
hpsizes = mm->context.high_slices_psize;
- for (i = 0; i < SLICE_NUM_HIGH; i++)
- if (((hpsizes >> (i * 4)) & 0xf) == old_psize)
- hpsizes = (hpsizes & ~(0xful << (i * 4))) |
- (((unsigned long)psize) << (i * 4));
+ for (i = 0; i < SLICE_NUM_HIGH; i++) {
+ index = i >> 1;
+ mask_index = i - (index << 1);
+ if (((hpsizes[index] >> (mask_index * 4)) & 0xf) == old_psize)
+ hpsizes[index] = (hpsizes[index] &
+ ~(0xf << (mask_index * 4))) |
+ (((unsigned long)psize) << (mask_index * 4));
+ }
+
+
- mm->context.low_slices_psize = lpsizes;
- mm->context.high_slices_psize = hpsizes;
slice_dbg(" lsps=%lx, hsps=%lx\n",
mm->context.low_slices_psize,
@@ -660,18 +680,27 @@ void slice_set_user_psize(struct mm_struct *mm, unsigned int psize)
void slice_set_psize(struct mm_struct *mm, unsigned long address,
unsigned int psize)
{
+ unsigned char *hpsizes;
unsigned long i, flags;
- u64 *p;
+ u64 *lpsizes;
spin_lock_irqsave(&slice_convert_lock, flags);
if (address < SLICE_LOW_TOP) {
i = GET_LOW_SLICE_INDEX(address);
- p = &mm->context.low_slices_psize;
+ lpsizes = &mm->context.low_slices_psize;
+ *lpsizes = (*lpsizes & ~(0xful << (i * 4))) |
+ ((unsigned long) psize << (i * 4));
} else {
+ int index, mask_index;
i = GET_HIGH_SLICE_INDEX(address);
- p = &mm->context.high_slices_psize;
+ hpsizes = mm->context.high_slices_psize;
+ index = i >> 1;
+ mask_index = i - (index << 1);
+ hpsizes[index] = (hpsizes[index] &
+ ~(0xf << (mask_index * 4))) |
+ (((unsigned long)psize) << (mask_index * 4));
}
- *p = (*p & ~(0xful << (i * 4))) | ((unsigned long) psize << (i * 4));
+
spin_unlock_irqrestore(&slice_convert_lock, flags);
#ifdef CONFIG_SPU_BASE
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 08/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
` (6 preceding siblings ...)
2012-07-09 13:13 ` [PATCH -V3 07/11] arch/powerpc: Increase the slice range to 64TB Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-23 0:20 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte Aneesh Kumar K.V
` (2 subsequent siblings)
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
slice array size and slice mask size depend on PGTABLE_RANGE. We
can't directly include pgtable.h in these header because there is
a circular dependency. So add compile time check for these values.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 13 ++++++++-----
arch/powerpc/include/asm/page_64.h | 17 ++++++++++++++---
arch/powerpc/include/asm/pgtable-ppc64.h | 8 ++++++++
arch/powerpc/mm/slice.c | 12 ++++++------
4 files changed, 36 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 35b74e8..aa0d560 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -419,6 +419,13 @@ extern void slb_set_size(u16 size);
srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
add rt,rt,rx
+/* 4 bits per slice and we have one slice per 1TB */
+#if 0 /* We can't directly include pgtable.h hence this hack */
+#define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41)
+#else
+/* Right now we only support 64TB */
+#define SLICE_ARRAY_SIZE 32
+#endif
#ifndef __ASSEMBLY__
@@ -463,11 +470,7 @@ typedef struct {
#ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */
- /*
- * Right now we support 64TB and 4 bits for each
- * 1TB slice we need 32 bytes for 64TB.
- */
- unsigned char high_slices_psize[32]; /* 4 bits per slice for now */
+ unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
#else
u16 sllp; /* SLB page size encoding */
#endif
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 6c9bef4..141853e 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -78,15 +78,26 @@ extern u64 ppc64_pft_size;
#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
+/* 1 bit per slice and we have one slice per 1TB */
+#if 0 /* We can't directly include pgtable.h hence this hack */
+#define SLICE_MASK_SIZE (PGTABLE_RANG >> 43)
+#else
+/* Right now we support only 64TB */
+#define SLICE_MASK_SIZE 8
+#endif
+
#ifndef __ASSEMBLY__
struct slice_mask {
u16 low_slices;
/*
- * This should be derived out of PGTABLE_RANGE. For the current
- * max 64TB, u64 should be ok.
+ * We do this as a union so that we can verify
+ * SLICE_MASK_SIZE against PGTABLE_RANGE
*/
- u64 high_slices;
+ union {
+ u64 high_slices;
+ unsigned char not_used[SLICE_MASK_SIZE];
+ };
};
struct mm_struct;
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 8af1cf2..dea953f 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -32,6 +32,14 @@
#endif
#endif
+#if (PGTABLE_RANGE >> 41) > SLICE_ARRAY_SIZE
+#error PGTABLE_RANGE exceeds SLICE_ARRAY_SIZE
+#endif
+
+#if (PGTABLE_RANGE >> 43) > SLICE_MASK_SIZE
+#error PGTABLE_RANGE exceeds slice_mask high_slices size
+#endif
+
/*
* Define the address range of the kernel non-linear virtual area
*/
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 302a481..0aa1b2d 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -73,7 +73,7 @@ static struct slice_mask slice_range_to_mask(unsigned long start,
unsigned long len)
{
unsigned long end = start + len - 1;
- struct slice_mask ret = { 0, 0 };
+ struct slice_mask ret = { 0, {0} };
if (start < SLICE_LOW_TOP) {
unsigned long mend = min(end, SLICE_LOW_TOP);
@@ -123,7 +123,7 @@ static int slice_high_has_vma(struct mm_struct *mm, unsigned long slice)
static struct slice_mask slice_mask_for_free(struct mm_struct *mm)
{
- struct slice_mask ret = { 0, 0 };
+ struct slice_mask ret = { 0, {0} };
unsigned long i;
for (i = 0; i < SLICE_NUM_LOW; i++)
@@ -144,7 +144,7 @@ static struct slice_mask slice_mask_for_size(struct mm_struct *mm, int psize)
{
unsigned char *hpsizes;
int index, mask_index;
- struct slice_mask ret = { 0, 0 };
+ struct slice_mask ret = { 0, {0} };
unsigned long i;
u64 lpsizes;
@@ -412,10 +412,10 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
unsigned long flags, unsigned int psize,
int topdown, int use_cache)
{
- struct slice_mask mask = {0, 0};
+ struct slice_mask mask = {0, {0} };
struct slice_mask good_mask;
- struct slice_mask potential_mask = {0,0} /* silence stupid warning */;
- struct slice_mask compat_mask = {0, 0};
+ struct slice_mask potential_mask = {0, {0} } /* silence stupid warning */;
+ struct slice_mask compat_mask = {0, {0} };
int fixed = (flags & MAP_FIXED);
int pshift = max_t(int, mmu_psize_defs[psize].shift, PAGE_SHIFT);
struct mm_struct *mm = current->mm;
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
` (7 preceding siblings ...)
2012-07-09 13:13 ` [PATCH -V3 08/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-23 0:06 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 10/11] arch/powerpc: Use 32bit array for slb cache Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 11/11] arch/powerpc: Add 64TB support Aneesh Kumar K.V
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Increase the number of valid VSID bits in slbmte instruction.
We will use the new bits when we increase valid VSID bits.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/slb_low.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index c355af6..c1fc81c 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -226,7 +226,7 @@ _GLOBAL(slb_allocate_user)
*/
slb_finish_load:
ASM_VSID_SCRAMBLE(r10,r9,256M)
- rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
+ rldimi r11,r10,SLB_VSID_SHIFT,2 /* combine VSID and flags */
/* r3 = EA, r11 = VSID data */
/*
@@ -290,7 +290,7 @@ _GLOBAL(slb_compare_rr_to_size)
slb_finish_load_1T:
srdi r10,r10,40-28 /* get 1T ESID */
ASM_VSID_SCRAMBLE(r10,r9,1T)
- rldimi r11,r10,SLB_VSID_SHIFT_1T,16 /* combine VSID and flags */
+ rldimi r11,r10,SLB_VSID_SHIFT_1T,2 /* combine VSID and flags */
li r10,MMU_SEGSIZE_1T
rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 10/11] arch/powerpc: Use 32bit array for slb cache
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
` (8 preceding siblings ...)
2012-07-09 13:13 ` [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-23 0:27 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 11/11] arch/powerpc: Add 64TB support Aneesh Kumar K.V
10 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
With larger vsid we need to track more bits of ESID in slb cache
for slb invalidate.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/paca.h | 2 +-
arch/powerpc/mm/slb_low.S | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index daf813f..3e7abba 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -100,7 +100,7 @@ struct paca_struct {
/* SLB related definitions */
u16 vmalloc_sllp;
u16 slb_cache_ptr;
- u16 slb_cache[SLB_CACHE_ENTRIES];
+ u32 slb_cache[SLB_CACHE_ENTRIES];
#endif /* CONFIG_PPC_STD_MMU_64 */
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index c1fc81c..d522679 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -269,10 +269,10 @@ _GLOBAL(slb_compare_rr_to_size)
bge 1f
/* still room in the slb cache */
- sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
- rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
- add r11,r11,r13 /* r11 = (u16 *)paca + offset */
- sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
+ sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
+ rldicl r10,r10,36,28 /* get the 36 bits of the ESID */
+ add r11,r11,r13 /* r11 = (u32 *)paca + offset */
+ stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
addi r3,r3,1 /* offset++ */
b 2f
1: /* offset >= SLB_CACHE_ENTRIES */
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
` (9 preceding siblings ...)
2012-07-09 13:13 ` [PATCH -V3 10/11] arch/powerpc: Use 32bit array for slb cache Aneesh Kumar K.V
@ 2012-07-09 13:13 ` Aneesh Kumar K.V
2012-07-23 0:15 ` Paul Mackerras
2012-07-23 9:39 ` Paul Mackerras
10 siblings, 2 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-09 13:13 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 8 ++++----
arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +-
arch/powerpc/include/asm/pgtable-ppc64-64k.h | 2 +-
arch/powerpc/include/asm/processor.h | 4 ++--
arch/powerpc/include/asm/sparsemem.h | 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index aa0d560..a227ba7 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -374,16 +374,16 @@ extern void slb_set_size(u16 size);
*/
#define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
-#define VSID_BITS_256M 36
+#define VSID_BITS_256M 38
#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_1T 24
+#define VSID_BITS_1T 26
#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
#define CONTEXT_BITS 19
-#define USER_ESID_BITS 16
-#define USER_ESID_BITS_1T 4
+#define USER_ESID_BITS 18
+#define USER_ESID_BITS_1T 6
#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
index 6eefdcf..b3eccf2 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
@@ -7,7 +7,7 @@
*/
#define PTE_INDEX_SIZE 9
#define PMD_INDEX_SIZE 7
-#define PUD_INDEX_SIZE 7
+#define PUD_INDEX_SIZE 9
#define PGD_INDEX_SIZE 9
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
index 90533dd..be4e287 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -7,7 +7,7 @@
#define PTE_INDEX_SIZE 12
#define PMD_INDEX_SIZE 12
#define PUD_INDEX_SIZE 0
-#define PGD_INDEX_SIZE 4
+#define PGD_INDEX_SIZE 6
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 413a5ea..ac3861b 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -97,8 +97,8 @@ extern struct task_struct *last_task_used_spe;
#endif
#ifdef CONFIG_PPC64
-/* 64-bit user address space is 44-bits (16TB user VM) */
-#define TASK_SIZE_USER64 (0x0000100000000000UL)
+/* 64-bit user address space is 46-bits (64TB user VM) */
+#define TASK_SIZE_USER64 (0x0000400000000000UL)
/*
* 32-bit user address space is 4GB - 1 page
diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
index 0c5fa31..f6fc0ee 100644
--- a/arch/powerpc/include/asm/sparsemem.h
+++ b/arch/powerpc/include/asm/sparsemem.h
@@ -10,8 +10,8 @@
*/
#define SECTION_SIZE_BITS 24
-#define MAX_PHYSADDR_BITS 44
-#define MAX_PHYSMEM_BITS 44
+#define MAX_PHYSADDR_BITS 46
+#define MAX_PHYSMEM_BITS 46
#endif /* CONFIG_SPARSEMEM */
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn
2012-07-09 13:13 ` [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
@ 2012-07-09 22:41 ` Stephen Rothwell
2012-07-10 6:12 ` Aneesh Kumar K.V
2012-07-09 23:06 ` Stephen Rothwell
2012-07-22 23:42 ` Paul Mackerras
2 siblings, 1 reply; 47+ messages in thread
From: Stephen Rothwell @ 2012-07-09 22:41 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 1501 bytes --]
Hi Aneesh,
On Mon, 9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> wrote:
>
> diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
> index 1c65a59..1c984a6 100644
> --- a/arch/powerpc/include/asm/mmu-hash64.h
> +++ b/arch/powerpc/include/asm/mmu-hash64.h
> @@ -154,9 +155,25 @@ struct mmu_psize_def
> #define MMU_SEGSIZE_256M 0
> #define MMU_SEGSIZE_1T 1
>
> +/*
> + * encode page number shift.
> + * Inorder to fit the 78 bit va in a 64 bit variable we shift the va by
> + * 12 bits. This enable us to address upto 76 bit va.
> + * For hpt hash from a va we can ignore the page size bits of va and for
> + * hpte encoding we ignore upto 23 bits of va. So ignoring lower 12 bits ensure
> + * we work in all cases including 4k page size.
> + */
> +#define VPN_SHIFT 12
>
> +static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
> + int ssize)
> +{
> + unsigned long v;
> + /*
> + * The AVA field omits the low-order 23 bits of the 78 bits VA.
> + * These bits are not needed in the PTE, because the
> + * low-order b of these bits are part of the byte offset
> + * into the virtual page and, if b < 23, the high-order
> + * 23-b of these bits are always used in selecting the
> + * PTEGs to be searched
> + */
> + BUG_ON(VPN_SHIFT > 23);
Could/should this be BUILD_BUG_ON()?
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn
2012-07-09 13:13 ` [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
2012-07-09 22:41 ` Stephen Rothwell
@ 2012-07-09 23:06 ` Stephen Rothwell
2012-07-10 6:15 ` Aneesh Kumar K.V
2012-07-22 23:42 ` Paul Mackerras
2 siblings, 1 reply; 47+ messages in thread
From: Stephen Rothwell @ 2012-07-09 23:06 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 1295 bytes --]
Hi Aneesh,
On Mon, 9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> wrote:
>
> diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
> index 660b8bb..308e29d 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -39,22 +39,33 @@
>
> DEFINE_RAW_SPINLOCK(native_tlbie_lock);
>
> -static inline void __tlbie(unsigned long va, int psize, int ssize)
> +static inline void __tlbie(unsigned long vpn, int psize, int ssize)
> {
> + unsigned long va;
> unsigned int penc;
>
> + /*
> + * We need 14 to 65 bits of va for a tlibe of 4K page
> + * With vpn we ignore the lower VPN_SHIFT bits already.
> + * And top two bits are already ignored because we can
> + * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
> + * of 12.
> + */
> + BUG_ON((77 - 65) > VPN_SHIFT);
BUILD_BUG_ON() ?
> -static inline void __tlbiel(unsigned long va, int psize, int ssize)
> +static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
> {
> + unsigned long va;
> unsigned int penc;
>
> + BUG_ON((77 - 65) > VPN_SHIFT);
BUILD_BUG_ON() ?
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn
2012-07-09 22:41 ` Stephen Rothwell
@ 2012-07-10 6:12 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-10 6:12 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev, paulus
Stephen Rothwell <sfr@canb.auug.org.au> writes:
> Hi Aneesh,
>
> On Mon, 9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> wrote:
>>
>> diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
>> index 1c65a59..1c984a6 100644
>> --- a/arch/powerpc/include/asm/mmu-hash64.h
>> +++ b/arch/powerpc/include/asm/mmu-hash64.h
>> @@ -154,9 +155,25 @@ struct mmu_psize_def
>> #define MMU_SEGSIZE_256M 0
>> #define MMU_SEGSIZE_1T 1
>>
>> +/*
>> + * encode page number shift.
>> + * Inorder to fit the 78 bit va in a 64 bit variable we shift the va by
>> + * 12 bits. This enable us to address upto 76 bit va.
>> + * For hpt hash from a va we can ignore the page size bits of va and for
>> + * hpte encoding we ignore upto 23 bits of va. So ignoring lower 12 bits ensure
>> + * we work in all cases including 4k page size.
>> + */
>> +#define VPN_SHIFT 12
>>
>> +static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
>> + int ssize)
>> +{
>> + unsigned long v;
>> + /*
>> + * The AVA field omits the low-order 23 bits of the 78 bits VA.
>> + * These bits are not needed in the PTE, because the
>> + * low-order b of these bits are part of the byte offset
>> + * into the virtual page and, if b < 23, the high-order
>> + * 23-b of these bits are always used in selecting the
>> + * PTEGs to be searched
>> + */
>> + BUG_ON(VPN_SHIFT > 23);
>
> Could/should this be BUILD_BUG_ON()?
>
Yes. Will update.
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn
2012-07-09 23:06 ` Stephen Rothwell
@ 2012-07-10 6:15 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-10 6:15 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev, paulus
Stephen Rothwell <sfr@canb.auug.org.au> writes:
> Hi Aneesh,
>
> On Mon, 9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> wrote:
>>
>> diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
>> index 660b8bb..308e29d 100644
>> --- a/arch/powerpc/mm/hash_native_64.c
>> +++ b/arch/powerpc/mm/hash_native_64.c
>> @@ -39,22 +39,33 @@
>>
>> DEFINE_RAW_SPINLOCK(native_tlbie_lock);
>>
>> -static inline void __tlbie(unsigned long va, int psize, int ssize)
>> +static inline void __tlbie(unsigned long vpn, int psize, int ssize)
>> {
>> + unsigned long va;
>> unsigned int penc;
>>
>> + /*
>> + * We need 14 to 65 bits of va for a tlibe of 4K page
>> + * With vpn we ignore the lower VPN_SHIFT bits already.
>> + * And top two bits are already ignored because we can
>> + * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
>> + * of 12.
>> + */
>> + BUG_ON((77 - 65) > VPN_SHIFT);
>
> BUILD_BUG_ON() ?
Yes. I also found a bug there. It should be updated as below
BUILD_BUG_ON(VPN_SHIFT > (77 - 65));
We want to make sure we are not ignoring bits above 65th bit.
>
>> -static inline void __tlbiel(unsigned long va, int psize, int ssize)
>> +static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
>> {
>> + unsigned long va;
>> unsigned int penc;
>>
>> + BUG_ON((77 - 65) > VPN_SHIFT);
>
> BUILD_BUG_ON() ?
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 01/11] arch/powerpc: Use hpt_va to compute virtual address
2012-07-09 13:13 ` [PATCH -V3 01/11] arch/powerpc: Use hpt_va to compute virtual address Aneesh Kumar K.V
@ 2012-07-22 23:17 ` Paul Mackerras
0 siblings, 0 replies; 47+ messages in thread
From: Paul Mackerras @ 2012-07-22 23:17 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:31PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> Don't open code the same
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Reviewed-by: Paul Mackerras <paulus@samba.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 02/11] arch/powerpc: Simplify hpte_decode
2012-07-09 13:13 ` [PATCH -V3 02/11] arch/powerpc: Simplify hpte_decode Aneesh Kumar K.V
@ 2012-07-22 23:26 ` Paul Mackerras
2012-07-23 5:41 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-22 23:26 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:32PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> This patch simplify hpte_decode for easy switching of virtual address to
> virtual page number in the later patch
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
I'm not convinced your version is simpler than what was there before.
It's certainly longer now. But it does seem to do the same calculation
as before, so:
Reviewed-by: Paul Mackerras <paulus@samba.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn
2012-07-09 13:13 ` [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
2012-07-09 22:41 ` Stephen Rothwell
2012-07-09 23:06 ` Stephen Rothwell
@ 2012-07-22 23:42 ` Paul Mackerras
2012-07-23 5:54 ` Aneesh Kumar K.V
2 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-22 23:42 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:33PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> This patch convert different functions to take virtual page number
> instead of virtual address. Virtual page number is virtual address
> shifted right by VPN_SHIFT (12) bits. This enable us to have an
> address range of upto 76 bits.
Some comments inline below...
> +/*
> + * encode page number shift.
> + * Inorder to fit the 78 bit va in a 64 bit variable we shift the va by
^ "in order"
> + * 12 bits. This enable us to address upto 76 bit va.
^ "up to"
> + * For hpt hash from a va we can ignore the page size bits of va and for
> + * hpte encoding we ignore upto 23 bits of va. So ignoring lower 12 bits ensure
> + * we work in all cases including 4k page size.
> + */
> +#define VPN_SHIFT 12
This can't be more than 12 bits because we sometimes use 4k pages even
in a kernel configured for 64k pages (e.g. with the subpage_protection
system call).
> +static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
> + int ssize)
> +{
> + unsigned long v;
> + /*
> + * The AVA field omits the low-order 23 bits of the 78 bits VA.
> + * These bits are not needed in the PTE, because the
> + * low-order b of these bits are part of the byte offset
> + * into the virtual page and, if b < 23, the high-order
> + * 23-b of these bits are always used in selecting the
> + * PTEGs to be searched
> + */
> + BUG_ON(VPN_SHIFT > 23);
I don't think we need this. If VPN_SHIFT was computed by some complex
expression whose value is not obvious, then BUG_ON (or BUILD_BUG_ON)
would be appropriate, but since it's just a #define, a comment at the
site of the definition will suffice.
> static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
> int ssize)
> {
> + int mask;
> unsigned long hash, vsid;
>
> + BUG_ON(shift < VPN_SHIFT);
So VPN_SHIFT can be at most 12, since 12 is the smallest shift value
possible here.
> -static inline void __tlbiel(unsigned long va, int psize, int ssize)
> +static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
> {
> + unsigned long va;
> unsigned int penc;
>
> + BUG_ON((77 - 65) > VPN_SHIFT);
> + va = vpn << VPN_SHIFT;
So VPN_SHIFT has to be at least 12. What is the significance of 77
and 65 here?
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 04/11] arch/powerpc: Rename va to vpn
2012-07-09 13:13 ` [PATCH -V3 04/11] arch/powerpc: Rename va " Aneesh Kumar K.V
@ 2012-07-22 23:46 ` Paul Mackerras
2012-07-23 6:14 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-22 23:46 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:34PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> Rename the variable to better reflect the values. No functional change
> in this patch.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
I think you missed a couple: kernel_map_linear_page and
kernel_unmap_linear_page are now broken since you change va to vpn in
the declaration but not in the uses, and you change host_va to
host_vpn in struct hpte_cache but don't fix up the use in
kvmppc_mmu_invalidate_pte. How many configs did you compile-test this
with?
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
2012-07-09 13:13 ` [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate Aneesh Kumar K.V
@ 2012-07-22 23:56 ` Paul Mackerras
2012-07-23 1:22 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-22 23:56 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:35PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> ISA doc doesn't talk about this. As per ISA doc for a 4K page
>
> tlbie RB RS
>
> " The Abbreviated Virtual Address (AVA) field in register RB must
> contain bits 14:65 of the virtual address translated by the TLB
> entry to be invalidated."
>
> That indicate we should not mask the top 16 bits. So remove the same.
Older versions of the architecture (2.02 and earler) require the
masking, so we can't just unconditionally remove it, since that would
potentially break POWER5 and PPC970. People are definitely still
running Linux bare-metal on PPC970s (though arguably not on POWER5).
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 06/11] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE
2012-07-09 13:13 ` [PATCH -V3 06/11] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE Aneesh Kumar K.V
@ 2012-07-22 23:57 ` Paul Mackerras
0 siblings, 0 replies; 47+ messages in thread
From: Paul Mackerras @ 2012-07-22 23:57 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:36PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> As we keep increasing PGTABLE_RANGE we need not increase the virual
> map area for kernel.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Reviewed-by: Paul Mackerras <paulus@samba.org>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 07/11] arch/powerpc: Increase the slice range to 64TB
2012-07-09 13:13 ` [PATCH -V3 07/11] arch/powerpc: Increase the slice range to 64TB Aneesh Kumar K.V
@ 2012-07-23 0:00 ` Paul Mackerras
2012-07-23 7:13 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 0:00 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:37PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> This patch makes the high psizes mask as an unsigned char array
> so that we can have more than 16TB. Currently we support upto
> 64TB
Some comments inline...
> @@ -804,16 +804,19 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
> #ifdef CONFIG_PPC_MM_SLICES
> unsigned int get_paca_psize(unsigned long addr)
> {
> - unsigned long index, slices;
> + u64 lpsizes;
> + unsigned char *hpsizes;
> + unsigned long index, mask_index;
>
> if (addr < SLICE_LOW_TOP) {
> - slices = get_paca()->context.low_slices_psize;
> + lpsizes = get_paca()->context.low_slices_psize;
> index = GET_LOW_SLICE_INDEX(addr);
> - } else {
> - slices = get_paca()->context.high_slices_psize;
> - index = GET_HIGH_SLICE_INDEX(addr);
> + return (lpsizes >> (index * 4)) & 0xF;
> }
> - return (slices >> (index * 4)) & 0xF;
> + hpsizes = get_paca()->context.high_slices_psize;
> + index = GET_HIGH_SLICE_INDEX(addr) >> 1;
> + mask_index = GET_HIGH_SLICE_INDEX(addr) - (index << 1);
> + return (hpsizes[index] >> (mask_index * 4)) & 0xF;
The last 3 lines here feel awkward. How about:
> + index = GET_HIGH_SLICE_INDEX(addr);
> + mask_index = index & 1;
> + return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
> static struct slice_mask slice_mask_for_size(struct mm_struct *mm, int psize)
> {
> + unsigned char *hpsizes;
> + int index, mask_index;
> struct slice_mask ret = { 0, 0 };
> unsigned long i;
> - u64 psizes;
> + u64 lpsizes;
>
> - psizes = mm->context.low_slices_psize;
> + lpsizes = mm->context.low_slices_psize;
> for (i = 0; i < SLICE_NUM_LOW; i++)
> - if (((psizes >> (i * 4)) & 0xf) == psize)
> + if (((lpsizes >> (i * 4)) & 0xf) == psize)
> ret.low_slices |= 1u << i;
>
> - psizes = mm->context.high_slices_psize;
> - for (i = 0; i < SLICE_NUM_HIGH; i++)
> - if (((psizes >> (i * 4)) & 0xf) == psize)
> + hpsizes = mm->context.high_slices_psize;
> + for (i = 0; i < SLICE_NUM_HIGH; i++) {
> + index = i >> 1;
> + mask_index = i - (index << 1);
Again, seems like a complicated way to do mask_index = i & 1 (or
even i % 2, if you prefer, but then make i an unsigned type).
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte
2012-07-09 13:13 ` [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte Aneesh Kumar K.V
@ 2012-07-23 0:06 ` Paul Mackerras
2012-07-23 8:21 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 0:06 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:39PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> Increase the number of valid VSID bits in slbmte instruction.
> We will use the new bits when we increase valid VSID bits.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/mm/slb_low.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
> index c355af6..c1fc81c 100644
> --- a/arch/powerpc/mm/slb_low.S
> +++ b/arch/powerpc/mm/slb_low.S
> @@ -226,7 +226,7 @@ _GLOBAL(slb_allocate_user)
> */
> slb_finish_load:
> ASM_VSID_SCRAMBLE(r10,r9,256M)
> - rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
> + rldimi r11,r10,SLB_VSID_SHIFT,2 /* combine VSID and flags */
You can't do that without either changing ASM_VSID_SCRAMBLE or masking
the VSID it generates to 36 bits, since the logic in ASM_VSID_SCRAMBLE
can leave non-zero bits in the high 28 bits of the result. Similarly
for the 1T case.
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-09 13:13 ` [PATCH -V3 11/11] arch/powerpc: Add 64TB support Aneesh Kumar K.V
@ 2012-07-23 0:15 ` Paul Mackerras
2012-07-23 8:49 ` Aneesh Kumar K.V
2012-07-23 9:39 ` Paul Mackerras
1 sibling, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 0:15 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> Increase max addressable range to 64TB. This is not tested on
> real hardware yet.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/mmu-hash64.h | 8 ++++----
> arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +-
> arch/powerpc/include/asm/pgtable-ppc64-64k.h | 2 +-
> arch/powerpc/include/asm/processor.h | 4 ++--
> arch/powerpc/include/asm/sparsemem.h | 4 ++--
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
> index aa0d560..a227ba7 100644
> --- a/arch/powerpc/include/asm/mmu-hash64.h
> +++ b/arch/powerpc/include/asm/mmu-hash64.h
> @@ -374,16 +374,16 @@ extern void slb_set_size(u16 size);
> */
>
> #define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
> -#define VSID_BITS_256M 36
> +#define VSID_BITS_256M 38
> #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
With these settings, the multiplication in ASM_VSID_SCRAMBLE could
overflow, leading to incorrect results (which would cause occasional
corruption of user processes under heavy load). You will need to
reduce the multiplier to be less than 2^26, and it will need to be
co-prime with 2^38 - 1. (Probably, the same value as we use in the 1T
case would be OK.)
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 08/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit
2012-07-09 13:13 ` [PATCH -V3 08/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit Aneesh Kumar K.V
@ 2012-07-23 0:20 ` Paul Mackerras
2012-07-23 7:29 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 0:20 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:38PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> slice array size and slice mask size depend on PGTABLE_RANGE. We
> can't directly include pgtable.h in these header because there is
> a circular dependency. So add compile time check for these values.
Some comments below...
> struct slice_mask {
> u16 low_slices;
> /*
> - * This should be derived out of PGTABLE_RANGE. For the current
> - * max 64TB, u64 should be ok.
> + * We do this as a union so that we can verify
> + * SLICE_MASK_SIZE against PGTABLE_RANGE
> */
> - u64 high_slices;
> + union {
> + u64 high_slices;
> + unsigned char not_used[SLICE_MASK_SIZE];
> + };
Seems ugly to have to have a union just for that. Can't we do
something like BUILD_BUG_ON(sizeof(u64) < SLICE_MASK_SIZE) instead?
> @@ -73,7 +73,7 @@ static struct slice_mask slice_range_to_mask(unsigned long start,
> unsigned long len)
> {
> unsigned long end = start + len - 1;
> - struct slice_mask ret = { 0, 0 };
> + struct slice_mask ret = { 0, {0} };
Wouldn't { 0 } suffice? Similarly in several places below.
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 10/11] arch/powerpc: Use 32bit array for slb cache
2012-07-09 13:13 ` [PATCH -V3 10/11] arch/powerpc: Use 32bit array for slb cache Aneesh Kumar K.V
@ 2012-07-23 0:27 ` Paul Mackerras
2012-07-23 8:25 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 0:27 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:40PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> With larger vsid we need to track more bits of ESID in slb cache
> for slb invalidate.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Minor comment below, but apart from that...
Reviewed-by: Paul Mackerras <paulus@samba.org>
> - sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
> - rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
> - add r11,r11,r13 /* r11 = (u16 *)paca + offset */
> - sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
> + sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
> + rldicl r10,r10,36,28 /* get the 36 bits of the ESID */
You're correct that the rldicl instruction produces 36 bits of result,
and in fact it is equivalent to srdi r10,r10,28. If you're changing
the line you might as well change the instruction to the simpler form
too.
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
2012-07-22 23:56 ` Paul Mackerras
@ 2012-07-23 1:22 ` Benjamin Herrenschmidt
2012-07-23 3:49 ` Paul Mackerras
0 siblings, 1 reply; 47+ messages in thread
From: Benjamin Herrenschmidt @ 2012-07-23 1:22 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Aneesh Kumar K.V
On Mon, 2012-07-23 at 09:56 +1000, Paul Mackerras wrote:
> > That indicate we should not mask the top 16 bits. So remove the
> same.
>
> Older versions of the architecture (2.02 and earler) require the
> masking, so we can't just unconditionally remove it, since that would
> potentially break POWER5 and PPC970. People are definitely still
> running Linux bare-metal on PPC970s (though arguably not on POWER5).
Are you sure ? I couldn't convince myself ... the old architectures say
that it only uses some of the bits but it doesn't mark the other ones as
"reserved" (as in must be 0).
(At least 1.x, I haven't looked at 2.x with x < 03)
Cheers,
Ben.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
2012-07-23 1:22 ` Benjamin Herrenschmidt
@ 2012-07-23 3:49 ` Paul Mackerras
2012-07-23 6:44 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 3:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Aneesh Kumar K.V
On Mon, Jul 23, 2012 at 11:22:08AM +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2012-07-23 at 09:56 +1000, Paul Mackerras wrote:
> > > That indicate we should not mask the top 16 bits. So remove the
> > same.
> >
> > Older versions of the architecture (2.02 and earler) require the
> > masking, so we can't just unconditionally remove it, since that would
> > potentially break POWER5 and PPC970. People are definitely still
> > running Linux bare-metal on PPC970s (though arguably not on POWER5).
>
> Are you sure ? I couldn't convince myself ... the old architectures say
> that it only uses some of the bits but it doesn't mark the other ones as
> "reserved" (as in must be 0).
>
> (At least 1.x, I haven't looked at 2.x with x < 03)
2.01 and 2.02 say bits 0..15 must be zero.
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 02/11] arch/powerpc: Simplify hpte_decode
2012-07-22 23:26 ` Paul Mackerras
@ 2012-07-23 5:41 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 5:41 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:32PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> This patch simplify hpte_decode for easy switching of virtual address to
>> virtual page number in the later patch
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> I'm not convinced your version is simpler than what was there before.
> It's certainly longer now. But it does seem to do the same calculation
> as before, so:
This actually make patch 3 "arch/powerpc: Convert virtual address to vpn"
simpler. The hpte_decode hunk is a one line change after this
>
> Reviewed-by: Paul Mackerras <paulus@samba.org>
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn
2012-07-22 23:42 ` Paul Mackerras
@ 2012-07-23 5:54 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 5:54 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:33PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> This patch convert different functions to take virtual page number
>> instead of virtual address. Virtual page number is virtual address
>> shifted right by VPN_SHIFT (12) bits. This enable us to have an
>> address range of upto 76 bits.
>
> Some comments inline below...
>
>> +/*
>> + * encode page number shift.
>> + * Inorder to fit the 78 bit va in a 64 bit variable we shift the va by
> ^ "in order"
>
>> + * 12 bits. This enable us to address upto 76 bit va.
> ^ "up to"
>
>> + * For hpt hash from a va we can ignore the page size bits of va and for
>> + * hpte encoding we ignore upto 23 bits of va. So ignoring lower 12 bits ensure
>> + * we work in all cases including 4k page size.
>> + */
>> +#define VPN_SHIFT 12
>
> This can't be more than 12 bits because we sometimes use 4k pages even
> in a kernel configured for 64k pages (e.g. with the subpage_protection
> system call).
Yes, I wanted to make that explicit, ie this is not a virtual page
number and hence all these BUG_ON. I actually updated few of them
to BUILD_BUG_ON() based of earlier review.
>
>> +static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
>> + int ssize)
>> +{
>> + unsigned long v;
>> + /*
>> + * The AVA field omits the low-order 23 bits of the 78 bits VA.
>> + * These bits are not needed in the PTE, because the
>> + * low-order b of these bits are part of the byte offset
>> + * into the virtual page and, if b < 23, the high-order
>> + * 23-b of these bits are always used in selecting the
>> + * PTEGs to be searched
>> + */
>> + BUG_ON(VPN_SHIFT > 23);
>
> I don't think we need this. If VPN_SHIFT was computed by some complex
> expression whose value is not obvious, then BUG_ON (or BUILD_BUG_ON)
> would be appropriate, but since it's just a #define, a comment at the
> site of the definition will suffice.
>
>> static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
>> int ssize)
>> {
>> + int mask;
>> unsigned long hash, vsid;
>>
>> + BUG_ON(shift < VPN_SHIFT);
>
> So VPN_SHIFT can be at most 12, since 12 is the smallest shift value
> possible here.
>
>> -static inline void __tlbiel(unsigned long va, int psize, int ssize)
>> +static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
>> {
>> + unsigned long va;
>> unsigned int penc;
>>
>> + BUG_ON((77 - 65) > VPN_SHIFT);
>> + va = vpn << VPN_SHIFT;
>
> So VPN_SHIFT has to be at least 12. What is the significance of 77
> and 65 here?
>
It is the other way around . I updated that in 77guccfav.fsf@skywalker.in.ibm.com
BUILD_BUG_ON(VPN_SHIFT > (77 - 65));
tlbiel says we can only ignore bits above 65 of va. hence the math of 77- 65.
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 04/11] arch/powerpc: Rename va to vpn
2012-07-22 23:46 ` Paul Mackerras
@ 2012-07-23 6:14 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 6:14 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:34PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> Rename the variable to better reflect the values. No functional change
>> in this patch.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> I think you missed a couple: kernel_map_linear_page and
> kernel_unmap_linear_page are now broken since you change va to vpn in
> the declaration but not in the uses, and you change host_va to
> host_vpn in struct hpte_cache but don't fix up the use in
> kvmppc_mmu_invalidate_pte.
Will fix.
> How many configs did you compile-test this
> with?
Not much. I will try to do a test build of multiple configs.
Thanks
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
2012-07-23 3:49 ` Paul Mackerras
@ 2012-07-23 6:44 ` Aneesh Kumar K.V
2012-07-23 6:48 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 6:44 UTC (permalink / raw)
To: Paul Mackerras, Benjamin Herrenschmidt; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 23, 2012 at 11:22:08AM +1000, Benjamin Herrenschmidt wrote:
>> On Mon, 2012-07-23 at 09:56 +1000, Paul Mackerras wrote:
>> > > That indicate we should not mask the top 16 bits. So remove the
>> > same.
>> >
>> > Older versions of the architecture (2.02 and earler) require the
>> > masking, so we can't just unconditionally remove it, since that would
>> > potentially break POWER5 and PPC970. People are definitely still
>> > running Linux bare-metal on PPC970s (though arguably not on POWER5).
>>
>> Are you sure ? I couldn't convince myself ... the old architectures say
>> that it only uses some of the bits but it doesn't mark the other ones as
>> "reserved" (as in must be 0).
>>
>> (At least 1.x, I haven't looked at 2.x with x < 03)
>
> 2.01 and 2.02 say bits 0..15 must be zero.
is this 0..15 of va or 0..15 of AVA ?
if it is 0.. 15 then that clear bit is wrong right ? We are doing that
on a 64 bit va. So with that we already have ignored 0..14.
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
2012-07-23 6:44 ` Aneesh Kumar K.V
@ 2012-07-23 6:48 ` Benjamin Herrenschmidt
0 siblings, 0 replies; 47+ messages in thread
From: Benjamin Herrenschmidt @ 2012-07-23 6:48 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, Paul Mackerras
On Mon, 2012-07-23 at 12:14 +0530, Aneesh Kumar K.V wrote:
>
> if it is 0.. 15 then that clear bit is wrong right ? We are doing that
> on a 64 bit va. So with that we already have ignored 0..14.
It's bit 0..15 of RB passed to tlbie
Cheers,
Ben.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 07/11] arch/powerpc: Increase the slice range to 64TB
2012-07-23 0:00 ` Paul Mackerras
@ 2012-07-23 7:13 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 7:13 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:37PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> This patch makes the high psizes mask as an unsigned char array
>> so that we can have more than 16TB. Currently we support upto
>> 64TB
>
> Some comments inline...
>
>> @@ -804,16 +804,19 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
>> #ifdef CONFIG_PPC_MM_SLICES
>> unsigned int get_paca_psize(unsigned long addr)
>> {
>> - unsigned long index, slices;
>> + u64 lpsizes;
>> + unsigned char *hpsizes;
>> + unsigned long index, mask_index;
>>
>> if (addr < SLICE_LOW_TOP) {
>> - slices = get_paca()->context.low_slices_psize;
>> + lpsizes = get_paca()->context.low_slices_psize;
>> index = GET_LOW_SLICE_INDEX(addr);
>> - } else {
>> - slices = get_paca()->context.high_slices_psize;
>> - index = GET_HIGH_SLICE_INDEX(addr);
>> + return (lpsizes >> (index * 4)) & 0xF;
>> }
>> - return (slices >> (index * 4)) & 0xF;
>> + hpsizes = get_paca()->context.high_slices_psize;
>> + index = GET_HIGH_SLICE_INDEX(addr) >> 1;
>> + mask_index = GET_HIGH_SLICE_INDEX(addr) - (index << 1);
>> + return (hpsizes[index] >> (mask_index * 4)) & 0xF;
>
> The last 3 lines here feel awkward. How about:
>
index = GET_HIGH_SLICE_INDEX(addr);
mask_index = index & 1;
return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
That is much simpler. I updated the patch, changing to the above format in
all the location.
>
>> static struct slice_mask slice_mask_for_size(struct mm_struct *mm, int psize)
>> {
>> + unsigned char *hpsizes;
>> + int index, mask_index;
>> struct slice_mask ret = { 0, 0 };
>> unsigned long i;
>> - u64 psizes;
>> + u64 lpsizes;
>>
>> - psizes = mm->context.low_slices_psize;
>> + lpsizes = mm->context.low_slices_psize;
>> for (i = 0; i < SLICE_NUM_LOW; i++)
>> - if (((psizes >> (i * 4)) & 0xf) == psize)
>> + if (((lpsizes >> (i * 4)) & 0xf) == psize)
>> ret.low_slices |= 1u << i;
>>
>> - psizes = mm->context.high_slices_psize;
>> - for (i = 0; i < SLICE_NUM_HIGH; i++)
>> - if (((psizes >> (i * 4)) & 0xf) == psize)
>> + hpsizes = mm->context.high_slices_psize;
>> + for (i = 0; i < SLICE_NUM_HIGH; i++) {
>> + index = i >> 1;
>> + mask_index = i - (index << 1);
>
> Again, seems like a complicated way to do mask_index = i & 1 (or
> even i % 2, if you prefer, but then make i an unsigned type).
>
> Paul.
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 08/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit
2012-07-23 0:20 ` Paul Mackerras
@ 2012-07-23 7:29 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 7:29 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:38PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> slice array size and slice mask size depend on PGTABLE_RANGE. We
>> can't directly include pgtable.h in these header because there is
>> a circular dependency. So add compile time check for these values.
>
> Some comments below...
>
>> struct slice_mask {
>> u16 low_slices;
>> /*
>> - * This should be derived out of PGTABLE_RANGE. For the current
>> - * max 64TB, u64 should be ok.
>> + * We do this as a union so that we can verify
>> + * SLICE_MASK_SIZE against PGTABLE_RANGE
>> */
>> - u64 high_slices;
>> + union {
>> + u64 high_slices;
>> + unsigned char not_used[SLICE_MASK_SIZE];
>> + };
>
> Seems ugly to have to have a union just for that. Can't we do
> something like BUILD_BUG_ON(sizeof(u64) < SLICE_MASK_SIZE) instead?
Dropped the union from the patch
>
>> @@ -73,7 +73,7 @@ static struct slice_mask slice_range_to_mask(unsigned long start,
>> unsigned long len)
>> {
>> unsigned long end = start + len - 1;
>> - struct slice_mask ret = { 0, 0 };
>> + struct slice_mask ret = { 0, {0} };
>
> Wouldn't { 0 } suffice? Similarly in several places below.
Once i drop the union all these changes can be dropped.
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte
2012-07-23 0:06 ` Paul Mackerras
@ 2012-07-23 8:21 ` Aneesh Kumar K.V
2012-07-23 9:36 ` Paul Mackerras
0 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 8:21 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:39PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> Increase the number of valid VSID bits in slbmte instruction.
>> We will use the new bits when we increase valid VSID bits.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> arch/powerpc/mm/slb_low.S | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
>> index c355af6..c1fc81c 100644
>> --- a/arch/powerpc/mm/slb_low.S
>> +++ b/arch/powerpc/mm/slb_low.S
>> @@ -226,7 +226,7 @@ _GLOBAL(slb_allocate_user)
>> */
>> slb_finish_load:
>> ASM_VSID_SCRAMBLE(r10,r9,256M)
>> - rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
>> + rldimi r11,r10,SLB_VSID_SHIFT,2 /* combine VSID and flags */
>
> You can't do that without either changing ASM_VSID_SCRAMBLE or masking
> the VSID it generates to 36 bits, since the logic in ASM_VSID_SCRAMBLE
> can leave non-zero bits in the high 28 bits of the result. Similarly
> for the 1T case.
>
How about change ASM_VSID_SCRAMBLE to clear the high bits ? That would
also make it close to vsid_scramble()
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index d24d484..173bb34 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -420,7 +420,8 @@ extern void slb_set_size(u16 size);
* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
addi rx,rt,1; \
srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
- add rt,rt,rx
+ add rt,rt,rx; \
+ clrldi rt,rt,(64 - VSID_BITS_##size);
/* 4 bits per slice and we have one slice per 1TB */
#if 0 /* We can't directly include pgtable.h hence this hack */
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 10/11] arch/powerpc: Use 32bit array for slb cache
2012-07-23 0:27 ` Paul Mackerras
@ 2012-07-23 8:25 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 8:25 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:40PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> With larger vsid we need to track more bits of ESID in slb cache
>> for slb invalidate.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> Minor comment below, but apart from that...
>
> Reviewed-by: Paul Mackerras <paulus@samba.org>
>
>> - sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
>> - rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
>> - add r11,r11,r13 /* r11 = (u16 *)paca + offset */
>> - sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
>> + sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
>> + rldicl r10,r10,36,28 /* get the 36 bits of the ESID */
>
> You're correct that the rldicl instruction produces 36 bits of result,
> and in fact it is equivalent to srdi r10,r10,28. If you're changing
> the line you might as well change the instruction to the simpler form
> too.
done.
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-23 0:15 ` Paul Mackerras
@ 2012-07-23 8:49 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 8:49 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> Increase max addressable range to 64TB. This is not tested on
>> real hardware yet.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> arch/powerpc/include/asm/mmu-hash64.h | 8 ++++----
>> arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +-
>> arch/powerpc/include/asm/pgtable-ppc64-64k.h | 2 +-
>> arch/powerpc/include/asm/processor.h | 4 ++--
>> arch/powerpc/include/asm/sparsemem.h | 4 ++--
>> 5 files changed, 10 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
>> index aa0d560..a227ba7 100644
>> --- a/arch/powerpc/include/asm/mmu-hash64.h
>> +++ b/arch/powerpc/include/asm/mmu-hash64.h
>> @@ -374,16 +374,16 @@ extern void slb_set_size(u16 size);
>> */
>>
>> #define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
>> -#define VSID_BITS_256M 36
>> +#define VSID_BITS_256M 38
>> #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
>
> With these settings, the multiplication in ASM_VSID_SCRAMBLE could
> overflow, leading to incorrect results (which would cause occasional
> corruption of user processes under heavy load). You will need to
> reduce the multiplier to be less than 2^26, and it will need to be
> co-prime with 2^38 - 1. (Probably, the same value as we use in the 1T
> case would be OK.)
I ended up using the same value as VSID_MULTIPLIER_1T.
(gdb) p/d 1ull << 38
$1 = 274877906944
(gdb) p/d 274877906943/12538073
$2 = 21923
(gdb) p/d 12538073ll*21923
$5 = 274872174379
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte
2012-07-23 8:21 ` Aneesh Kumar K.V
@ 2012-07-23 9:36 ` Paul Mackerras
2012-07-23 10:22 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 9:36 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 23, 2012 at 01:51:49PM +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras <paulus@samba.org> writes:
>
> > On Mon, Jul 09, 2012 at 06:43:39PM +0530, Aneesh Kumar K.V wrote:
> >> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
> >>
> >> Increase the number of valid VSID bits in slbmte instruction.
> >> We will use the new bits when we increase valid VSID bits.
> >>
> >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> >> ---
> >> arch/powerpc/mm/slb_low.S | 4 ++--
> >> 1 file changed, 2 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
> >> index c355af6..c1fc81c 100644
> >> --- a/arch/powerpc/mm/slb_low.S
> >> +++ b/arch/powerpc/mm/slb_low.S
> >> @@ -226,7 +226,7 @@ _GLOBAL(slb_allocate_user)
> >> */
> >> slb_finish_load:
> >> ASM_VSID_SCRAMBLE(r10,r9,256M)
> >> - rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
> >> + rldimi r11,r10,SLB_VSID_SHIFT,2 /* combine VSID and flags */
> >
> > You can't do that without either changing ASM_VSID_SCRAMBLE or masking
> > the VSID it generates to 36 bits, since the logic in ASM_VSID_SCRAMBLE
> > can leave non-zero bits in the high 28 bits of the result. Similarly
> > for the 1T case.
> >
>
> How about change ASM_VSID_SCRAMBLE to clear the high bits ? That would
> also make it close to vsid_scramble()
One more instruction in a hot path - I'd rather not. How about
changing the rldimi instruction to:
rldimi r11,r10,SLB_VSID_SHIFT,(64-SLB_VSID_SHIFT-VSID_BITS_256M)
and similarly for the 1T case. That will give the proper masking
when you change VSID_BITS_256M.
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-09 13:13 ` [PATCH -V3 11/11] arch/powerpc: Add 64TB support Aneesh Kumar K.V
2012-07-23 0:15 ` Paul Mackerras
@ 2012-07-23 9:39 ` Paul Mackerras
2012-07-23 10:22 ` Aneesh Kumar K.V
1 sibling, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 9:39 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
> -#define USER_ESID_BITS 16
> -#define USER_ESID_BITS_1T 4
> +#define USER_ESID_BITS 18
> +#define USER_ESID_BITS_1T 6
You also need to change the proto-VSID generation for kernel addresses
when you do this. If you don't you'll end up with some user processes
using the same VSIDs as we use for the kernel addresses, meaning that
those processes won't run very well...
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-23 9:39 ` Paul Mackerras
@ 2012-07-23 10:22 ` Aneesh Kumar K.V
2012-07-23 11:06 ` Paul Mackerras
0 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 10:22 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
>
>> -#define USER_ESID_BITS 16
>> -#define USER_ESID_BITS_1T 4
>> +#define USER_ESID_BITS 18
>> +#define USER_ESID_BITS_1T 6
>
> You also need to change the proto-VSID generation for kernel addresses
> when you do this. If you don't you'll end up with some user processes
> using the same VSIDs as we use for the kernel addresses, meaning that
> those processes won't run very well...
>
Can you explain this more. right now we generate vsid as below
vsid_scramble(ea >> SID_SHIFT, 256M) for kernel
vsid_scramble((context << USER_ESID_BITS) | (ea >> SID_SHIFT), 256M);
for user
what changes are you suggesting ?
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte
2012-07-23 9:36 ` Paul Mackerras
@ 2012-07-23 10:22 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-23 10:22 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 23, 2012 at 01:51:49PM +0530, Aneesh Kumar K.V wrote:
>> Paul Mackerras <paulus@samba.org> writes:
>>
>> > On Mon, Jul 09, 2012 at 06:43:39PM +0530, Aneesh Kumar K.V wrote:
>> >> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>> >>
>> >> Increase the number of valid VSID bits in slbmte instruction.
>> >> We will use the new bits when we increase valid VSID bits.
>> >>
>> >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> >> ---
>> >> arch/powerpc/mm/slb_low.S | 4 ++--
>> >> 1 file changed, 2 insertions(+), 2 deletions(-)
>> >>
>> >> diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
>> >> index c355af6..c1fc81c 100644
>> >> --- a/arch/powerpc/mm/slb_low.S
>> >> +++ b/arch/powerpc/mm/slb_low.S
>> >> @@ -226,7 +226,7 @@ _GLOBAL(slb_allocate_user)
>> >> */
>> >> slb_finish_load:
>> >> ASM_VSID_SCRAMBLE(r10,r9,256M)
>> >> - rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
>> >> + rldimi r11,r10,SLB_VSID_SHIFT,2 /* combine VSID and flags */
>> >
>> > You can't do that without either changing ASM_VSID_SCRAMBLE or masking
>> > the VSID it generates to 36 bits, since the logic in ASM_VSID_SCRAMBLE
>> > can leave non-zero bits in the high 28 bits of the result. Similarly
>> > for the 1T case.
>> >
>>
>> How about change ASM_VSID_SCRAMBLE to clear the high bits ? That would
>> also make it close to vsid_scramble()
>
> One more instruction in a hot path - I'd rather not. How about
> changing the rldimi instruction to:
> rldimi r11,r10,SLB_VSID_SHIFT,(64-SLB_VSID_SHIFT-VSID_BITS_256M)
>
> and similarly for the 1T case. That will give the proper masking
> when you change VSID_BITS_256M.
>
This is better. I have made this change.
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-23 10:22 ` Aneesh Kumar K.V
@ 2012-07-23 11:06 ` Paul Mackerras
2012-07-24 8:37 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Paul Mackerras @ 2012-07-23 11:06 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev
On Mon, Jul 23, 2012 at 03:52:05PM +0530, Aneesh Kumar K.V wrote:
> Paul Mackerras <paulus@samba.org> writes:
>
> > On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
> >
> >> -#define USER_ESID_BITS 16
> >> -#define USER_ESID_BITS_1T 4
> >> +#define USER_ESID_BITS 18
> >> +#define USER_ESID_BITS_1T 6
> >
> > You also need to change the proto-VSID generation for kernel addresses
> > when you do this. If you don't you'll end up with some user processes
> > using the same VSIDs as we use for the kernel addresses, meaning that
> > those processes won't run very well...
> >
>
> Can you explain this more. right now we generate vsid as below
>
> vsid_scramble(ea >> SID_SHIFT, 256M) for kernel
>
> vsid_scramble((context << USER_ESID_BITS) | (ea >> SID_SHIFT), 256M);
> for user
>
> what changes are you suggesting ?
Think about it. With the current values of USER_ESID_BITS and
CONTEXT_BITS, and the addresses we use for kernel mappings, there are
no values of context, user_ea and kernel_ea for which
kernel_ea >> SID_SHIFT == (context << USER_ESID_BITS) | (user_ea >> SID_SHIFT)
If you increase USER_ESID_BITS, then there will be some context values
for which that equation becomes true. For example, if you increase
USER_ESID_BITS to 18, then context 0x30000 will generate the same
proto-VSIDs as the kernel linear mapping. Since we can hand out
contexts up to 0x7ffff (with CONTEXT_BITS = 19), there is a collision.
In other words, the proto-VSID space (the space of values that are
input to vsid_scramble) is currently divided into two mutually
exclusive regions: from 0 to 2^35 - 1 for user processes, and from
2^35 to 2^36 - 1 for kernel addresses. You are wanting to expand the
amount of proto-VSID space that user processes can use, but you need
either to move the kernel portion of the space, or to make sure that
the context allocator doesn't hand out context values that would
collide with the kernel portion of the space (or both).
Paul.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-23 11:06 ` Paul Mackerras
@ 2012-07-24 8:37 ` Aneesh Kumar K.V
2012-07-24 9:14 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-24 8:37 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 23, 2012 at 03:52:05PM +0530, Aneesh Kumar K.V wrote:
>> Paul Mackerras <paulus@samba.org> writes:
>>
>> > On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
>> >
>> >> -#define USER_ESID_BITS 16
>> >> -#define USER_ESID_BITS_1T 4
>> >> +#define USER_ESID_BITS 18
>> >> +#define USER_ESID_BITS_1T 6
>> >
>> > You also need to change the proto-VSID generation for kernel addresses
>> > when you do this. If you don't you'll end up with some user processes
>> > using the same VSIDs as we use for the kernel addresses, meaning that
>> > those processes won't run very well...
>> >
>>
>> Can you explain this more. right now we generate vsid as below
>>
>> vsid_scramble(ea >> SID_SHIFT, 256M) for kernel
>>
>> vsid_scramble((context << USER_ESID_BITS) | (ea >> SID_SHIFT), 256M);
>> for user
>>
>> what changes are you suggesting ?
>
> Think about it. With the current values of USER_ESID_BITS and
> CONTEXT_BITS, and the addresses we use for kernel mappings, there are
> no values of context, user_ea and kernel_ea for which
>
> kernel_ea >> SID_SHIFT == (context << USER_ESID_BITS) | (user_ea >> SID_SHIFT)
>
> If you increase USER_ESID_BITS, then there will be some context values
> for which that equation becomes true. For example, if you increase
> USER_ESID_BITS to 18, then context 0x30000 will generate the same
> proto-VSIDs as the kernel linear mapping. Since we can hand out
> contexts up to 0x7ffff (with CONTEXT_BITS = 19), there is a collision.
>
> In other words, the proto-VSID space (the space of values that are
> input to vsid_scramble) is currently divided into two mutually
> exclusive regions: from 0 to 2^35 - 1 for user processes, and from
> 2^35 to 2^36 - 1 for kernel addresses. You are wanting to expand the
> amount of proto-VSID space that user processes can use, but you need
> either to move the kernel portion of the space, or to make sure that
> the context allocator doesn't hand out context values that would
> collide with the kernel portion of the space (or both).
How about this ?. There is a FIXME in there which is not related.
commit 4881230dc34cbe24141f06004371082da6b121a5
Author: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Date: Tue Jul 24 11:40:29 2012 +0530
proto vsid fixes
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index daa3e4b..736df15 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -516,9 +516,19 @@ typedef struct {
/* This is only valid for addresses >= PAGE_OFFSET */
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble(ea >> SID_SHIFT, 256M);
- return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
+ unsigned long proto_vsid;
+ /*
+ * We need to make sure proto_vsid for the kernel is
+ * >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
+ */
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ea >> SID_SHIFT;
+ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ea >> SID_SHIFT_1T;
+ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
+ return vsid_scramble(proto_vsid, 1T);
}
/* Returns the segment size indicator for a user address */
@@ -534,11 +544,17 @@ static inline int user_segment_size(unsigned long addr)
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble((context << USER_ESID_BITS)
- | (ea >> SID_SHIFT), 256M);
- return vsid_scramble((context << USER_ESID_BITS_1T)
- | (ea >> SID_SHIFT_1T), 1T);
+ unsigned long proto_vsid;
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ((context << USER_ESID_BITS) |(ea >> SID_SHIFT));
+ /* truncate this to 37 bits */
+ proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS)) - 1;
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ((context << USER_ESID_BITS_1T) | (ea >> SID_SHIFT_1T));
+ /* truncate this to 25 bits */
+ proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T)) - 1;
+ return vsid_scramble( proto_vsid, 1T);
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 1c06d29..40ed208 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -958,7 +958,9 @@ _GLOBAL(do_stab_bolted)
rldimi r10,r11,7,52 /* r10 = first ste of the group */
/* Calculate VSID */
- /* This is a kernel address, so protovsid = ESID */
+ /* This is a kernel address, so protovsid = ESID | 1 << 37 */
+ li r9,0x1
+ rldimi r11,r9,(CONTEXT_BITS + USER_ESID_BITS),0
ASM_VSID_SCRAMBLE(r11, r9, 256M)
rldic r9,r11,12,16 /* r9 = vsid << 12 */
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index db2cb3f..792bfa8 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -57,8 +57,13 @@ _GLOBAL(slb_allocate_realmode)
_GLOBAL(slb_miss_kernel_load_linear)
li r11,0
BEGIN_FTR_SECTION
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS_1T),0
b slb_finish_load_1T
1:
@@ -86,8 +91,13 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
li r11,0
6:
BEGIN_FTR_SECTION
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS_1T),0
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -156,10 +166,13 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
BEGIN_FTR_SECTION
cmpldi r10,0x1000
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- rldimi r10,r9,USER_ESID_BITS,0
+ rldimi r10,r9,USER_ESID_BITS,0 /* FIXME!! ? We should do it after srdi ? */
BEGIN_FTR_SECTION
+ srdi r10,r10,40-28 /* get 1T ESID */
+ clrldi r10,r10,(64 - (CONTEXT_BITS + USER_ESID_BITS_1T))
bge slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
+ clrldi r10,r10,(64 - (CONTEXT_BITS + USER_ESID_BITS))
b slb_finish_load
8: /* invalid EA */
@@ -292,7 +305,6 @@ _GLOBAL(slb_compare_rr_to_size)
* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
*/
slb_finish_load_1T:
- srdi r10,r10,40-28 /* get 1T ESID */
ASM_VSID_SCRAMBLE(r10,r9,1T)
/*
* bits above VSID_BITS_1T need to be ignored from r10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-24 8:37 ` Aneesh Kumar K.V
@ 2012-07-24 9:14 ` Aneesh Kumar K.V
2012-07-24 19:50 ` Aneesh Kumar K.V
0 siblings, 1 reply; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-24 9:14 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
> Paul Mackerras <paulus@samba.org> writes:
>
>> On Mon, Jul 23, 2012 at 03:52:05PM +0530, Aneesh Kumar K.V wrote:
>>> Paul Mackerras <paulus@samba.org> writes:
>>>
>>> > On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
>>> >
>>> >> -#define USER_ESID_BITS 16
>>> >> -#define USER_ESID_BITS_1T 4
>>> >> +#define USER_ESID_BITS 18
>>> >> +#define USER_ESID_BITS_1T 6
>>> >
>>> > You also need to change the proto-VSID generation for kernel addresses
>>> > when you do this. If you don't you'll end up with some user processes
>>> > using the same VSIDs as we use for the kernel addresses, meaning that
>>> > those processes won't run very well...
>>> >
>>>
>>> Can you explain this more. right now we generate vsid as below
>>>
>>> vsid_scramble(ea >> SID_SHIFT, 256M) for kernel
>>>
>>> vsid_scramble((context << USER_ESID_BITS) | (ea >> SID_SHIFT), 256M);
>>> for user
>>>
>>> what changes are you suggesting ?
>>
>> Think about it. With the current values of USER_ESID_BITS and
>> CONTEXT_BITS, and the addresses we use for kernel mappings, there are
>> no values of context, user_ea and kernel_ea for which
>>
>> kernel_ea >> SID_SHIFT == (context << USER_ESID_BITS) | (user_ea >> SID_SHIFT)
>>
>> If you increase USER_ESID_BITS, then there will be some context values
>> for which that equation becomes true. For example, if you increase
>> USER_ESID_BITS to 18, then context 0x30000 will generate the same
>> proto-VSIDs as the kernel linear mapping. Since we can hand out
>> contexts up to 0x7ffff (with CONTEXT_BITS = 19), there is a collision.
>>
>> In other words, the proto-VSID space (the space of values that are
>> input to vsid_scramble) is currently divided into two mutually
>> exclusive regions: from 0 to 2^35 - 1 for user processes, and from
>> 2^35 to 2^36 - 1 for kernel addresses. You are wanting to expand the
>> amount of proto-VSID space that user processes can use, but you need
>> either to move the kernel portion of the space, or to make sure that
>> the context allocator doesn't hand out context values that would
>> collide with the kernel portion of the space (or both).
>
> How about this ?. There is a FIXME in there which is not related.
Updated one with both the fixes. Let me know what you think
>From f04a505be381b9c162fa41bda5df4a1a9edfdeb9 Mon Sep 17 00:00:00 2001
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Date: Tue, 24 Jul 2012 14:22:15 +0530
Subject: [PATCH 1/2] arch/powerpc: properly offset the context bits for 1T
segemnts
We should do rldimi r10,r9,USER_ESID_BITS,0 only after populating
r10 with ESID bits.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/slb_low.S | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index db2cb3f..7bd8438 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -59,6 +59,7 @@ _GLOBAL(slb_miss_kernel_load_linear)
BEGIN_FTR_SECTION
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
b slb_finish_load_1T
1:
@@ -88,6 +89,7 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
BEGIN_FTR_SECTION
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -155,13 +157,16 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
ld r9,PACACONTEXTID(r13)
BEGIN_FTR_SECTION
cmpldi r10,0x1000
+ bge 9f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
rldimi r10,r9,USER_ESID_BITS,0
+ b slb_finish_load
BEGIN_FTR_SECTION
- bge slb_finish_load_1T
+9:
+ srdi r10,r10,40-28 /* get 1T ESID */
+ rldimi r10,r9,USER_ESID_BITS,0
+ b slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- b slb_finish_load
-
8: /* invalid EA */
li r10,0 /* BAD_VSID */
li r11,SLB_VSID_USER /* flags don't much matter */
@@ -292,7 +297,6 @@ _GLOBAL(slb_compare_rr_to_size)
* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
*/
slb_finish_load_1T:
- srdi r10,r10,40-28 /* get 1T ESID */
ASM_VSID_SCRAMBLE(r10,r9,1T)
/*
* bits above VSID_BITS_1T need to be ignored from r10
--
1.7.10
>From 43792d9e2c394370c71623f2769d11ff98090918 Mon Sep 17 00:00:00 2001
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Date: Tue, 24 Jul 2012 11:40:29 +0530
Subject: [PATCH 2/2] arch/powerpc: properly isolate kernel and user
proto-VSID
The proto-VSID space is divided into two class
User: 0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
This patch does above isolation
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 32 ++++++++++++++++++++++++--------
arch/powerpc/kernel/exceptions-64s.S | 4 +++-
arch/powerpc/mm/slb_low.S | 10 ++++++++++
3 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index daa3e4b..736df15 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -516,9 +516,19 @@ typedef struct {
/* This is only valid for addresses >= PAGE_OFFSET */
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble(ea >> SID_SHIFT, 256M);
- return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
+ unsigned long proto_vsid;
+ /*
+ * We need to make sure proto_vsid for the kernel is
+ * >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
+ */
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ea >> SID_SHIFT;
+ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ea >> SID_SHIFT_1T;
+ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
+ return vsid_scramble(proto_vsid, 1T);
}
/* Returns the segment size indicator for a user address */
@@ -534,11 +544,17 @@ static inline int user_segment_size(unsigned long addr)
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble((context << USER_ESID_BITS)
- | (ea >> SID_SHIFT), 256M);
- return vsid_scramble((context << USER_ESID_BITS_1T)
- | (ea >> SID_SHIFT_1T), 1T);
+ unsigned long proto_vsid;
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ((context << USER_ESID_BITS) |(ea >> SID_SHIFT));
+ /* truncate this to 37 bits */
+ proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS)) - 1;
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ((context << USER_ESID_BITS_1T) | (ea >> SID_SHIFT_1T));
+ /* truncate this to 25 bits */
+ proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T)) - 1;
+ return vsid_scramble( proto_vsid, 1T);
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 1c06d29..40ed208 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -958,7 +958,9 @@ _GLOBAL(do_stab_bolted)
rldimi r10,r11,7,52 /* r10 = first ste of the group */
/* Calculate VSID */
- /* This is a kernel address, so protovsid = ESID */
+ /* This is a kernel address, so protovsid = ESID | 1 << 37 */
+ li r9,0x1
+ rldimi r11,r9,(CONTEXT_BITS + USER_ESID_BITS),0
ASM_VSID_SCRAMBLE(r11, r9, 256M)
rldic r9,r11,12,16 /* r9 = vsid << 12 */
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 7bd8438..e6bace3 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -57,9 +57,13 @@ _GLOBAL(slb_allocate_realmode)
_GLOBAL(slb_miss_kernel_load_linear)
li r11,0
BEGIN_FTR_SECTION
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
srdi r10,r10,40-28 /* get 1T ESID */
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS_1T),0
b slb_finish_load_1T
1:
@@ -87,9 +91,13 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
li r11,0
6:
BEGIN_FTR_SECTION
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
srdi r10,r10,40-28 /* get 1T ESID */
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS_1T),0
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -160,11 +168,13 @@ BEGIN_FTR_SECTION
bge 9f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
rldimi r10,r9,USER_ESID_BITS,0
+ clrldi r10,r10,(64 - (CONTEXT_BITS + USER_ESID_BITS))
b slb_finish_load
BEGIN_FTR_SECTION
9:
srdi r10,r10,40-28 /* get 1T ESID */
rldimi r10,r9,USER_ESID_BITS,0
+ clrldi r10,r10,(64 - (CONTEXT_BITS + USER_ESID_BITS_1T))
b slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
8: /* invalid EA */
--
1.7.10
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
2012-07-24 9:14 ` Aneesh Kumar K.V
@ 2012-07-24 19:50 ` Aneesh Kumar K.V
0 siblings, 0 replies; 47+ messages in thread
From: Aneesh Kumar K.V @ 2012-07-24 19:50 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
......
> /* Returns the segment size indicator for a user address */
> @@ -534,11 +544,17 @@ static inline int user_segment_size(unsigned long addr)
> static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
> int ssize)
> {
> - if (ssize == MMU_SEGSIZE_256M)
> - return vsid_scramble((context << USER_ESID_BITS)
> - | (ea >> SID_SHIFT), 256M);
> - return vsid_scramble((context << USER_ESID_BITS_1T)
> - | (ea >> SID_SHIFT_1T), 1T);
> + unsigned long proto_vsid;
> + if (ssize == MMU_SEGSIZE_256M) {
> + proto_vsid = ((context << USER_ESID_BITS) |(ea >> SID_SHIFT));
> + /* truncate this to 37 bits */
> + proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS)) - 1;
> + return vsid_scramble(proto_vsid, 256M);
> + }
> + proto_vsid = ((context << USER_ESID_BITS_1T) | (ea >> SID_SHIFT_1T));
> + /* truncate this to 25 bits */
> + proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T)) - 1;
> + return vsid_scramble( proto_vsid, 1T);
> }
I guess we can drop this hunk and related asm, because context is
guaranteed to be <= CONTEXT_BITS (via MAX_CONTEXTS )
-aneesh
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2012-07-24 19:51 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-07-09 13:13 [PATCH -V3 0/11] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 01/11] arch/powerpc: Use hpt_va to compute virtual address Aneesh Kumar K.V
2012-07-22 23:17 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 02/11] arch/powerpc: Simplify hpte_decode Aneesh Kumar K.V
2012-07-22 23:26 ` Paul Mackerras
2012-07-23 5:41 ` Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
2012-07-09 22:41 ` Stephen Rothwell
2012-07-10 6:12 ` Aneesh Kumar K.V
2012-07-09 23:06 ` Stephen Rothwell
2012-07-10 6:15 ` Aneesh Kumar K.V
2012-07-22 23:42 ` Paul Mackerras
2012-07-23 5:54 ` Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 04/11] arch/powerpc: Rename va " Aneesh Kumar K.V
2012-07-22 23:46 ` Paul Mackerras
2012-07-23 6:14 ` Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate Aneesh Kumar K.V
2012-07-22 23:56 ` Paul Mackerras
2012-07-23 1:22 ` Benjamin Herrenschmidt
2012-07-23 3:49 ` Paul Mackerras
2012-07-23 6:44 ` Aneesh Kumar K.V
2012-07-23 6:48 ` Benjamin Herrenschmidt
2012-07-09 13:13 ` [PATCH -V3 06/11] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE Aneesh Kumar K.V
2012-07-22 23:57 ` Paul Mackerras
2012-07-09 13:13 ` [PATCH -V3 07/11] arch/powerpc: Increase the slice range to 64TB Aneesh Kumar K.V
2012-07-23 0:00 ` Paul Mackerras
2012-07-23 7:13 ` Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 08/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit Aneesh Kumar K.V
2012-07-23 0:20 ` Paul Mackerras
2012-07-23 7:29 ` Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte Aneesh Kumar K.V
2012-07-23 0:06 ` Paul Mackerras
2012-07-23 8:21 ` Aneesh Kumar K.V
2012-07-23 9:36 ` Paul Mackerras
2012-07-23 10:22 ` Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 10/11] arch/powerpc: Use 32bit array for slb cache Aneesh Kumar K.V
2012-07-23 0:27 ` Paul Mackerras
2012-07-23 8:25 ` Aneesh Kumar K.V
2012-07-09 13:13 ` [PATCH -V3 11/11] arch/powerpc: Add 64TB support Aneesh Kumar K.V
2012-07-23 0:15 ` Paul Mackerras
2012-07-23 8:49 ` Aneesh Kumar K.V
2012-07-23 9:39 ` Paul Mackerras
2012-07-23 10:22 ` Aneesh Kumar K.V
2012-07-23 11:06 ` Paul Mackerras
2012-07-24 8:37 ` Aneesh Kumar K.V
2012-07-24 9:14 ` Aneesh Kumar K.V
2012-07-24 19:50 ` Aneesh Kumar K.V
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