KVM: PPC: BOOK3S: PR: P8 Support

KVM: PPC: BOOK3S: PR: P8 Support

[Aneesh Kumar K.V]

This patchset adds support for emulating VTB, IC and Doorbell features in P8.
Doorbell support is dummy since we don't support SMT cores with PR-KVM.


-aneesh

[PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Aneesh Kumar K.V]

virtual time base register is a per VM, per cpu register that needs
to be saved and restored on vm exit and entry. Writing to VTB is not
allowed in the privileged mode.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/kvm_host.h |  1 +
 arch/powerpc/include/asm/reg.h      | 15 +++++++++++++++
 arch/powerpc/include/asm/time.h     |  9 +++++++++
 arch/powerpc/kvm/book3s.c           |  6 ++++++
 arch/powerpc/kvm/book3s_emulate.c   |  3 +++
 arch/powerpc/kvm/book3s_hv.c        |  6 ------
 arch/powerpc/kvm/book3s_pr.c        |  3 ++-
 7 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index 4a58731a0a72..bd3caeaeebe1 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -505,6 +505,7 @@ struct kvm_vcpu_arch {
 #endif
 	/* Time base value when we entered the guest */
 	u64 entry_tb;
+	u64 entry_vtb;
 	u32 tcr;
 	ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
 	u32 ivor[64];
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 4852bcf270f3..3e7085d8af90 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -25,6 +25,7 @@
 #ifdef CONFIG_8xx
 #include <asm/reg_8xx.h>
 #endif /* CONFIG_8xx */
+#include <asm/bug.h>
 
 #define MSR_SF_LG	63              /* Enable 64 bit mode */
 #define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
@@ -1193,6 +1194,20 @@
 				     : "r" ((unsigned long)(v)) \
 				     : "memory")
 
+static inline unsigned long mfvtb (void)
+{
+#ifdef CONFIG_PPC_BOOK3S_64
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		return mfspr(SPRN_VTB);
+#endif
+	/*
+	 * The above mfspr will be a no-op on anything before Power8
+	 * That can result in random values returned. We need to
+	 * capture that.
+	 */
+	BUG();
+}
+
 #ifdef __powerpc64__
 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
 #define mftb()		({unsigned long rval;				\
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index 1d428e6007ca..03cbada59d3a 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -102,6 +102,15 @@ static inline u64 get_rtc(void)
 	return (u64)hi * 1000000000 + lo;
 }
 
+static inline u64 get_vtb(void)
+{
+#ifdef CONFIG_PPC_BOOK3S_64
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		return mfvtb();
+#endif
+	return 0;
+}
+
 #ifdef CONFIG_PPC64
 static inline u64 get_tb(void)
 {
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 52c654dbd41a..ae43e4178ecd 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -646,6 +646,9 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 		case KVM_REG_PPC_BESCR:
 			val = get_reg_val(reg->id, vcpu->arch.bescr);
 			break;
+		case KVM_REG_PPC_VTB:
+			val = get_reg_val(reg->id, vcpu->arch.vtb);
+			break;
 		default:
 			r = -EINVAL;
 			break;
@@ -750,6 +753,9 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 		case KVM_REG_PPC_BESCR:
 			vcpu->arch.bescr = set_reg_val(reg->id, val);
 			break;
+		case KVM_REG_PPC_VTB:
+			vcpu->arch.vtb = set_reg_val(reg->id, val);
+			break;
 		default:
 			r = -EINVAL;
 			break;
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 3565e775b61b..1bb16a59dcbc 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -577,6 +577,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 		 */
 		*spr_val = vcpu->arch.spurr;
 		break;
+	case SPRN_VTB:
+		*spr_val = vcpu->arch.vtb;
+		break;
 	case SPRN_GQR0:
 	case SPRN_GQR1:
 	case SPRN_GQR2:
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index aba05bbb3e74..f6ac58336b3f 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -897,9 +897,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_IC:
 		*val = get_reg_val(id, vcpu->arch.ic);
 		break;
-	case KVM_REG_PPC_VTB:
-		*val = get_reg_val(id, vcpu->arch.vtb);
-		break;
 	case KVM_REG_PPC_CSIGR:
 		*val = get_reg_val(id, vcpu->arch.csigr);
 		break;
@@ -1097,9 +1094,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_IC:
 		vcpu->arch.ic = set_reg_val(id, *val);
 		break;
-	case KVM_REG_PPC_VTB:
-		vcpu->arch.vtb = set_reg_val(id, *val);
-		break;
 	case KVM_REG_PPC_CSIGR:
 		vcpu->arch.csigr = set_reg_val(id, *val);
 		break;
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index ff15f8e31a27..96cdf89a8c86 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -125,6 +125,7 @@ void kvmppc_copy_to_svcpu(struct kvmppc_book3s_shadow_vcpu *svcpu,
 	 * to find the guest purr and spurr value.
 	 */
 	vcpu->arch.entry_tb = get_tb();
+	vcpu->arch.entry_vtb = get_vtb();
 	svcpu->in_use = true;
 }
 
@@ -176,7 +177,7 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu,
 	 */
 	vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb;
 	vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb;
-
+	vcpu->arch.vtb += get_vtb() - vcpu->arch.entry_vtb;
 	svcpu->in_use = false;
 
 out:
-- 
1.9.1

[PATCH 2/4] KVM: PPC: BOOK3S: PR: Doorbell support

[Aneesh Kumar K.V]

We don't have SMT support yet, hence we should not find a doorbell
message generated

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/kvm/book3s_emulate.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 1bb16a59dcbc..d6c87d085182 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -28,7 +28,9 @@
 #define OP_19_XOP_RFI		50
 
 #define OP_31_XOP_MFMSR		83
+#define OP_31_XOP_MSGSNDP	142
 #define OP_31_XOP_MTMSR		146
+#define OP_31_XOP_MSGCLRP	174
 #define OP_31_XOP_MTMSRD	178
 #define OP_31_XOP_MTSR		210
 #define OP_31_XOP_MTSRIN	242
@@ -303,6 +305,22 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu,
 
 			break;
 		}
+		case OP_31_XOP_MSGSNDP:
+		{
+			/*
+			 * PR KVM still don't support SMT mode. So we should
+			 * not see a MSGSNDP/MSGCLRP used with PR KVM
+			 */
+			pr_info("KVM: MSGSNDP used in non SMT case\n");
+			emulated = EMULATE_FAIL;
+			break;
+		}
+		case OP_31_XOP_MSGCLRP:
+		{
+			pr_info("KVM: MSGCLRP used in non SMT case\n");
+			emulated = EMULATE_FAIL;
+			break;
+		}
 		default:
 			emulated = EMULATE_FAIL;
 		}
-- 
1.9.1

[PATCH 3/4] KVM: PPC: BOOK3S: PR: Emulate DPDES register

[Aneesh Kumar K.V]

Since we don't support SMT yet, we should always find zero in
Directed privileged doorbell exception state register.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/kvm/book3s_emulate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index d6c87d085182..062b5da7786e 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -655,6 +655,7 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 	case SPRN_MMCR1:
 	case SPRN_MMCR2:
 	case SPRN_TIR:
+	case SPRN_DPDES:
 #endif
 		*spr_val = 0;
 		break;
-- 
1.9.1

[PATCH 4/4] KVM: PPC: BOOK3S: PR: Emulate instruction counter

[Aneesh Kumar K.V]

Writing to IC is not allowed in the privileged mode.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/kvm_host.h | 1 +
 arch/powerpc/kvm/book3s.c           | 6 ++++++
 arch/powerpc/kvm/book3s_emulate.c   | 3 +++
 arch/powerpc/kvm/book3s_hv.c        | 6 ------
 arch/powerpc/kvm/book3s_pr.c        | 4 ++++
 5 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index bd3caeaeebe1..f9ae69682ce1 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -506,6 +506,7 @@ struct kvm_vcpu_arch {
 	/* Time base value when we entered the guest */
 	u64 entry_tb;
 	u64 entry_vtb;
+	u64 entry_ic;
 	u32 tcr;
 	ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
 	u32 ivor[64];
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index ae43e4178ecd..52c4c43900cb 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -649,6 +649,9 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 		case KVM_REG_PPC_VTB:
 			val = get_reg_val(reg->id, vcpu->arch.vtb);
 			break;
+		case KVM_REG_PPC_IC:
+			val = get_reg_val(reg->id, vcpu->arch.ic);
+			break;
 		default:
 			r = -EINVAL;
 			break;
@@ -756,6 +759,9 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 		case KVM_REG_PPC_VTB:
 			vcpu->arch.vtb = set_reg_val(reg->id, val);
 			break;
+		case KVM_REG_PPC_IC:
+			vcpu->arch.ic = set_reg_val(reg->id, val);
+			break;
 		default:
 			r = -EINVAL;
 			break;
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 062b5da7786e..e6912c618160 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -598,6 +598,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
 	case SPRN_VTB:
 		*spr_val = vcpu->arch.vtb;
 		break;
+	case SPRN_IC:
+		*spr_val = vcpu->arch.ic;
+		break;
 	case SPRN_GQR0:
 	case SPRN_GQR1:
 	case SPRN_GQR2:
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index f6ac58336b3f..c38cf9f836c0 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -894,9 +894,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 	case KVM_REG_PPC_CIABR:
 		*val = get_reg_val(id, vcpu->arch.ciabr);
 		break;
-	case KVM_REG_PPC_IC:
-		*val = get_reg_val(id, vcpu->arch.ic);
-		break;
 	case KVM_REG_PPC_CSIGR:
 		*val = get_reg_val(id, vcpu->arch.csigr);
 		break;
@@ -1091,9 +1088,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
 		if ((vcpu->arch.ciabr & CIABR_PRIV) == CIABR_PRIV_HYPER)
 			vcpu->arch.ciabr &= ~CIABR_PRIV;	/* disable */
 		break;
-	case KVM_REG_PPC_IC:
-		vcpu->arch.ic = set_reg_val(id, *val);
-		break;
 	case KVM_REG_PPC_CSIGR:
 		vcpu->arch.csigr = set_reg_val(id, *val);
 		break;
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 96cdf89a8c86..03fc8847cd67 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -126,6 +126,8 @@ void kvmppc_copy_to_svcpu(struct kvmppc_book3s_shadow_vcpu *svcpu,
 	 */
 	vcpu->arch.entry_tb = get_tb();
 	vcpu->arch.entry_vtb = get_vtb();
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		vcpu->arch.entry_ic = mfspr(SPRN_IC);
 	svcpu->in_use = true;
 }
 
@@ -178,6 +180,8 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu,
 	vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb;
 	vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb;
 	vcpu->arch.vtb += get_vtb() - vcpu->arch.entry_vtb;
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		vcpu->arch.ic += mfspr(SPRN_IC) - vcpu->arch.entry_ic;
 	svcpu->in_use = false;
 
 out:
-- 
1.9.1

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Alexander Graf]

On 05.06.14 14:08, Aneesh Kumar K.V wrote:
> virtual time base register is a per VM, per cpu register that needs
> to be saved and restored on vm exit and entry. Writing to VTB is not
> allowed in the privileged mode.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>   arch/powerpc/include/asm/kvm_host.h |  1 +
>   arch/powerpc/include/asm/reg.h      | 15 +++++++++++++++
>   arch/powerpc/include/asm/time.h     |  9 +++++++++
>   arch/powerpc/kvm/book3s.c           |  6 ++++++
>   arch/powerpc/kvm/book3s_emulate.c   |  3 +++
>   arch/powerpc/kvm/book3s_hv.c        |  6 ------
>   arch/powerpc/kvm/book3s_pr.c        |  3 ++-
>   7 files changed, 36 insertions(+), 7 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
> index 4a58731a0a72..bd3caeaeebe1 100644
> --- a/arch/powerpc/include/asm/kvm_host.h
> +++ b/arch/powerpc/include/asm/kvm_host.h
> @@ -505,6 +505,7 @@ struct kvm_vcpu_arch {
>   #endif
>   	/* Time base value when we entered the guest */
>   	u64 entry_tb;
> +	u64 entry_vtb;
>   	u32 tcr;
>   	ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
>   	u32 ivor[64];
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 4852bcf270f3..3e7085d8af90 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -25,6 +25,7 @@
>   #ifdef CONFIG_8xx
>   #include <asm/reg_8xx.h>
>   #endif /* CONFIG_8xx */
> +#include <asm/bug.h>
>   
>   #define MSR_SF_LG	63              /* Enable 64 bit mode */
>   #define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
> @@ -1193,6 +1194,20 @@
>   				     : "r" ((unsigned long)(v)) \
>   				     : "memory")
>   
> +static inline unsigned long mfvtb (void)
> +{
> +#ifdef CONFIG_PPC_BOOK3S_64
> +	if (cpu_has_feature(CPU_FTR_ARCH_207S))
> +		return mfspr(SPRN_VTB);
> +#endif
> +	/*
> +	 * The above mfspr will be a no-op on anything before Power8
> +	 * That can result in random values returned. We need to
> +	 * capture that.
> +	 */
> +	BUG();
> +}
> +
>   #ifdef __powerpc64__
>   #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
>   #define mftb()		({unsigned long rval;				\
> diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
> index 1d428e6007ca..03cbada59d3a 100644
> --- a/arch/powerpc/include/asm/time.h
> +++ b/arch/powerpc/include/asm/time.h
> @@ -102,6 +102,15 @@ static inline u64 get_rtc(void)
>   	return (u64)hi * 1000000000 + lo;
>   }
>   
> +static inline u64 get_vtb(void)
> +{
> +#ifdef CONFIG_PPC_BOOK3S_64
> +	if (cpu_has_feature(CPU_FTR_ARCH_207S))
> +		return mfvtb();
> +#endif
> +	return 0;
> +}
> +
>   #ifdef CONFIG_PPC64
>   static inline u64 get_tb(void)
>   {
> diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
> index 52c654dbd41a..ae43e4178ecd 100644
> --- a/arch/powerpc/kvm/book3s.c
> +++ b/arch/powerpc/kvm/book3s.c
> @@ -646,6 +646,9 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
>   		case KVM_REG_PPC_BESCR:
>   			val = get_reg_val(reg->id, vcpu->arch.bescr);
>   			break;
> +		case KVM_REG_PPC_VTB:
> +			val = get_reg_val(reg->id, vcpu->arch.vtb);
> +			break;
>   		default:
>   			r = -EINVAL;
>   			break;
> @@ -750,6 +753,9 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
>   		case KVM_REG_PPC_BESCR:
>   			vcpu->arch.bescr = set_reg_val(reg->id, val);
>   			break;
> +		case KVM_REG_PPC_VTB:
> +			vcpu->arch.vtb = set_reg_val(reg->id, val);
> +			break;
>   		default:
>   			r = -EINVAL;
>   			break;
> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
> index 3565e775b61b..1bb16a59dcbc 100644
> --- a/arch/powerpc/kvm/book3s_emulate.c
> +++ b/arch/powerpc/kvm/book3s_emulate.c
> @@ -577,6 +577,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
>   		 */
>   		*spr_val = vcpu->arch.spurr;
>   		break;
> +	case SPRN_VTB:
> +		*spr_val = vcpu->arch.vtb;

Doesn't this mean that vtb can be the same 2 when the guest reads it 2 
times in a row without getting preempted?


Alex

> +		break;
>   	case SPRN_GQR0:
>   	case SPRN_GQR1:
>   	case SPRN_GQR2:
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index aba05bbb3e74..f6ac58336b3f 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -897,9 +897,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
>   	case KVM_REG_PPC_IC:
>   		*val = get_reg_val(id, vcpu->arch.ic);
>   		break;
> -	case KVM_REG_PPC_VTB:
> -		*val = get_reg_val(id, vcpu->arch.vtb);
> -		break;
>   	case KVM_REG_PPC_CSIGR:
>   		*val = get_reg_val(id, vcpu->arch.csigr);
>   		break;
> @@ -1097,9 +1094,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
>   	case KVM_REG_PPC_IC:
>   		vcpu->arch.ic = set_reg_val(id, *val);
>   		break;
> -	case KVM_REG_PPC_VTB:
> -		vcpu->arch.vtb = set_reg_val(id, *val);
> -		break;
>   	case KVM_REG_PPC_CSIGR:
>   		vcpu->arch.csigr = set_reg_val(id, *val);
>   		break;
> diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
> index ff15f8e31a27..96cdf89a8c86 100644
> --- a/arch/powerpc/kvm/book3s_pr.c
> +++ b/arch/powerpc/kvm/book3s_pr.c
> @@ -125,6 +125,7 @@ void kvmppc_copy_to_svcpu(struct kvmppc_book3s_shadow_vcpu *svcpu,
>   	 * to find the guest purr and spurr value.
>   	 */
>   	vcpu->arch.entry_tb = get_tb();
> +	vcpu->arch.entry_vtb = get_vtb();
>   	svcpu->in_use = true;
>   }
>   
> @@ -176,7 +177,7 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu,
>   	 */
>   	vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb;
>   	vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb;
> -
> +	vcpu->arch.vtb += get_vtb() - vcpu->arch.entry_vtb;
>   	svcpu->in_use = false;
>   
>   out:

Re: [PATCH 2/4] KVM: PPC: BOOK3S: PR: Doorbell support

[Alexander Graf]

On 05.06.14 14:08, Aneesh Kumar K.V wrote:
> We don't have SMT support yet, hence we should not find a doorbell
> message generated
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>   arch/powerpc/kvm/book3s_emulate.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
>
> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
> index 1bb16a59dcbc..d6c87d085182 100644
> --- a/arch/powerpc/kvm/book3s_emulate.c
> +++ b/arch/powerpc/kvm/book3s_emulate.c
> @@ -28,7 +28,9 @@
>   #define OP_19_XOP_RFI		50
>   
>   #define OP_31_XOP_MFMSR		83
> +#define OP_31_XOP_MSGSNDP	142
>   #define OP_31_XOP_MTMSR		146
> +#define OP_31_XOP_MSGCLRP	174
>   #define OP_31_XOP_MTMSRD	178
>   #define OP_31_XOP_MTSR		210
>   #define OP_31_XOP_MTSRIN	242
> @@ -303,6 +305,22 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu,
>   
>   			break;
>   		}
> +		case OP_31_XOP_MSGSNDP:
> +		{
> +			/*
> +			 * PR KVM still don't support SMT mode. So we should

still?

> +			 * not see a MSGSNDP/MSGCLRP used with PR KVM
> +			 */
> +			pr_info("KVM: MSGSNDP used in non SMT case\n");
> +			emulated = EMULATE_FAIL;

What would happen on an HV guest with only 1 thread that MSGSNDs to 
thread 0? Would the guest get an illegal instruction trap, a 
self-interrupt or would this be a simple nop?


Alex

> +			break;
> +		}
> +		case OP_31_XOP_MSGCLRP:
> +		{
> +			pr_info("KVM: MSGCLRP used in non SMT case\n");
> +			emulated = EMULATE_FAIL;
> +			break;
> +		}
>   		default:
>   			emulated = EMULATE_FAIL;
>   		}

Re: [PATCH 2/4] KVM: PPC: BOOK3S: PR: Doorbell support

[Alexander Graf]

On 05.06.14 14:21, Alexander Graf wrote:
>
> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>> We don't have SMT support yet, hence we should not find a doorbell
>> message generated
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>>   arch/powerpc/kvm/book3s_emulate.c | 18 ++++++++++++++++++
>>   1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/powerpc/kvm/book3s_emulate.c 
>> b/arch/powerpc/kvm/book3s_emulate.c
>> index 1bb16a59dcbc..d6c87d085182 100644
>> --- a/arch/powerpc/kvm/book3s_emulate.c
>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>> @@ -28,7 +28,9 @@
>>   #define OP_19_XOP_RFI        50
>>     #define OP_31_XOP_MFMSR        83
>> +#define OP_31_XOP_MSGSNDP    142
>>   #define OP_31_XOP_MTMSR        146
>> +#define OP_31_XOP_MSGCLRP    174
>>   #define OP_31_XOP_MTMSRD    178
>>   #define OP_31_XOP_MTSR        210
>>   #define OP_31_XOP_MTSRIN    242
>> @@ -303,6 +305,22 @@ int kvmppc_core_emulate_op_pr(struct kvm_run 
>> *run, struct kvm_vcpu *vcpu,
>>                 break;
>>           }
>> +        case OP_31_XOP_MSGSNDP:
>> +        {
>> +            /*
>> +             * PR KVM still don't support SMT mode. So we should
>
> still?
>
>> +             * not see a MSGSNDP/MSGCLRP used with PR KVM
>> +             */
>> +            pr_info("KVM: MSGSNDP used in non SMT case\n");
>> +            emulated = EMULATE_FAIL;
>
> What would happen on an HV guest with only 1 thread that MSGSNDs to 
> thread 0? Would the guest get an illegal instruction trap, a 
> self-interrupt or would this be a simple nop?

What I'm trying to say here is that it's ok to treat it as illegal 
instructions, but then we don't need this patch :).


Alex

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Aneesh Kumar K.V]

Alexander Graf <agraf@suse.de> writes:

> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>> virtual time base register is a per VM, per cpu register that needs
>> to be saved and restored on vm exit and entry. Writing to VTB is not
>> allowed in the privileged mode.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>>   arch/powerpc/include/asm/kvm_host.h |  1 +
>>   arch/powerpc/include/asm/reg.h      | 15 +++++++++++++++
>>   arch/powerpc/include/asm/time.h     |  9 +++++++++
>>   arch/powerpc/kvm/book3s.c           |  6 ++++++
>>   arch/powerpc/kvm/book3s_emulate.c   |  3 +++
>>   arch/powerpc/kvm/book3s_hv.c        |  6 ------
>>   arch/powerpc/kvm/book3s_pr.c        |  3 ++-
>>   7 files changed, 36 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
>> index 4a58731a0a72..bd3caeaeebe1 100644
>> --- a/arch/powerpc/include/asm/kvm_host.h
>> +++ b/arch/powerpc/include/asm/kvm_host.h
>> @@ -505,6 +505,7 @@ struct kvm_vcpu_arch {
>>   #endif
>>   	/* Time base value when we entered the guest */
>>   	u64 entry_tb;
>> +	u64 entry_vtb;
>>   	u32 tcr;
>>   	ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
>>   	u32 ivor[64];
>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
>> index 4852bcf270f3..3e7085d8af90 100644
>> --- a/arch/powerpc/include/asm/reg.h
>> +++ b/arch/powerpc/include/asm/reg.h
>> @@ -25,6 +25,7 @@
>>   #ifdef CONFIG_8xx
>>   #include <asm/reg_8xx.h>
>>   #endif /* CONFIG_8xx */
>> +#include <asm/bug.h>
>>   
>>   #define MSR_SF_LG	63              /* Enable 64 bit mode */
>>   #define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
>> @@ -1193,6 +1194,20 @@
>>   				     : "r" ((unsigned long)(v)) \
>>   				     : "memory")
>>   
>> +static inline unsigned long mfvtb (void)
>> +{
>> +#ifdef CONFIG_PPC_BOOK3S_64
>> +	if (cpu_has_feature(CPU_FTR_ARCH_207S))
>> +		return mfspr(SPRN_VTB);
>> +#endif
>> +	/*
>> +	 * The above mfspr will be a no-op on anything before Power8
>> +	 * That can result in random values returned. We need to
>> +	 * capture that.
>> +	 */
>> +	BUG();
>> +}
>> +
>>   #ifdef __powerpc64__
>>   #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
>>   #define mftb()		({unsigned long rval;				\
>> diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
>> index 1d428e6007ca..03cbada59d3a 100644
>> --- a/arch/powerpc/include/asm/time.h
>> +++ b/arch/powerpc/include/asm/time.h
>> @@ -102,6 +102,15 @@ static inline u64 get_rtc(void)
>>   	return (u64)hi * 1000000000 + lo;
>>   }
>>   
>> +static inline u64 get_vtb(void)
>> +{
>> +#ifdef CONFIG_PPC_BOOK3S_64
>> +	if (cpu_has_feature(CPU_FTR_ARCH_207S))
>> +		return mfvtb();
>> +#endif
>> +	return 0;
>> +}
>> +
>>   #ifdef CONFIG_PPC64
>>   static inline u64 get_tb(void)
>>   {
>> diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
>> index 52c654dbd41a..ae43e4178ecd 100644
>> --- a/arch/powerpc/kvm/book3s.c
>> +++ b/arch/powerpc/kvm/book3s.c
>> @@ -646,6 +646,9 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
>>   		case KVM_REG_PPC_BESCR:
>>   			val = get_reg_val(reg->id, vcpu->arch.bescr);
>>   			break;
>> +		case KVM_REG_PPC_VTB:
>> +			val = get_reg_val(reg->id, vcpu->arch.vtb);
>> +			break;
>>   		default:
>>   			r = -EINVAL;
>>   			break;
>> @@ -750,6 +753,9 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
>>   		case KVM_REG_PPC_BESCR:
>>   			vcpu->arch.bescr = set_reg_val(reg->id, val);
>>   			break;
>> +		case KVM_REG_PPC_VTB:
>> +			vcpu->arch.vtb = set_reg_val(reg->id, val);
>> +			break;
>>   		default:
>>   			r = -EINVAL;
>>   			break;
>> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
>> index 3565e775b61b..1bb16a59dcbc 100644
>> --- a/arch/powerpc/kvm/book3s_emulate.c
>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>> @@ -577,6 +577,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
>>   		 */
>>   		*spr_val = vcpu->arch.spurr;
>>   		break;
>> +	case SPRN_VTB:
>> +		*spr_val = vcpu->arch.vtb;
>
> Doesn't this mean that vtb can be the same 2 when the guest reads it 2 
> times in a row without getting preempted?


But a mfspr will result in VM exit and that would make sure we
update vcpu->arch.vtb with the correct value.


-aneesh

Re: [PATCH 2/4] KVM: PPC: BOOK3S: PR: Doorbell support

[Aneesh Kumar K.V]

Alexander Graf <agraf@suse.de> writes:

> On 05.06.14 14:21, Alexander Graf wrote:
>>
>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>> We don't have SMT support yet, hence we should not find a doorbell
>>> message generated
>>>
>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>>> ---
>>>   arch/powerpc/kvm/book3s_emulate.c | 18 ++++++++++++++++++
>>>   1 file changed, 18 insertions(+)
>>>
>>> diff --git a/arch/powerpc/kvm/book3s_emulate.c 
>>> b/arch/powerpc/kvm/book3s_emulate.c
>>> index 1bb16a59dcbc..d6c87d085182 100644
>>> --- a/arch/powerpc/kvm/book3s_emulate.c
>>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>>> @@ -28,7 +28,9 @@
>>>   #define OP_19_XOP_RFI        50
>>>     #define OP_31_XOP_MFMSR        83
>>> +#define OP_31_XOP_MSGSNDP    142
>>>   #define OP_31_XOP_MTMSR        146
>>> +#define OP_31_XOP_MSGCLRP    174
>>>   #define OP_31_XOP_MTMSRD    178
>>>   #define OP_31_XOP_MTSR        210
>>>   #define OP_31_XOP_MTSRIN    242
>>> @@ -303,6 +305,22 @@ int kvmppc_core_emulate_op_pr(struct kvm_run 
>>> *run, struct kvm_vcpu *vcpu,
>>>                 break;
>>>           }
>>> +        case OP_31_XOP_MSGSNDP:
>>> +        {
>>> +            /*
>>> +             * PR KVM still don't support SMT mode. So we should
>>
>> still?
>>
>>> +             * not see a MSGSNDP/MSGCLRP used with PR KVM
>>> +             */
>>> +            pr_info("KVM: MSGSNDP used in non SMT case\n");
>>> +            emulated = EMULATE_FAIL;
>>
>> What would happen on an HV guest with only 1 thread that MSGSNDs to 
>> thread 0? Would the guest get an illegal instruction trap, a 
>> self-interrupt or would this be a simple nop?
>
> What I'm trying to say here is that it's ok to treat it as illegal 
> instructions, but then we don't need this patch :).
>

Agreed. I will verify whether it is treated as a nop. If so will send an
updated patch.

-aneesh

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Alexander Graf]

On 05.06.14 17:50, Aneesh Kumar K.V wrote:
> Alexander Graf <agraf@suse.de> writes:
>
>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>> virtual time base register is a per VM, per cpu register that needs
>>> to be saved and restored on vm exit and entry. Writing to VTB is not
>>> allowed in the privileged mode.
>>>
>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>>> ---
>>>    arch/powerpc/include/asm/kvm_host.h |  1 +
>>>    arch/powerpc/include/asm/reg.h      | 15 +++++++++++++++
>>>    arch/powerpc/include/asm/time.h     |  9 +++++++++
>>>    arch/powerpc/kvm/book3s.c           |  6 ++++++
>>>    arch/powerpc/kvm/book3s_emulate.c   |  3 +++
>>>    arch/powerpc/kvm/book3s_hv.c        |  6 ------
>>>    arch/powerpc/kvm/book3s_pr.c        |  3 ++-
>>>    7 files changed, 36 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
>>> index 4a58731a0a72..bd3caeaeebe1 100644
>>> --- a/arch/powerpc/include/asm/kvm_host.h
>>> +++ b/arch/powerpc/include/asm/kvm_host.h
>>> @@ -505,6 +505,7 @@ struct kvm_vcpu_arch {
>>>    #endif
>>>    	/* Time base value when we entered the guest */
>>>    	u64 entry_tb;
>>> +	u64 entry_vtb;
>>>    	u32 tcr;
>>>    	ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
>>>    	u32 ivor[64];
>>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
>>> index 4852bcf270f3..3e7085d8af90 100644
>>> --- a/arch/powerpc/include/asm/reg.h
>>> +++ b/arch/powerpc/include/asm/reg.h
>>> @@ -25,6 +25,7 @@
>>>    #ifdef CONFIG_8xx
>>>    #include <asm/reg_8xx.h>
>>>    #endif /* CONFIG_8xx */
>>> +#include <asm/bug.h>
>>>    
>>>    #define MSR_SF_LG	63              /* Enable 64 bit mode */
>>>    #define MSR_ISF_LG	61              /* Interrupt 64b mode valid on 630 */
>>> @@ -1193,6 +1194,20 @@
>>>    				     : "r" ((unsigned long)(v)) \
>>>    				     : "memory")
>>>    
>>> +static inline unsigned long mfvtb (void)
>>> +{
>>> +#ifdef CONFIG_PPC_BOOK3S_64
>>> +	if (cpu_has_feature(CPU_FTR_ARCH_207S))
>>> +		return mfspr(SPRN_VTB);
>>> +#endif
>>> +	/*
>>> +	 * The above mfspr will be a no-op on anything before Power8
>>> +	 * That can result in random values returned. We need to
>>> +	 * capture that.
>>> +	 */
>>> +	BUG();
>>> +}
>>> +
>>>    #ifdef __powerpc64__
>>>    #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
>>>    #define mftb()		({unsigned long rval;				\
>>> diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
>>> index 1d428e6007ca..03cbada59d3a 100644
>>> --- a/arch/powerpc/include/asm/time.h
>>> +++ b/arch/powerpc/include/asm/time.h
>>> @@ -102,6 +102,15 @@ static inline u64 get_rtc(void)
>>>    	return (u64)hi * 1000000000 + lo;
>>>    }
>>>    
>>> +static inline u64 get_vtb(void)
>>> +{
>>> +#ifdef CONFIG_PPC_BOOK3S_64
>>> +	if (cpu_has_feature(CPU_FTR_ARCH_207S))
>>> +		return mfvtb();
>>> +#endif
>>> +	return 0;
>>> +}
>>> +
>>>    #ifdef CONFIG_PPC64
>>>    static inline u64 get_tb(void)
>>>    {
>>> diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
>>> index 52c654dbd41a..ae43e4178ecd 100644
>>> --- a/arch/powerpc/kvm/book3s.c
>>> +++ b/arch/powerpc/kvm/book3s.c
>>> @@ -646,6 +646,9 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
>>>    		case KVM_REG_PPC_BESCR:
>>>    			val = get_reg_val(reg->id, vcpu->arch.bescr);
>>>    			break;
>>> +		case KVM_REG_PPC_VTB:
>>> +			val = get_reg_val(reg->id, vcpu->arch.vtb);
>>> +			break;
>>>    		default:
>>>    			r = -EINVAL;
>>>    			break;
>>> @@ -750,6 +753,9 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
>>>    		case KVM_REG_PPC_BESCR:
>>>    			vcpu->arch.bescr = set_reg_val(reg->id, val);
>>>    			break;
>>> +		case KVM_REG_PPC_VTB:
>>> +			vcpu->arch.vtb = set_reg_val(reg->id, val);
>>> +			break;
>>>    		default:
>>>    			r = -EINVAL;
>>>    			break;
>>> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
>>> index 3565e775b61b..1bb16a59dcbc 100644
>>> --- a/arch/powerpc/kvm/book3s_emulate.c
>>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>>> @@ -577,6 +577,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
>>>    		 */
>>>    		*spr_val = vcpu->arch.spurr;
>>>    		break;
>>> +	case SPRN_VTB:
>>> +		*spr_val = vcpu->arch.vtb;
>> Doesn't this mean that vtb can be the same 2 when the guest reads it 2
>> times in a row without getting preempted?
>
> But a mfspr will result in VM exit and that would make sure we
> update vcpu->arch.vtb with the correct value.

We only call kvmppc_core_vcpu_put_pr() when we context switch away from 
KVM, so it won't be updated, no?


Alex

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Aneesh Kumar K.V]

Alexander Graf <agraf@suse.de> writes:

> On 05.06.14 17:50, Aneesh Kumar K.V wrote:
>> Alexander Graf <agraf@suse.de> writes:
>>
>>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>>> virtual time base register is a per VM, per cpu register that needs
>>>> to be saved and restored on vm exit and entry. Writing to VTB is not
>>>> allowed in the privileged mode.
>>>>
>>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

.......

>>>>    			break;
>>>> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
>>>> index 3565e775b61b..1bb16a59dcbc 100644
>>>> --- a/arch/powerpc/kvm/book3s_emulate.c
>>>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>>>> @@ -577,6 +577,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
>>>>    		 */
>>>>    		*spr_val = vcpu->arch.spurr;
>>>>    		break;
>>>> +	case SPRN_VTB:
>>>> +		*spr_val = vcpu->arch.vtb;
>>> Doesn't this mean that vtb can be the same 2 when the guest reads it 2
>>> times in a row without getting preempted?
>>
>> But a mfspr will result in VM exit and that would make sure we
>> update vcpu->arch.vtb with the correct value.
>
> We only call kvmppc_core_vcpu_put_pr() when we context switch away from 
> KVM, so it won't be updated, no?
>
>

kvmppc_copy_from_svcpu is also called from VM exit path (book3s_interrupt.S)

-aneesh

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Alexander Graf]

On 05.06.14 19:33, Aneesh Kumar K.V wrote:
> Alexander Graf <agraf@suse.de> writes:
>
>> On 05.06.14 17:50, Aneesh Kumar K.V wrote:
>>> Alexander Graf <agraf@suse.de> writes:
>>>
>>>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>>>> virtual time base register is a per VM, per cpu register that needs
>>>>> to be saved and restored on vm exit and entry. Writing to VTB is not
>>>>> allowed in the privileged mode.
>>>>>
>>>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> .......
>
>>>>>     			break;
>>>>> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
>>>>> index 3565e775b61b..1bb16a59dcbc 100644
>>>>> --- a/arch/powerpc/kvm/book3s_emulate.c
>>>>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>>>>> @@ -577,6 +577,9 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
>>>>>     		 */
>>>>>     		*spr_val = vcpu->arch.spurr;
>>>>>     		break;
>>>>> +	case SPRN_VTB:
>>>>> +		*spr_val = vcpu->arch.vtb;
>>>> Doesn't this mean that vtb can be the same 2 when the guest reads it 2
>>>> times in a row without getting preempted?
>>> But a mfspr will result in VM exit and that would make sure we
>>> update vcpu->arch.vtb with the correct value.
>> We only call kvmppc_core_vcpu_put_pr() when we context switch away from
>> KVM, so it won't be updated, no?
>>
>>
> kvmppc_copy_from_svcpu is also called from VM exit path (book3s_interrupt.S)

... where it will run into this code path:

         /*
          * Maybe we were already preempted and synced the svcpu from
          * our preempt notifiers. Don't bother touching this svcpu then.
          */
         if (!svcpu->in_use)
                 goto out;


Alex

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Alexander Graf]

On 06.06.14 00:32, Alexander Graf wrote:
>
> On 05.06.14 19:33, Aneesh Kumar K.V wrote:
>> Alexander Graf <agraf@suse.de> writes:
>>
>>> On 05.06.14 17:50, Aneesh Kumar K.V wrote:
>>>> Alexander Graf <agraf@suse.de> writes:
>>>>
>>>>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>>>>> virtual time base register is a per VM, per cpu register that needs
>>>>>> to be saved and restored on vm exit and entry. Writing to VTB is not
>>>>>> allowed in the privileged mode.
>>>>>>
>>>>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> .......
>>
>>>>>>                 break;
>>>>>> diff --git a/arch/powerpc/kvm/book3s_emulate.c 
>>>>>> b/arch/powerpc/kvm/book3s_emulate.c
>>>>>> index 3565e775b61b..1bb16a59dcbc 100644
>>>>>> --- a/arch/powerpc/kvm/book3s_emulate.c
>>>>>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>>>>>> @@ -577,6 +577,9 @@ int kvmppc_core_emulate_mfspr_pr(struct 
>>>>>> kvm_vcpu *vcpu, int sprn, ulong *spr_val
>>>>>>              */
>>>>>>             *spr_val = vcpu->arch.spurr;
>>>>>>             break;
>>>>>> +    case SPRN_VTB:
>>>>>> +        *spr_val = vcpu->arch.vtb;
>>>>> Doesn't this mean that vtb can be the same 2 when the guest reads 
>>>>> it 2
>>>>> times in a row without getting preempted?
>>>> But a mfspr will result in VM exit and that would make sure we
>>>> update vcpu->arch.vtb with the correct value.
>>> We only call kvmppc_core_vcpu_put_pr() when we context switch away from
>>> KVM, so it won't be updated, no?
>>>
>>>
>> kvmppc_copy_from_svcpu is also called from VM exit path 
>> (book3s_interrupt.S)
>
> ... where it will run into this code path:
>
>         /*
>          * Maybe we were already preempted and synced the svcpu from
>          * our preempt notifiers. Don't bother touching this svcpu then.
>          */
>         if (!svcpu->in_use)
>                 goto out;

Scratch that. We're always calling this on entry/exit, so you're right.


Alex

Re: [PATCH 2/4] KVM: PPC: BOOK3S: PR: Doorbell support

[Aneesh Kumar K.V]

Alexander Graf <agraf@suse.de> writes:

> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>> We don't have SMT support yet, hence we should not find a doorbell
>> message generated
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>>   arch/powerpc/kvm/book3s_emulate.c | 18 ++++++++++++++++++
>>   1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
>> index 1bb16a59dcbc..d6c87d085182 100644
>> --- a/arch/powerpc/kvm/book3s_emulate.c
>> +++ b/arch/powerpc/kvm/book3s_emulate.c
>> @@ -28,7 +28,9 @@
>>   #define OP_19_XOP_RFI		50
>>   
>>   #define OP_31_XOP_MFMSR		83
>> +#define OP_31_XOP_MSGSNDP	142
>>   #define OP_31_XOP_MTMSR		146
>> +#define OP_31_XOP_MSGCLRP	174
>>   #define OP_31_XOP_MTMSRD	178
>>   #define OP_31_XOP_MTSR		210
>>   #define OP_31_XOP_MTSRIN	242
>> @@ -303,6 +305,22 @@ int kvmppc_core_emulate_op_pr(struct kvm_run *run, struct kvm_vcpu *vcpu,
>>   
>>   			break;
>>   		}
>> +		case OP_31_XOP_MSGSNDP:
>> +		{
>> +			/*
>> +			 * PR KVM still don't support SMT mode. So we should
>
> still?
>
>> +			 * not see a MSGSNDP/MSGCLRP used with PR KVM
>> +			 */
>> +			pr_info("KVM: MSGSNDP used in non SMT case\n");
>> +			emulated = EMULATE_FAIL;
>
> What would happen on an HV guest with only 1 thread that MSGSNDs to 
> thread 0? Would the guest get an illegal instruction trap, a 
> self-interrupt or would this be a simple nop?
>

We do get a self-interrupt. I tried the below

tag = mfspr(SPRN_TIR) & 0x7f;
ppc_msgsnd(5, 0, tag);

And that results in doorbell exception. That implies we will have to
have full implementation of doorbell. You can drop patch 2 and 3 from
this series. I will rework them.

NOTE: This is not an issue for Linux guest, because we don't send ipi
to self. But to complete the emulation of msgsndp we will need to
emulate it properly.

-aneesh

Re: KVM: PPC: BOOK3S: PR: P8 Support

[Alexander Graf]

On 05.06.14 14:08, Aneesh Kumar K.V wrote:
> This patchset adds support for emulating VTB, IC and Doorbell features in P8.
> Doorbell support is dummy since we don't support SMT cores with PR-KVM.

Thanks, applied patches 1 and 4 to kvm-ppc-queue.


Alex

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Alexander Graf]

On 05.06.14 14:08, Aneesh Kumar K.V wrote:
> virtual time base register is a per VM, per cpu register that needs
> to be saved and restored on vm exit and entry. Writing to VTB is not
> allowed in the privileged mode.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

For some reason BUG() doesn't always trigger the "execution stops here" 
logic in gcc. So I've squashed this patch into yours.


Alex


diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 3e7085d..99de6ad 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1206,6 +1206,7 @@ static inline unsigned long mfvtb (void)
       * capture that.
       */
      BUG();
+    return 0;
  }

  #ifdef __powerpc64__

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Aneesh Kumar K.V]

Alexander Graf <agraf@suse.de> writes:

> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>> virtual time base register is a per VM, per cpu register that needs
>> to be saved and restored on vm exit and entry. Writing to VTB is not
>> allowed in the privileged mode.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> For some reason BUG() doesn't always trigger the "execution stops here" 
> logic in gcc. So I've squashed this patch into yours.
>
>
> Alex
>
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 3e7085d..99de6ad 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -1206,6 +1206,7 @@ static inline unsigned long mfvtb (void)
>        * capture that.
>        */
>       BUG();
> +    return 0;
>   }
>
>   #ifdef __powerpc64__

you can then drop the include header change. ie, 

#include <asm/bug.h>

-aneesh

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Alexander Graf]

On 06.06.14 18:27, Aneesh Kumar K.V wrote:
> Alexander Graf <agraf@suse.de> writes:
>
>> On 05.06.14 14:08, Aneesh Kumar K.V wrote:
>>> virtual time base register is a per VM, per cpu register that needs
>>> to be saved and restored on vm exit and entry. Writing to VTB is not
>>> allowed in the privileged mode.
>>>
>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> For some reason BUG() doesn't always trigger the "execution stops here"
>> logic in gcc. So I've squashed this patch into yours.
>>
>>
>> Alex
>>
>>
>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
>> index 3e7085d..99de6ad 100644
>> --- a/arch/powerpc/include/asm/reg.h
>> +++ b/arch/powerpc/include/asm/reg.h
>> @@ -1206,6 +1206,7 @@ static inline unsigned long mfvtb (void)
>>         * capture that.
>>         */
>>        BUG();
>> +    return 0;
>>    }
>>
>>    #ifdef __powerpc64__
> you can then drop the include header change. ie,
>
> #include <asm/bug.h>

Yeah, things are even worse than I thought. I've eventually squashed the 
following in. a NOP'ed mfspr() won't keep the branch from blr'ing, so 
we'd never hit the BUG() anyway.


Alex

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1f34ef7..c8f3381 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -25,7 +25,6 @@
  #ifdef CONFIG_8xx
  #include <asm/reg_8xx.h>
  #endif /* CONFIG_8xx */
-#include <asm/bug.h>

  #define MSR_SF_LG      63              /* Enable 64 bit mode */
  #define MSR_ISF_LG     61              /* Interrupt 64b mode valid on 
630 */
@@ -1210,12 +1209,6 @@ static inline unsigned long mfvtb (void)
         if (cpu_has_feature(CPU_FTR_ARCH_207S))
                 return mfspr(SPRN_VTB);
  #endif
-       /*
-        * The above mfspr will be a no-op on anything before Power8
-        * That can result in random values returned. We need to
-        * capture that.
-        */
-       BUG();
         return 0;
  }

Re: [PATCH 1/4] KVM: PPC: BOOK3S: PR: Emulate virtual timebase register

[Stewart Smith]

Alexander Graf <agraf@suse.de> writes:
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -25,7 +25,6 @@
>   #ifdef CONFIG_8xx
>   #include <asm/reg_8xx.h>
>   #endif /* CONFIG_8xx */
> -#include <asm/bug.h>
>
>   #define MSR_SF_LG      63              /* Enable 64 bit mode */
>   #define MSR_ISF_LG     61              /* Interrupt 64b mode valid on 
> 630 */
> @@ -1210,12 +1209,6 @@ static inline unsigned long mfvtb (void)
>          if (cpu_has_feature(CPU_FTR_ARCH_207S))
>                  return mfspr(SPRN_VTB);
>   #endif
> -       /*
> -        * The above mfspr will be a no-op on anything before Power8
> -        * That can result in random values returned. We need to
> -        * capture that.
> -        */
> -       BUG();
>          return 0;
>   }

(i missed CCing aneesh on this mail in reply to the build robot, so
inserting the same reply here)

  the only place that calls it also does the cpu_has_feature() check and
  returns 0 ifndef CONFIG_PPC_BOOK3S_64 or !cpu_has_feature().

  Looking get_vtb (the only caller) and the places it's called (as well as
  PowerISA 2.07) I think in the emulation code we're missing invoking the
  "system privileged instruction error handler" as the VTB SPR has spr bit
  0 set to 1 (page 107 of PowerISA 2.07, mfspr docs).

  That being said... any guest sholud do the cpu_has_feature check
  themselves, so this probably isn't an issue in the real world.

  Certainly the host really shouldn't BUG() for what is really a guest
  issue (actually.. this would be a good DoS attack on < Power8 host).

  Reviewed-by: Stewart Smith <stewart@linux.vnet.ibm.com>