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From: Paul Mackerras <paulus@ozlabs.org>
To: kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, linuxppc-dev@ozlabs.org
Subject: [PATCH 12/13] KVM: PPC: Book3S HV: Use stop instruction rather than nap on POWER9
Date: Fri, 18 Nov 2016 18:28:41 +1100	[thread overview]
Message-ID: <1479454122-26994-13-git-send-email-paulus@ozlabs.org> (raw)
In-Reply-To: <1479454122-26994-1-git-send-email-paulus@ozlabs.org>

POWER9 replaces the various power-saving mode instructions on POWER8
(doze, nap, sleep and rvwinkle) with a single "stop" instruction, plus
a register, PSSCR, which controls the depth of the power-saving mode.
This replaces the use of the nap instruction when threads are idle
during guest execution with the stop instruction, and adds code to
set PSSCR to a value which will allow an SMT mode switch while the
thread is idle (given that the core as a whole won't be idle in these
cases).

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
 arch/powerpc/kvm/book3s_hv_rmhandlers.S | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index acae5c3..e9eaff4 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -501,17 +501,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 	cmpwi	r0, 0
 	beq	57f
 	li	r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
-	mfspr	r4, SPRN_LPCR
-	rlwimi	r4, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
-	mtspr	SPRN_LPCR, r4
-	isync
-	std	r0, HSTATE_SCRATCH0(r13)
-	ptesync
-	ld	r0, HSTATE_SCRATCH0(r13)
-1:	cmpd	r0, r0
-	bne	1b
-	nap
-	b	.
+	mfspr	r5, SPRN_LPCR
+	rlwimi	r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
+	b	kvm_nap_sequence
 
 57:	li	r0, 0
 	stbx	r0, r3, r4
@@ -2256,6 +2248,17 @@ BEGIN_FTR_SECTION
 	ori	r5, r5, LPCR_PECEDH
 	rlwimi	r5, r3, 0, LPCR_PECEDP
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+
+kvm_nap_sequence:		/* desired LPCR value in r5 */
+BEGIN_FTR_SECTION
+	/*
+	 * PSSCR bits:	exit criterion = 1 (wakeup based on LPCR at sreset)
+	 *		enable state loss = 1 (allow SMT mode switch)
+	 *		requested level = 0 (just stop dispatching)
+	 */
+	lis	r3, (PSSCR_EC | PSSCR_ESL)@h
+	mtspr	SPRN_PSSCR, r3
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
 	mtspr	SPRN_LPCR,r5
 	isync
 	li	r0, 0
@@ -2264,7 +2267,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 	ld	r0, HSTATE_SCRATCH0(r13)
 1:	cmpd	r0, r0
 	bne	1b
+BEGIN_FTR_SECTION
 	nap
+FTR_SECTION_ELSE
+	PPC_STOP
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
 	b	.
 
 33:	mr	r4, r3
-- 
2.7.4

  parent reply	other threads:[~2016-11-18  7:28 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-18  7:28 [PATCH 00/13] KVM: PPC: Support POWER9 guests Paul Mackerras
2016-11-18  7:28 ` [PATCH 01/13] powerpc/64: Add some more SPRs and SPR bits for POWER9 Paul Mackerras
2016-11-18  7:28 ` [PATCH 02/13] powerpc/64: Provide functions for accessing POWER9 partition table Paul Mackerras
2016-11-18 14:27   ` Aneesh Kumar K.V
2016-11-19  4:19     ` Paul Mackerras
2016-11-19  6:35       ` Aneesh Kumar K.V
2016-11-21  2:14         ` Paul Mackerras
2016-11-19  0:45   ` Balbir Singh
2016-11-19  4:23     ` Paul Mackerras
2016-11-18  7:28 ` [PATCH 03/13] powerpc/powernv: Define real-mode versions of OPAL XICS accessors Paul Mackerras
2016-11-18  7:28 ` [PATCH 04/13] KVM: PPC: Book3S HV: Don't lose hardware R/C bit updates in H_PROTECT Paul Mackerras
2016-11-18  7:28 ` [PATCH 05/13] KVM: PPC: Book3S HV: Adapt to new HPTE format on POWER9 Paul Mackerras
2016-11-19  0:38   ` Balbir Singh
2016-11-21  2:02     ` Paul Mackerras
2016-11-18  7:28 ` [PATCH 06/13] KVM: PPC: Book3S HV: Set partition table rather than SDR1 " Paul Mackerras
2016-11-19  1:01   ` Balbir Singh
2016-11-18  7:28 ` [PATCH 07/13] KVM: PPC: Book3S HV: Adjust host/guest context switch for POWER9 Paul Mackerras
2016-11-18 14:35   ` Aneesh Kumar K.V
2016-11-19  4:02     ` Paul Mackerras
2016-11-18  7:28 ` [PATCH 08/13] KVM: PPC: Book3S HV: Add new POWER9 guest-accessible SPRs Paul Mackerras
2016-11-18  7:28 ` [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9 Paul Mackerras
2016-11-18 14:41   ` Aneesh Kumar K.V
2016-11-18 21:57     ` Benjamin Herrenschmidt
2016-11-19  4:14       ` Paul Mackerras
2016-11-19  4:41         ` Benjamin Herrenschmidt
2016-11-19  4:13     ` Paul Mackerras
2016-11-18  7:28 ` [PATCH 10/13] KVM: PPC: Book3S HV: Use msgsnd for IPIs to other cores " Paul Mackerras
2016-11-18 14:47   ` Aneesh Kumar K.V
2016-11-19  3:53     ` Paul Mackerras
2016-11-18  7:28 ` [PATCH 11/13] KVM: PPC: Book3S HV: Use OPAL XICS emulation " Paul Mackerras
2016-11-18  7:28 ` Paul Mackerras [this message]
2016-11-18  7:28 ` [PATCH 13/13] KVM: PPC: Book3S HV: Treat POWER9 CPU threads as independent subcores Paul Mackerras

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