From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
To: mpe@ellerman.id.au
Cc: mikey@neuling.org, maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH 0/4] powerpc/perf: Power PMU fixes for power10 DD1
Date: Thu, 8 Oct 2020 06:52:05 -0400
Message-ID: <1602154329-2092-1-git-send-email-atrajeev@linux.vnet.ibm.com> (raw)
The patch series addresses PMU fixes for power10 DD1
Patch1 introduces a new power pmu flag to include
conditional code changes for power10 DD1.
Patch2 and Patch3 includes fixes in core-book3s to address
issues with marked events during sampling.
Patch4 includes fix to drop kernel samples while
userspace profiling.
Athira Rajeev (4):
powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" for power10 DD1
powerpc/perf: Using SIER[CMPL] instead of SIER[SIAR_VALID]
powerpc/perf: Use the address from SIAR register to set cpumode flags
powerpc/perf: Exclude kernel samples while counting events in user
space.
arch/powerpc/include/asm/perf_event_server.h | 1 +
arch/powerpc/perf/core-book3s.c | 35 +++++++++++++++++++++++++++-
arch/powerpc/perf/power10-pmu.c | 6 +++++
3 files changed, 41 insertions(+), 1 deletion(-)
--
1.8.3.1
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Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-08 10:52 Athira Rajeev [this message]
2020-10-08 10:52 ` [PATCH 1/4] powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" " Athira Rajeev
2020-10-08 10:52 ` [PATCH 2/4] powerpc/perf: Using SIER[CMPL] instead of SIER[SIAR_VALID] Athira Rajeev
2020-10-08 10:52 ` [PATCH 3/4] powerpc/perf: Use the address from SIAR register to set cpumode flags Athira Rajeev
2020-10-08 10:52 ` [PATCH 4/4] powerpc/perf: Exclude kernel samples while counting events in user space Athira Rajeev
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