* [PATCH RFT V2 1/8] clk: divider: add explicit big endian support
2019-04-15 10:10 [PATCH RFT V2 0/8] clk: make register endianness a run-time property Jonas Gorski
@ 2019-04-15 10:10 ` Jonas Gorski
2019-04-16 4:05 ` kbuild test robot
2019-04-17 23:32 ` Stephen Boyd
2019-04-15 10:10 ` [PATCH RFT V2 2/8] clk: fractional-divider: " Jonas Gorski
` (6 subsequent siblings)
7 siblings, 2 replies; 13+ messages in thread
From: Jonas Gorski @ 2019-04-15 10:10 UTC (permalink / raw)
To: linux-clk, linuxppc-dev, linux-arm-kernel, linux-rockchip, linux-tegra
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner, Stephen Boyd,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian divider clocks.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-divider.c | 26 ++++++++++++++++++++++----
include/linux/clk-provider.h | 4 ++++
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index e5a17265cfaf..ff791a7a5e9e 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -25,6 +25,24 @@
* parent - fixed parent. No clk_set_parent support
*/
+static inline u32 clk_div_readl(struct clk_divider *divider)
+{
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ return ioread32be(divider->reg);
+ else
+ return clk_readl(divider->reg);
+}
+
+static inline void clk_div_writel(struct clk_divider *divider, u32 val)
+{
+ if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
+ iowrite32be(val, divider->reg);
+ else
+ clk_writel(val, divider->reg);
+}
+
+#define div_mask(width) ((1 << (width)) - 1)
+
static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
u8 width)
{
@@ -135,7 +153,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int val;
- val = clk_readl(divider->reg) >> divider->shift;
+ val = clk_div_readl(divider) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -370,7 +388,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_READ_ONLY) {
u32 val;
- val = clk_readl(divider->reg) >> divider->shift;
+ val = clk_div_readl(divider->reg) >> divider->shift;
val &= clk_div_mask(divider->width);
return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -420,11 +438,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = clk_div_mask(divider->width) << (divider->shift + 16);
} else {
- val = clk_readl(divider->reg);
+ val = clk_div_readl(divider->reg);
val &= ~(clk_div_mask(divider->width) << divider->shift);
}
val |= (u32)value << divider->shift;
- clk_writel(val, divider->reg);
+ clk_div_writel(divider, val);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index db21437c77e2..7117b8cc0c0c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -416,6 +416,9 @@ struct clk_div_table {
* CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
* except when the value read from the register is zero, the divisor is
* 2^width of the field.
+ * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
+ * for the divider register. Setting this flag makes the register accesses
+ * big endian.
*/
struct clk_divider {
struct clk_hw hw;
@@ -437,6 +440,7 @@ struct clk_divider {
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+#define CLK_DIVIDER_BIG_ENDIAN BIT(7)
extern const struct clk_ops clk_divider_ops;
extern const struct clk_ops clk_divider_ro_ops;
--
2.13.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH RFT V2 1/8] clk: divider: add explicit big endian support
2019-04-15 10:10 ` [PATCH RFT V2 1/8] clk: divider: add explicit big endian support Jonas Gorski
@ 2019-04-16 4:05 ` kbuild test robot
2019-04-17 23:32 ` Stephen Boyd
1 sibling, 0 replies; 13+ messages in thread
From: kbuild test robot @ 2019-04-16 4:05 UTC (permalink / raw)
To: Jonas Gorski
Cc: Prashant Gaikwad, Sascha Hauer, Heiko Stuebner, Stephen Boyd,
Fabio Estevam, Peter De Schrijver, Michal Simek, Shawn Guo,
Jonathan Hunter, linux-rockchip, Michael Turquette,
Paul Mackerras, kbuild-all, Pengutronix Kernel Team, linux-tegra,
Thierry Reding, Anatolij Gustschin, linuxppc-dev, linux-clk,
linux-arm-kernel, NXP Linux Team
Hi Jonas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on v5.1-rc5 next-20190415]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Jonas-Gorski/clk-make-register-endianness-a-run-time-property/20190415-235847
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
sparse warnings: (new ones prefixed by >>)
drivers/clk/clk-divider.c:317:18: sparse: expression using sizeof(void)
drivers/clk/clk-divider.c:317:18: sparse: expression using sizeof(void)
>> drivers/clk/clk-divider.c:391:44: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct clk_divider *divider @@ got voistruct clk_divider *divider @@
drivers/clk/clk-divider.c:391:44: expected struct clk_divider *divider
drivers/clk/clk-divider.c:391:44: got void [noderef] <asn:2>*reg
drivers/clk/clk-divider.c:416:16: sparse: expression using sizeof(void)
drivers/clk/clk-divider.c:416:16: sparse: expression using sizeof(void)
drivers/clk/clk-divider.c:441:44: sparse: incorrect type in argument 1 (different address spaces) @@ expected struct clk_divider *divider @@ got voistruct clk_divider *divider @@
drivers/clk/clk-divider.c:441:44: expected struct clk_divider *divider
drivers/clk/clk-divider.c:441:44: got void [noderef] <asn:2>*reg
vim +391 drivers/clk/clk-divider.c
289
290 static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
291 unsigned long rate,
292 unsigned long *best_parent_rate,
293 const struct clk_div_table *table, u8 width,
294 unsigned long flags)
295 {
296 int i, bestdiv = 0;
297 unsigned long parent_rate, best = 0, now, maxdiv;
298 unsigned long parent_rate_saved = *best_parent_rate;
299
300 if (!rate)
301 rate = 1;
302
303 maxdiv = _get_maxdiv(table, width, flags);
304
305 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
306 parent_rate = *best_parent_rate;
307 bestdiv = _div_round(table, parent_rate, rate, flags);
308 bestdiv = bestdiv == 0 ? 1 : bestdiv;
309 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
310 return bestdiv;
311 }
312
313 /*
314 * The maximum divider we can use without overflowing
315 * unsigned long in rate * i below
316 */
> 317 maxdiv = min(ULONG_MAX / rate, maxdiv);
318
319 for (i = _next_div(table, 0, flags); i <= maxdiv;
320 i = _next_div(table, i, flags)) {
321 if (rate * i == parent_rate_saved) {
322 /*
323 * It's the most ideal case if the requested rate can be
324 * divided from parent clock without needing to change
325 * parent rate, so return the divider immediately.
326 */
327 *best_parent_rate = parent_rate_saved;
328 return i;
329 }
330 parent_rate = clk_hw_round_rate(parent, rate * i);
331 now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
332 if (_is_best_div(rate, now, best, flags)) {
333 bestdiv = i;
334 best = now;
335 *best_parent_rate = parent_rate;
336 }
337 }
338
339 if (!bestdiv) {
340 bestdiv = _get_maxdiv(table, width, flags);
341 *best_parent_rate = clk_hw_round_rate(parent, 1);
342 }
343
344 return bestdiv;
345 }
346
347 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
348 unsigned long rate, unsigned long *prate,
349 const struct clk_div_table *table,
350 u8 width, unsigned long flags)
351 {
352 int div;
353
354 div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);
355
356 return DIV_ROUND_UP_ULL((u64)*prate, div);
357 }
358 EXPORT_SYMBOL_GPL(divider_round_rate_parent);
359
360 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
361 unsigned long rate, unsigned long *prate,
362 const struct clk_div_table *table, u8 width,
363 unsigned long flags, unsigned int val)
364 {
365 int div;
366
367 div = _get_div(table, val, flags, width);
368
369 /* Even a read-only clock can propagate a rate change */
370 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
371 if (!parent)
372 return -EINVAL;
373
374 *prate = clk_hw_round_rate(parent, rate * div);
375 }
376
377 return DIV_ROUND_UP_ULL((u64)*prate, div);
378 }
379 EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent);
380
381
382 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
383 unsigned long *prate)
384 {
385 struct clk_divider *divider = to_clk_divider(hw);
386
387 /* if read only, just return current value */
388 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
389 u32 val;
390
> 391 val = clk_div_readl(divider->reg) >> divider->shift;
392 val &= clk_div_mask(divider->width);
393
394 return divider_ro_round_rate(hw, rate, prate, divider->table,
395 divider->width, divider->flags,
396 val);
397 }
398
399 return divider_round_rate(hw, rate, prate, divider->table,
400 divider->width, divider->flags);
401 }
402
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH RFT V2 1/8] clk: divider: add explicit big endian support
2019-04-15 10:10 ` [PATCH RFT V2 1/8] clk: divider: add explicit big endian support Jonas Gorski
2019-04-16 4:05 ` kbuild test robot
@ 2019-04-17 23:32 ` Stephen Boyd
2019-04-18 9:00 ` Jonas Gorski
1 sibling, 1 reply; 13+ messages in thread
From: Stephen Boyd @ 2019-04-17 23:32 UTC (permalink / raw)
To: Jonas Gorski, linux-arm-kernel, linux-clk, linux-rockchip,
linux-tegra, linuxppc-dev
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Quoting Jonas Gorski (2019-04-15 03:10:39)
> @@ -370,7 +388,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> if (divider->flags & CLK_DIVIDER_READ_ONLY) {
> u32 val;
>
> - val = clk_readl(divider->reg) >> divider->shift;
> + val = clk_div_readl(divider->reg) >> divider->shift;
Good deal that kbuild running sparse found that this was supposed to be
divider and not divider->reg. If you can fix that and remove the else in
all the basic type readl wrappers then this series looks good to merge
for me.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH RFT V2 1/8] clk: divider: add explicit big endian support
2019-04-17 23:32 ` Stephen Boyd
@ 2019-04-18 9:00 ` Jonas Gorski
0 siblings, 0 replies; 13+ messages in thread
From: Jonas Gorski @ 2019-04-18 9:00 UTC (permalink / raw)
To: Stephen Boyd
Cc: Thierry Reding, Peter De Schrijver, Fabio Estevam, Sascha Hauer,
Heiko Stuebner, Michael Turquette, Michal Simek, Jonathan Hunter,
linux-rockchip, Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, linux-tegra, Shawn Guo,
Anatolij Gustschin, linuxppc-dev, linux-clk,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Thu, 18 Apr 2019 at 01:32, Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Jonas Gorski (2019-04-15 03:10:39)
> > @@ -370,7 +388,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> > if (divider->flags & CLK_DIVIDER_READ_ONLY) {
> > u32 val;
> >
> > - val = clk_readl(divider->reg) >> divider->shift;
> > + val = clk_div_readl(divider->reg) >> divider->shift;
>
> Good deal that kbuild running sparse found that this was supposed to be
> divider and not divider->reg. If you can fix that and remove the else in
> all the basic type readl wrappers then this series looks good to merge
> for me.
Yeah, I'm quite glad about that. I was first confused why I didn't
catch it in my test build, but then remembered only C++ complains
about implicit void* casts (IIRC). I have it already fixed locally and
did a sparse build myself, was just waiting for at least one non-bot
comment before resending the series.
Regards
Jonas
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH RFT V2 2/8] clk: fractional-divider: add explicit big endian support
2019-04-15 10:10 [PATCH RFT V2 0/8] clk: make register endianness a run-time property Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 1/8] clk: divider: add explicit big endian support Jonas Gorski
@ 2019-04-15 10:10 ` Jonas Gorski
2019-04-17 23:30 ` Stephen Boyd
2019-04-15 10:10 ` [PATCH RFT V2 3/8] clk: gate: " Jonas Gorski
` (5 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Jonas Gorski @ 2019-04-15 10:10 UTC (permalink / raw)
To: linux-clk, linuxppc-dev, linux-arm-kernel, linux-rockchip, linux-tegra
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner, Stephen Boyd,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian fractional divider clocks.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
V1 -> V2:
* newly added patch
drivers/clk/clk-fractional-divider.c | 22 +++++++++++++++++++---
include/linux/clk-provider.h | 4 ++++
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index fdfe2e423d15..b9988d3b3828 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -13,6 +13,22 @@
#include <linux/slab.h>
#include <linux/rational.h>
+static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
+{
+ if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
+ return ioread32be(fd->reg);
+ else
+ return clk_readl(fd->reg);
+}
+
+static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
+{
+ if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
+ iowrite32be(val, fd->reg);
+ else
+ clk_writel(val, fd->reg);
+}
+
static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -27,7 +43,7 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
else
__acquire(fd->lock);
- val = clk_readl(fd->reg);
+ val = clk_fd_readl(fd);
if (fd->lock)
spin_unlock_irqrestore(fd->lock, flags);
@@ -115,10 +131,10 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
else
__acquire(fd->lock);
- val = clk_readl(fd->reg);
+ val = clk_fd_readl(fd);
val &= ~(fd->mmask | fd->nmask);
val |= (m << fd->mshift) | (n << fd->nshift);
- clk_writel(val, fd->reg);
+ clk_fd_writel(fd, val);
if (fd->lock)
spin_unlock_irqrestore(fd->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7117b8cc0c0c..8c07d810acf5 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -607,6 +607,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
* is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
* is set then the numerator and denominator are both the value read
* plus one.
+ * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
+ * used for the divider register. Setting this flag makes the register
+ * accesses big endian.
*/
struct clk_fractional_divider {
struct clk_hw hw;
@@ -627,6 +630,7 @@ struct clk_fractional_divider {
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
+#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
extern const struct clk_ops clk_fractional_divider_ops;
struct clk *clk_register_fractional_divider(struct device *dev,
--
2.13.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH RFT V2 2/8] clk: fractional-divider: add explicit big endian support
2019-04-15 10:10 ` [PATCH RFT V2 2/8] clk: fractional-divider: " Jonas Gorski
@ 2019-04-17 23:30 ` Stephen Boyd
0 siblings, 0 replies; 13+ messages in thread
From: Stephen Boyd @ 2019-04-17 23:30 UTC (permalink / raw)
To: Jonas Gorski, linux-arm-kernel, linux-clk, linux-rockchip,
linux-tegra, linuxppc-dev
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Quoting Jonas Gorski (2019-04-15 03:10:40)
> diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
> index fdfe2e423d15..b9988d3b3828 100644
> --- a/drivers/clk/clk-fractional-divider.c
> +++ b/drivers/clk/clk-fractional-divider.c
> @@ -13,6 +13,22 @@
> #include <linux/slab.h>
> #include <linux/rational.h>
>
> +static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
> +{
> + if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
> + return ioread32be(fd->reg);
> + else
> + return clk_readl(fd->reg);
Can you write it without the else?
if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
return ioread32be(fd->reg);
return clk_readl(fd->reg);
This same comment applies to all the basic clk types.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH RFT V2 3/8] clk: gate: add explicit big endian support
2019-04-15 10:10 [PATCH RFT V2 0/8] clk: make register endianness a run-time property Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 1/8] clk: divider: add explicit big endian support Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 2/8] clk: fractional-divider: " Jonas Gorski
@ 2019-04-15 10:10 ` Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 4/8] clk: multiplier: " Jonas Gorski
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Jonas Gorski @ 2019-04-15 10:10 UTC (permalink / raw)
To: linux-clk, linuxppc-dev, linux-arm-kernel, linux-rockchip, linux-tegra
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner, Stephen Boyd,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian gated clocks.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-gate.c | 22 +++++++++++++++++++---
include/linux/clk-provider.h | 4 ++++
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index f05823cd9b21..521e112ef5b5 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -23,6 +23,22 @@
* parent - fixed parent. No clk_set_parent support
*/
+static inline u32 clk_gate_readl(struct clk_gate *gate)
+{
+ if (gate->flags & CLK_GATE_BIG_ENDIAN)
+ return ioread32be(gate->reg);
+ else
+ return clk_readl(gate->reg);
+}
+
+static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
+{
+ if (gate->flags & CLK_GATE_BIG_ENDIAN)
+ iowrite32be(val, gate->reg);
+ else
+ clk_writel(val, gate->reg);
+}
+
/*
* It works on following logic:
*
@@ -55,7 +71,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
- reg = clk_readl(gate->reg);
+ reg = clk_gate_readl(gate);
if (set)
reg |= BIT(gate->bit_idx);
@@ -63,7 +79,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
reg &= ~BIT(gate->bit_idx);
}
- clk_writel(reg, gate->reg);
+ clk_gate_writel(gate, reg);
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
@@ -88,7 +104,7 @@ int clk_gate_is_enabled(struct clk_hw *hw)
u32 reg;
struct clk_gate *gate = to_clk_gate(hw);
- reg = clk_readl(gate->reg);
+ reg = clk_gate_readl(gate);
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 8c07d810acf5..8576c2dbc639 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -348,6 +348,9 @@ void of_fixed_clk_setup(struct device_node *np);
* of this register, and mask of gate bits are in higher 16-bit of this
* register. While setting the gate bits, higher 16-bit should also be
* updated to indicate changing gate bits.
+ * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
+ * the gate register. Setting this flag makes the register accesses big
+ * endian.
*/
struct clk_gate {
struct clk_hw hw;
@@ -361,6 +364,7 @@ struct clk_gate {
#define CLK_GATE_SET_TO_DISABLE BIT(0)
#define CLK_GATE_HIWORD_MASK BIT(1)
+#define CLK_GATE_BIG_ENDIAN BIT(2)
extern const struct clk_ops clk_gate_ops;
struct clk *clk_register_gate(struct device *dev, const char *name,
--
2.13.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH RFT V2 4/8] clk: multiplier: add explicit big endian support
2019-04-15 10:10 [PATCH RFT V2 0/8] clk: make register endianness a run-time property Jonas Gorski
` (2 preceding siblings ...)
2019-04-15 10:10 ` [PATCH RFT V2 3/8] clk: gate: " Jonas Gorski
@ 2019-04-15 10:10 ` Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 5/8] clk: mux: " Jonas Gorski
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Jonas Gorski @ 2019-04-15 10:10 UTC (permalink / raw)
To: linux-clk, linuxppc-dev, linux-arm-kernel, linux-rockchip, linux-tegra
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner, Stephen Boyd,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian multiplier clocks.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
V1 -> V2:
* newly added patch
drivers/clk/clk-multiplier.c | 22 +++++++++++++++++++---
include/linux/clk-provider.h | 4 ++++
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c
index 3c86f859c199..fb032f7dd407 100644
--- a/drivers/clk/clk-multiplier.c
+++ b/drivers/clk/clk-multiplier.c
@@ -11,6 +11,22 @@
#include <linux/of.h>
#include <linux/slab.h>
+static inline u32 clk_mult_readl(struct clk_multiplier *mult)
+{
+ if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
+ return ioread32be(mult->reg);
+ else
+ return clk_readl(mult->reg);
+}
+
+static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val)
+{
+ if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
+ iowrite32be(val, mult->reg);
+ else
+ clk_writel(val, mult->reg);
+}
+
static unsigned long __get_mult(struct clk_multiplier *mult,
unsigned long rate,
unsigned long parent_rate)
@@ -27,7 +43,7 @@ static unsigned long clk_multiplier_recalc_rate(struct clk_hw *hw,
struct clk_multiplier *mult = to_clk_multiplier(hw);
unsigned long val;
- val = clk_readl(mult->reg) >> mult->shift;
+ val = clk_mult_readl(mult) >> mult->shift;
val &= GENMASK(mult->width - 1, 0);
if (!val && mult->flags & CLK_MULTIPLIER_ZERO_BYPASS)
@@ -118,10 +134,10 @@ static int clk_multiplier_set_rate(struct clk_hw *hw, unsigned long rate,
else
__acquire(mult->lock);
- val = clk_readl(mult->reg);
+ val = clk_mult_readl(mult);
val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift);
val |= factor << mult->shift;
- clk_writel(val, mult->reg);
+ clk_mult_writel(mult, val);
if (mult->lock)
spin_unlock_irqrestore(mult->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 8576c2dbc639..9df78e3fb62b 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -667,6 +667,9 @@ void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
* leaving the parent rate unmodified.
* CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
* rounded to the closest integer instead of the down one.
+ * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
+ * used for the multiplier register. Setting this flag makes the register
+ * accesses big endian.
*/
struct clk_multiplier {
struct clk_hw hw;
@@ -681,6 +684,7 @@ struct clk_multiplier {
#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
+#define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
extern const struct clk_ops clk_multiplier_ops;
--
2.13.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH RFT V2 5/8] clk: mux: add explicit big endian support
2019-04-15 10:10 [PATCH RFT V2 0/8] clk: make register endianness a run-time property Jonas Gorski
` (3 preceding siblings ...)
2019-04-15 10:10 ` [PATCH RFT V2 4/8] clk: multiplier: " Jonas Gorski
@ 2019-04-15 10:10 ` Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 6/8] powerpc/512x: mark clocks as big endian Jonas Gorski
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Jonas Gorski @ 2019-04-15 10:10 UTC (permalink / raw)
To: linux-clk, linuxppc-dev, linux-arm-kernel, linux-rockchip, linux-tegra
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner, Stephen Boyd,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Add a clock specific flag to switch register accesses to big endian, to
allow runtime configuration of big endian mux clocks.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
V1 -> V2:
* switch from global to local flag
drivers/clk/clk-mux.c | 22 +++++++++++++++++++---
include/linux/clk-provider.h | 4 ++++
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 2ad2df2e8909..47f6f4f55f08 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -23,6 +23,22 @@
* parent - parent is adjustable through clk_set_parent
*/
+static inline u32 clk_mux_readl(struct clk_mux *mux)
+{
+ if (mux->flags & CLK_MUX_BIG_ENDIAN)
+ return ioread32be(mux->reg);
+ else
+ return clk_readl(mux->reg);
+}
+
+static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
+{
+ if (mux->flags & CLK_MUX_BIG_ENDIAN)
+ iowrite32be(val, mux->reg);
+ else
+ clk_writel(val, mux->reg);
+}
+
int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
unsigned int val)
{
@@ -73,7 +89,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
struct clk_mux *mux = to_clk_mux(hw);
u32 val;
- val = clk_readl(mux->reg) >> mux->shift;
+ val = clk_mux_readl(mux) >> mux->shift;
val &= mux->mask;
return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
@@ -94,12 +110,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
if (mux->flags & CLK_MUX_HIWORD_MASK) {
reg = mux->mask << (mux->shift + 16);
} else {
- reg = clk_readl(mux->reg);
+ reg = clk_mux_readl(mux);
reg &= ~(mux->mask << mux->shift);
}
val = val << mux->shift;
reg |= val;
- clk_writel(reg, mux->reg);
+ clk_mux_writel(mux, reg);
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 9df78e3fb62b..f82cda41e1a8 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -510,6 +510,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw);
* .get_parent clk_op.
* CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
* frequency.
+ * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
+ * the mux register. Setting this flag makes the register accesses big
+ * endian.
*/
struct clk_mux {
struct clk_hw hw;
@@ -528,6 +531,7 @@ struct clk_mux {
#define CLK_MUX_HIWORD_MASK BIT(2)
#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
#define CLK_MUX_ROUND_CLOSEST BIT(4)
+#define CLK_MUX_BIG_ENDIAN BIT(5)
extern const struct clk_ops clk_mux_ops;
extern const struct clk_ops clk_mux_ro_ops;
--
2.13.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH RFT V2 6/8] powerpc/512x: mark clocks as big endian
2019-04-15 10:10 [PATCH RFT V2 0/8] clk: make register endianness a run-time property Jonas Gorski
` (4 preceding siblings ...)
2019-04-15 10:10 ` [PATCH RFT V2 5/8] clk: mux: " Jonas Gorski
@ 2019-04-15 10:10 ` Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 7/8] clk: core: remove powerpc special handling Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 8/8] clk: core: replace clk_{readl, writel} with {readl, writel} Jonas Gorski
7 siblings, 0 replies; 13+ messages in thread
From: Jonas Gorski @ 2019-04-15 10:10 UTC (permalink / raw)
To: linux-clk, linuxppc-dev, linux-arm-kernel, linux-rockchip, linux-tegra
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner, Stephen Boyd,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
These clocks' registers are accessed as big endian, so mark them as
such.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
V1 -> V2:
* switch from global to local flags
arch/powerpc/platforms/512x/clock-commonclk.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index b3097fe6441b..0072330350fa 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -240,7 +240,8 @@ static inline struct clk *mpc512x_clk_divider(
u32 __iomem *reg, u8 pos, u8 len, int divflags)
{
return clk_register_divider(NULL, name, parent_name, clkflags,
- reg, pos, len, divflags, &clklock);
+ reg, pos, len,
+ divflags | CLK_DIVIDER_BIG_ENDIAN, &clklock);
}
static inline struct clk *mpc512x_clk_divtable(
@@ -250,7 +251,7 @@ static inline struct clk *mpc512x_clk_divtable(
{
u8 divflags;
- divflags = 0;
+ divflags = CLK_DIVIDER_BIG_ENDIAN;
return clk_register_divider_table(NULL, name, parent_name, 0,
reg, pos, len, divflags,
divtab, &clklock);
@@ -261,10 +262,12 @@ static inline struct clk *mpc512x_clk_gated(
u32 __iomem *reg, u8 pos)
{
int clkflags;
+ u8 gateflags;
clkflags = CLK_SET_RATE_PARENT;
+ gateflags = CLK_GATE_BIG_ENDIAN;
return clk_register_gate(NULL, name, parent_name, clkflags,
- reg, pos, 0, &clklock);
+ reg, pos, gateflags, &clklock);
}
static inline struct clk *mpc512x_clk_muxed(const char *name,
@@ -275,7 +278,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name,
u8 muxflags;
clkflags = CLK_SET_RATE_PARENT;
- muxflags = 0;
+ muxflags = CLK_MUX_BIG_ENDIAN;
return clk_register_mux(NULL, name,
parent_names, parent_count, clkflags,
reg, pos, len, muxflags, &clklock);
--
2.13.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH RFT V2 7/8] clk: core: remove powerpc special handling
2019-04-15 10:10 [PATCH RFT V2 0/8] clk: make register endianness a run-time property Jonas Gorski
` (5 preceding siblings ...)
2019-04-15 10:10 ` [PATCH RFT V2 6/8] powerpc/512x: mark clocks as big endian Jonas Gorski
@ 2019-04-15 10:10 ` Jonas Gorski
2019-04-15 10:10 ` [PATCH RFT V2 8/8] clk: core: replace clk_{readl, writel} with {readl, writel} Jonas Gorski
7 siblings, 0 replies; 13+ messages in thread
From: Jonas Gorski @ 2019-04-15 10:10 UTC (permalink / raw)
To: linux-clk, linuxppc-dev, linux-arm-kernel, linux-rockchip, linux-tegra
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner, Stephen Boyd,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Now that the powerpc clocks are properly marked as big endian, we can
remove the special handling for PowerPC.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
V1 -> V2:
* no actual changes
include/linux/clk-provider.h | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f82cda41e1a8..479e616ce7f5 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1001,20 +1001,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index,
* for improved portability across platforms
*/
-#if IS_ENABLED(CONFIG_PPC)
-
-static inline u32 clk_readl(u32 __iomem *reg)
-{
- return ioread32be(reg);
-}
-
-static inline void clk_writel(u32 val, u32 __iomem *reg)
-{
- iowrite32be(val, reg);
-}
-
-#else /* platform dependent I/O accessors */
-
static inline u32 clk_readl(u32 __iomem *reg)
{
return readl(reg);
@@ -1025,8 +1011,6 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
writel(val, reg);
}
-#endif /* platform dependent I/O accessors */
-
void clk_gate_restore_context(struct clk_hw *hw);
#endif /* CONFIG_COMMON_CLK */
--
2.13.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH RFT V2 8/8] clk: core: replace clk_{readl, writel} with {readl, writel}
2019-04-15 10:10 [PATCH RFT V2 0/8] clk: make register endianness a run-time property Jonas Gorski
` (6 preceding siblings ...)
2019-04-15 10:10 ` [PATCH RFT V2 7/8] clk: core: remove powerpc special handling Jonas Gorski
@ 2019-04-15 10:10 ` Jonas Gorski
7 siblings, 0 replies; 13+ messages in thread
From: Jonas Gorski @ 2019-04-15 10:10 UTC (permalink / raw)
To: linux-clk, linuxppc-dev, linux-arm-kernel, linux-rockchip, linux-tegra
Cc: Peter De Schrijver, Fabio Estevam, Heiko Stuebner, Stephen Boyd,
Michael Turquette, Michal Simek, Jonathan Hunter,
Prashant Gaikwad, Paul Mackerras, NXP Linux Team,
Pengutronix Kernel Team, Thierry Reding, Anatolij Gustschin,
Shawn Guo, Sascha Hauer
Now that clk_{readl,writel} is just an alias for {readl,writel}, we can
switch all users of clk_* to use the accessors directly and remove the
helpers.
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
V1 -> V2:
* newly added patch
drivers/clk/clk-divider.c | 4 ++--
drivers/clk/clk-fractional-divider.c | 4 ++--
drivers/clk/clk-gate.c | 4 ++--
drivers/clk/clk-multiplier.c | 4 ++--
drivers/clk/clk-mux.c | 4 ++--
drivers/clk/clk-xgene.c | 6 +++---
drivers/clk/hisilicon/clk-hisi-phase.c | 4 ++--
drivers/clk/imx/clk-divider-gate.c | 20 ++++++++++----------
drivers/clk/imx/clk-sccg-pll.c | 12 ++++++------
drivers/clk/nxp/clk-lpc18xx-ccu.c | 6 +++---
drivers/clk/nxp/clk-lpc18xx-cgu.c | 24 ++++++++++++------------
drivers/clk/rockchip/clk-ddr.c | 2 +-
drivers/clk/rockchip/clk-half-divider.c | 6 +++---
drivers/clk/tegra/clk-tegra124.c | 4 ++--
drivers/clk/tegra/clk-tegra210.c | 6 +++---
drivers/clk/zynq/clkc.c | 6 +++---
drivers/clk/zynq/pll.c | 18 +++++++++---------
include/linux/clk-provider.h | 15 ---------------
18 files changed, 67 insertions(+), 82 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index ff791a7a5e9e..bb49dbf05a64 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -30,7 +30,7 @@ static inline u32 clk_div_readl(struct clk_divider *divider)
if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
return ioread32be(divider->reg);
else
- return clk_readl(divider->reg);
+ return readl(divider->reg);
}
static inline void clk_div_writel(struct clk_divider *divider, u32 val)
@@ -38,7 +38,7 @@ static inline void clk_div_writel(struct clk_divider *divider, u32 val)
if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
iowrite32be(val, divider->reg);
else
- clk_writel(val, divider->reg);
+ writel(val, divider->reg);
}
#define div_mask(width) ((1 << (width)) - 1)
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index b9988d3b3828..99133554466f 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -18,7 +18,7 @@ static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
return ioread32be(fd->reg);
else
- return clk_readl(fd->reg);
+ return readl(fd->reg);
}
static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
@@ -26,7 +26,7 @@ static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
iowrite32be(val, fd->reg);
else
- clk_writel(val, fd->reg);
+ writel(val, fd->reg);
}
static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 521e112ef5b5..bd201eaa99df 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -28,7 +28,7 @@ static inline u32 clk_gate_readl(struct clk_gate *gate)
if (gate->flags & CLK_GATE_BIG_ENDIAN)
return ioread32be(gate->reg);
else
- return clk_readl(gate->reg);
+ return readl(gate->reg);
}
static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
@@ -36,7 +36,7 @@ static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
if (gate->flags & CLK_GATE_BIG_ENDIAN)
iowrite32be(val, gate->reg);
else
- clk_writel(val, gate->reg);
+ writel(val, gate->reg);
}
/*
diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c
index fb032f7dd407..a433442a1fa6 100644
--- a/drivers/clk/clk-multiplier.c
+++ b/drivers/clk/clk-multiplier.c
@@ -16,7 +16,7 @@ static inline u32 clk_mult_readl(struct clk_multiplier *mult)
if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
return ioread32be(mult->reg);
else
- return clk_readl(mult->reg);
+ return readl(mult->reg);
}
static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val)
@@ -24,7 +24,7 @@ static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val)
if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
iowrite32be(val, mult->reg);
else
- clk_writel(val, mult->reg);
+ writel(val, mult->reg);
}
static unsigned long __get_mult(struct clk_multiplier *mult,
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 47f6f4f55f08..9ae3a4c17ed5 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -28,7 +28,7 @@ static inline u32 clk_mux_readl(struct clk_mux *mux)
if (mux->flags & CLK_MUX_BIG_ENDIAN)
return ioread32be(mux->reg);
else
- return clk_readl(mux->reg);
+ return readl(mux->reg);
}
static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
@@ -36,7 +36,7 @@ static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
if (mux->flags & CLK_MUX_BIG_ENDIAN)
iowrite32be(val, mux->reg);
else
- clk_writel(val, mux->reg);
+ writel(val, mux->reg);
}
int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 531b030d4d4e..d975465fe2a8 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -262,7 +262,7 @@ static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw,
else
__acquire(fd->lock);
- val = clk_readl(fd->reg);
+ val = readl(fd->reg);
if (fd->lock)
spin_unlock_irqrestore(fd->lock, flags);
@@ -333,10 +333,10 @@ static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate,
else
__acquire(fd->lock);
- val = clk_readl(fd->reg);
+ val = readl(fd->reg);
val &= ~fd->mask;
val |= (scale << fd->shift);
- clk_writel(val, fd->reg);
+ writel(val, fd->reg);
if (fd->lock)
spin_unlock_irqrestore(fd->lock, flags);
diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c
index 5fdc267bb2da..ba6afad66a2b 100644
--- a/drivers/clk/hisilicon/clk-hisi-phase.c
+++ b/drivers/clk/hisilicon/clk-hisi-phase.c
@@ -75,10 +75,10 @@ static int hisi_clk_set_phase(struct clk_hw *hw, int degrees)
spin_lock_irqsave(phase->lock, flags);
- val = clk_readl(phase->reg);
+ val = readl(phase->reg);
val &= ~phase->mask;
val |= regval << phase->shift;
- clk_writel(val, phase->reg);
+ writel(val, phase->reg);
spin_unlock_irqrestore(phase->lock, flags);
diff --git a/drivers/clk/imx/clk-divider-gate.c b/drivers/clk/imx/clk-divider-gate.c
index df1f8429fe16..2a8352a316c7 100644
--- a/drivers/clk/imx/clk-divider-gate.c
+++ b/drivers/clk/imx/clk-divider-gate.c
@@ -29,7 +29,7 @@ static unsigned long clk_divider_gate_recalc_rate_ro(struct clk_hw *hw,
struct clk_divider *div = to_clk_divider(hw);
unsigned int val;
- val = clk_readl(div->reg) >> div->shift;
+ val = readl(div->reg) >> div->shift;
val &= clk_div_mask(div->width);
if (!val)
return 0;
@@ -51,7 +51,7 @@ static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
if (!clk_hw_is_enabled(hw)) {
val = div_gate->cached_val;
} else {
- val = clk_readl(div->reg) >> div->shift;
+ val = readl(div->reg) >> div->shift;
val &= clk_div_mask(div->width);
}
@@ -87,10 +87,10 @@ static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
spin_lock_irqsave(div->lock, flags);
if (clk_hw_is_enabled(hw)) {
- val = clk_readl(div->reg);
+ val = readl(div->reg);
val &= ~(clk_div_mask(div->width) << div->shift);
val |= (u32)value << div->shift;
- clk_writel(val, div->reg);
+ writel(val, div->reg);
} else {
div_gate->cached_val = value;
}
@@ -114,9 +114,9 @@ static int clk_divider_enable(struct clk_hw *hw)
spin_lock_irqsave(div->lock, flags);
/* restore div val */
- val = clk_readl(div->reg);
+ val = readl(div->reg);
val |= div_gate->cached_val << div->shift;
- clk_writel(val, div->reg);
+ writel(val, div->reg);
spin_unlock_irqrestore(div->lock, flags);
@@ -133,10 +133,10 @@ static void clk_divider_disable(struct clk_hw *hw)
spin_lock_irqsave(div->lock, flags);
/* store the current div val */
- val = clk_readl(div->reg) >> div->shift;
+ val = readl(div->reg) >> div->shift;
val &= clk_div_mask(div->width);
div_gate->cached_val = val;
- clk_writel(0, div->reg);
+ writel(0, div->reg);
spin_unlock_irqrestore(div->lock, flags);
}
@@ -146,7 +146,7 @@ static int clk_divider_is_enabled(struct clk_hw *hw)
struct clk_divider *div = to_clk_divider(hw);
u32 val;
- val = clk_readl(div->reg) >> div->shift;
+ val = readl(div->reg) >> div->shift;
val &= clk_div_mask(div->width);
return val ? 1 : 0;
@@ -206,7 +206,7 @@ struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name,
div_gate->divider.hw.init = &init;
div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;
/* cache gate status */
- val = clk_readl(reg) >> shift;
+ val = readl(reg) >> shift;
val &= clk_div_mask(width);
div_gate->cached_val = val;
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 9dfd03a95557..991bbe63f156 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -348,7 +348,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
temp64 = parent_rate;
- val = clk_readl(pll->base + PLL_CFG0);
+ val = readl(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK) {
temp64 = parent_rate;
} else if (val & SSCG_PLL_BYPASS1_MASK) {
@@ -371,10 +371,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
u32 val;
/* set bypass here too since the parent might be the same */
- val = clk_readl(pll->base + PLL_CFG0);
+ val = readl(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
- clk_writel(val, pll->base + PLL_CFG0);
+ writel(val, pll->base + PLL_CFG0);
val = readl_relaxed(pll->base + PLL_CFG2);
val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
@@ -395,7 +395,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw)
u32 val;
u8 ret = pll->parent;
- val = clk_readl(pll->base + PLL_CFG0);
+ val = readl(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK)
ret = pll->bypass2;
else if (val & SSCG_PLL_BYPASS1_MASK)
@@ -408,10 +408,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index)
struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
u32 val;
- val = clk_readl(pll->base + PLL_CFG0);
+ val = readl(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
- clk_writel(val, pll->base + PLL_CFG0);
+ writel(val, pll->base + PLL_CFG0);
return clk_sccg_pll_wait_lock(pll);
}
diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c
index 27781b49eb82..5969f620607a 100644
--- a/drivers/clk/nxp/clk-lpc18xx-ccu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-ccu.c
@@ -142,7 +142,7 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
* Divider field is write only, so divider stat field must
* be read so divider field can be set accordingly.
*/
- val = clk_readl(gate->reg);
+ val = readl(gate->reg);
if (val & LPC18XX_CCU_DIVSTAT)
val |= LPC18XX_CCU_DIV;
@@ -155,12 +155,12 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
* and the next write should clear the RUN bit.
*/
val |= LPC18XX_CCU_AUTO;
- clk_writel(val, gate->reg);
+ writel(val, gate->reg);
val &= ~LPC18XX_CCU_RUN;
}
- clk_writel(val, gate->reg);
+ writel(val, gate->reg);
return 0;
}
diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
index 2531174b399e..f5bc8bd192b7 100644
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -352,9 +352,9 @@ static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw,
struct lpc18xx_pll *pll = to_lpc_pll(hw);
u32 ctrl, mdiv, msel, npdiv;
- ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
- mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
- npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
+ ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+ mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
+ npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)
return parent_rate;
@@ -415,25 +415,25 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate,
m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;
/* Power down PLL, disable clk output and dividers */
- ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+ ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
ctrl |= LPC18XX_PLL0_CTRL_PD;
ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |
LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);
- clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+ writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
/* Configure new PLL settings */
- clk_writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
- clk_writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
+ writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
+ writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
/* Power up PLL and wait for lock */
ctrl &= ~LPC18XX_PLL0_CTRL_PD;
- clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+ writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
do {
udelay(10);
- stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
+ stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
if (stat & LPC18XX_PLL0_STAT_LOCK) {
ctrl |= LPC18XX_PLL0_CTRL_CLKEN;
- clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+ writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
return 0;
}
@@ -458,8 +458,8 @@ static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw,
bool direct, fbsel;
u32 stat, ctrl;
- stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
- ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
+ stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
+ ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;
diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index ebce5260068b..09ede6920593 100644
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -82,7 +82,7 @@ static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
u32 val;
- val = clk_readl(ddrclk->reg_base +
+ val = readl(ddrclk->reg_base +
ddrclk->mux_offset) >> ddrclk->mux_shift;
val &= GENMASK(ddrclk->mux_width - 1, 0);
diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
index b8da6e799423..784b81e1ea7c 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -24,7 +24,7 @@ static unsigned long clk_half_divider_recalc_rate(struct clk_hw *hw,
struct clk_divider *divider = to_clk_divider(hw);
unsigned int val;
- val = clk_readl(divider->reg) >> divider->shift;
+ val = readl(divider->reg) >> divider->shift;
val &= div_mask(divider->width);
val = val * 2 + 3;
@@ -124,11 +124,11 @@ static int clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider->width) << (divider->shift + 16);
} else {
- val = clk_readl(divider->reg);
+ val = readl(divider->reg);
val &= ~(div_mask(divider->width) << divider->shift);
}
val |= value << divider->shift;
- clk_writel(val, divider->reg);
+ writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index df0018f7bf7e..abc0c4bea740 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1466,9 +1466,9 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
tegra_pmc_clk_init(pmc_base, tegra124_clks);
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
- plld_base = clk_readl(clk_base + PLLD_BASE);
+ plld_base = readl(clk_base + PLLD_BASE);
plld_base &= ~BIT(25);
- clk_writel(plld_base, clk_base + PLLD_BASE);
+ writel(plld_base, clk_base + PLLD_BASE);
}
/**
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 7545af763d7a..ed3c7df75d1e 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3557,7 +3557,7 @@ static void __init tegra210_clock_init(struct device_node *np)
if (!clks)
return;
- value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
+ value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
@@ -3574,9 +3574,9 @@ static void __init tegra210_clock_init(struct device_node *np)
tegra_pmc_clk_init(pmc_base, tegra210_clks);
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
- value = clk_readl(clk_base + PLLD_BASE);
+ value = readl(clk_base + PLLD_BASE);
value &= ~BIT(25);
- clk_writel(value, clk_base + PLLD_BASE);
+ writel(value, clk_base + PLLD_BASE);
tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index d7b53ac8ad11..4b9d5c14c400 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -158,7 +158,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
clks[fclk] = clk_register_gate(NULL, clk_name,
div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
- enable_reg = clk_readl(fclk_gate_reg) & 1;
+ enable_reg = readl(fclk_gate_reg) & 1;
if (enable && !enable_reg) {
if (clk_prepare_enable(clks[fclk]))
pr_warn("%s: FCLK%u enable failed\n", __func__,
@@ -287,7 +287,7 @@ static void __init zynq_clk_setup(struct device_node *np)
SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
/* CPU clocks */
- tmp = clk_readl(SLCR_621_TRUE) & 1;
+ tmp = readl(SLCR_621_TRUE) & 1;
clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
&armclk_lock);
@@ -510,7 +510,7 @@ static void __init zynq_clk_setup(struct device_node *np)
&dbgclk_lock);
/* leave debug clocks in the state the bootloader set them up to */
- tmp = clk_readl(SLCR_DBG_CLK_CTRL);
+ tmp = readl(SLCR_DBG_CLK_CTRL);
if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
if (clk_prepare_enable(clks[dbg_trc]))
pr_warn("%s: trace clk enable failed\n", __func__);
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
index 00d72fb5c036..800b70ee19b3 100644
--- a/drivers/clk/zynq/pll.c
+++ b/drivers/clk/zynq/pll.c
@@ -90,7 +90,7 @@ static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
* makes probably sense to redundantly save fbdiv in the struct
* zynq_pll to save the IO access.
*/
- fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
+ fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
PLLCTRL_FBDIV_SHIFT;
return parent_rate * fbdiv;
@@ -112,7 +112,7 @@ static int zynq_pll_is_enabled(struct clk_hw *hw)
spin_lock_irqsave(clk->lock, flags);
- reg = clk_readl(clk->pll_ctrl);
+ reg = readl(clk->pll_ctrl);
spin_unlock_irqrestore(clk->lock, flags);
@@ -138,10 +138,10 @@ static int zynq_pll_enable(struct clk_hw *hw)
/* Power up PLL and wait for lock */
spin_lock_irqsave(clk->lock, flags);
- reg = clk_readl(clk->pll_ctrl);
+ reg = readl(clk->pll_ctrl);
reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
- clk_writel(reg, clk->pll_ctrl);
- while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit)))
+ writel(reg, clk->pll_ctrl);
+ while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
;
spin_unlock_irqrestore(clk->lock, flags);
@@ -168,9 +168,9 @@ static void zynq_pll_disable(struct clk_hw *hw)
/* shut down PLL */
spin_lock_irqsave(clk->lock, flags);
- reg = clk_readl(clk->pll_ctrl);
+ reg = readl(clk->pll_ctrl);
reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
- clk_writel(reg, clk->pll_ctrl);
+ writel(reg, clk->pll_ctrl);
spin_unlock_irqrestore(clk->lock, flags);
}
@@ -223,9 +223,9 @@ struct clk *clk_register_zynq_pll(const char *name, const char *parent,
spin_lock_irqsave(pll->lock, flags);
- reg = clk_readl(pll->pll_ctrl);
+ reg = readl(pll->pll_ctrl);
reg &= ~PLLCTRL_BPQUAL_MASK;
- clk_writel(reg, pll->pll_ctrl);
+ writel(reg, pll->pll_ctrl);
spin_unlock_irqrestore(pll->lock, flags);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 479e616ce7f5..46d5fc3057b5 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -996,21 +996,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index,
}
#endif /* CONFIG_OF */
-/*
- * wrap access to peripherals in accessor routines
- * for improved portability across platforms
- */
-
-static inline u32 clk_readl(u32 __iomem *reg)
-{
- return readl(reg);
-}
-
-static inline void clk_writel(u32 val, u32 __iomem *reg)
-{
- writel(val, reg);
-}
-
void clk_gate_restore_context(struct clk_hw *hw);
#endif /* CONFIG_COMMON_CLK */
--
2.13.2
^ permalink raw reply related [flat|nested] 13+ messages in thread