RE: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support

[Leekha Shaveta-B20052 <B20052@freescale.com>]

-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Monday, March 18, 2013 8:26 PM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support


On Mar 18, 2013, at 1:28 AM, Leekha Shaveta-B20052 wrote:

>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Friday, March 15, 2013 9:28 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 5/6] powerpc/fsl-booke: Add B4_QDS board support
>=20
>=20
> On Mar 15, 2013, at 2:55 AM, Shaveta Leekha wrote:
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>> - Add support for B4 board's personalities in board file  b4_qds.c,=20
>> It is common for B4 personalities B4860 and B4420QDS
>> - Add B4QDS support in Kconfig and Makefile
>=20
> Code also references a B4220, what about it?
> [SL] I have added the basic support for it in board file as it's one=20
> of the personality of B4, missed it in description. But device trees for =
this has not been created and tested.
> So what do you suggest here:
> Should I add it here in B4 board support or should I remove its reference=
s altogether?

What's the difference between B4220 and B4420 or B4860?

- k
[SL] B4220 is again a reduced personality of B4 with some differences like:
	Even lesser Number of cores than B4860 and B4420, lesser number of SerDes =
lanes and some difference in 	other peripherals.
=09
BR,
Shaveta

>=20
>>=20
>> B4860QDS is a high-performance computing evaluation, development and=20
>> test platform supporting the B4860 QorIQ Power Architecture=20
>> processor, with following major features:
>>=20
>>   - Four dual-threaded e6500 Power Architecture processors
>>     organized in one cluster-each core runs up to 1.8 GHz
>>   - Two DDR3/3L controllers for high-speed memory interface each
>>     runs at up to 1866.67 MHz
>>   - CoreNet fabric that fully supports coherency using MESI protocol
>>     between the e6500 cores, SC3900 FVP cores, memories and
>>     external interfaces.
>>   - Data Path Acceleration Architecture having FMAN, QMan, BMan, SEC 5.3=
 and RMAN
>>   - Large internal cache memory with snooping and stashing capabilities
>>   - Sixteen 10-GHz SerDes lanes that serve:
>>       - Two SRIO interfaces. Each supports up to 4 lanes and
>>         a total of up to 8 lanes
>>       - Up to 8-lanes Common Public Radio Interface (CPRI) controller
>>         for glue-less antenna connection
>>       - Two 10-Gbit Ethernet controllers (10GEC)
>>       - Six 1G/2.5-Gbit Ethernet controllers for network communications
>>       - PCI Express controller
>>       - Debug (Aurora)
>>   - Various system peripherals
>>=20
>> B4420 is a reduced personality of B4860 with fewer core/clusters(both=20
>> SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMI=
I interfaces and reduced target frequencies.
>>=20
>> Key differences between B4860 and B4420:
>> B4420 has:
>>   - Fewer e6500 cores:
>>       1 cluster with 2 e6500 cores
>>   - Fewer SC3900 cores/clusters:
>>       1 cluster with 2 SC3900 cores per cluster
>>   - Single DDRC
>>   - 2X 4 lane serdes
>>   - 3 SGMII interfaces
>>   - no sRIO
>>   - no 10G
>>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> ---
>> arch/powerpc/platforms/85xx/Kconfig  |   16 +++++
>> arch/powerpc/platforms/85xx/Makefile |    1 +
>> arch/powerpc/platforms/85xx/b4_qds.c |  102
>> ++++++++++++++++++++++++++++++++++
>> 3 files changed, 119 insertions(+), 0 deletions(-) create mode 100644=20
>> arch/powerpc/platforms/85xx/b4_qds.c