* [PATCH] phy: ti-pipe3: Use TRM recommended settings for SATA DPLL
@ 2017-05-22 8:10 Roger Quadros
2017-08-07 9:11 ` [PATCH v2] " Roger Quadros
0 siblings, 1 reply; 3+ messages in thread
From: Roger Quadros @ 2017-05-22 8:10 UTC (permalink / raw)
To: kishon; +Cc: nsekhar, linux-kernel, Roger Quadros
The AM572x TRM [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.
Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.
[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
drivers/phy/phy-ti-pipe3.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 9c84d32..0e564f3 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -118,12 +118,12 @@ static struct pipe3_dpll_map dpll_map_usb[] = {
};
static struct pipe3_dpll_map dpll_map_sata[] = {
- {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
- {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
+ {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
- {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
- {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
- {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
+ {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
+ {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
{ }, /* Terminator */
};
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v2] phy: ti-pipe3: Use TRM recommended settings for SATA DPLL
2017-05-22 8:10 [PATCH] phy: ti-pipe3: Use TRM recommended settings for SATA DPLL Roger Quadros
@ 2017-08-07 9:11 ` Roger Quadros
2017-08-08 12:06 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 3+ messages in thread
From: Roger Quadros @ 2017-08-07 9:11 UTC (permalink / raw)
To: kishon; +Cc: nsekhar, linux-kernel, rogerq, linux-omap
The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.
Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.
[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
[nsekhar@ti.com: add exact TRM version to commit text]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
v2:
- Mention full TRM version in commit log
drivers/phy/ti/phy-ti-pipe3.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
index 9c84d32..0e564f3 100644
--- a/drivers/phy/ti/phy-ti-pipe3.c
+++ b/drivers/phy/ti/phy-ti-pipe3.c
@@ -118,12 +118,12 @@ static struct pipe3_dpll_map dpll_map_usb[] = {
};
static struct pipe3_dpll_map dpll_map_sata[] = {
- {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
- {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
+ {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
- {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
- {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
- {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
+ {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
+ {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
{ }, /* Terminator */
};
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] phy: ti-pipe3: Use TRM recommended settings for SATA DPLL
2017-08-07 9:11 ` [PATCH v2] " Roger Quadros
@ 2017-08-08 12:06 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 3+ messages in thread
From: Kishon Vijay Abraham I @ 2017-08-08 12:06 UTC (permalink / raw)
To: Roger Quadros; +Cc: nsekhar, linux-kernel, linux-omap
On Monday 07 August 2017 02:41 PM, Roger Quadros wrote:
> The AM572x Technical Reference Manual, SPRUHZ6H,
> Revised November 2016 [1], shows recommended settings for the
> SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.
>
> Use those settings in the driver. The TRM does not show
> a value for 20MHz SYS_CLK so we use something close to the
> 26MHz setting.
>
> [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf
>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> [nsekhar@ti.com: add exact TRM version to commit text]
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
merged, thanks!
-Kishon
> ---
> v2:
> - Mention full TRM version in commit log
>
> drivers/phy/ti/phy-ti-pipe3.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
> index 9c84d32..0e564f3 100644
> --- a/drivers/phy/ti/phy-ti-pipe3.c
> +++ b/drivers/phy/ti/phy-ti-pipe3.c
> @@ -118,12 +118,12 @@ static struct pipe3_dpll_map dpll_map_usb[] = {
> };
>
> static struct pipe3_dpll_map dpll_map_sata[] = {
> - {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
> - {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
> + {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
> + {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
> {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
> - {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
> - {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
> - {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
> + {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
> + {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
> + {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
> { }, /* Terminator */
> };
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-05-22 8:10 [PATCH] phy: ti-pipe3: Use TRM recommended settings for SATA DPLL Roger Quadros
2017-08-07 9:11 ` [PATCH v2] " Roger Quadros
2017-08-08 12:06 ` Kishon Vijay Abraham I
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