Re: [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 22/08/2022 22:19, Serge Semin wrote:
> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
> are individual IRQs for each ECC and DFI events.The dedicated scrubber

Missing space before "The".

> clock source is absent since it's fully synchronous to the core clock.

You need allOf:if-then restricting this per variant.

> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate
> registers space.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> ---
>  .../memory-controllers/snps,dw-umctl2-ddrc.yaml        | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> index 8db92210cfe1..899a6c5f9806 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> @@ -26,6 +26,7 @@ properties:
>      enum:
>        - snps,ddrc-3.80a
>        - xlnx,zynqmp-ddrc-2.40a
> +      - baikal,bt1-ddrc

Messed order. Don't add stuff at the end, but in alphabetical order.

>  
>    interrupts:
>      description:
> @@ -49,7 +50,14 @@ properties:
>            enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
>  
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
> +
> +  reg-names:
> +    minItems: 1
> +    items:
> +      - const: umctl2
> +      - const: phy

You need allOf:if-then restricting this per variant.

Best regards,
Krzysztof