From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
Michal Simek <michal.simek@xilinx.com>,
Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Manish Narani <manish.narani@xilinx.com>
Cc: Serge Semin <fancer.lancer@gmail.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>,
Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>,
Dinh Nguyen <dinguyen@kernel.org>,
James Morse <james.morse@arm.com>,
Robert Richter <rric@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 01/13] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props
Date: Tue, 23 Aug 2022 11:11:08 +0300 [thread overview]
Message-ID: <6a803554-bc1a-9f53-b7e2-7571fffea7e0@linaro.org> (raw)
In-Reply-To: <20220822191957.28546-2-Sergey.Semin@baikalelectronics.ru>
On 22/08/2022 22:19, Serge Semin wrote:
> First of all the DW uMCTL2 DDRC IP-core supports the individual IRQ lines
> for each standard event: ECC Corrected Error, ECC Uncorrected Error, ECC
> Address Protection, Scrubber-Done signal, DFI Parity/CRC Error. It's
> possible that the platform engineers merge them up in the IRQ controller
> level. So let's add both configuration support to the DT-schema.
>
> Secondly each IP-core interface is supplied with a clock source like APB
> reference clock, AXI-ports clock, main DDRC core reference clock and
> Scrubber low-power clock. In addition to that each clock domain can have a
> dedicated reset signal. Let's add the properties for at least the denoted
> clock sources and the corresponding reset controls.
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> ---
> .../snps,dw-umctl2-ddrc.yaml | 65 +++++++++++++++++--
> 1 file changed, 60 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> index 787d91d64eee..8db92210cfe1 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> @@ -13,13 +13,13 @@ maintainers:
>
> description: |
> Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is cappable of
Typo in original text: capable
> - working with DDR devices up to (LP)DDR4 protocol. It can be equipped
> + working with DDR devices upporting to (LP)DDR4 protocol. It can be equipped
Typo - supporting?
> with SEC/DEC ECC feature if DRAM data bus width is either 16-bits or
> 32-bits or 64-bits wide.
>
> - The ZynqMP DDR controller is based on the DW uMCTL2 v2.40a controller.
> - It has an optional SEC/DEC ECC support in 64-bit and 32-bit bus width
> - configurations.
> + For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
> + controller. It has an optional SEC/DEC ECC support in 64-bit and 32-bit
> + bus width configurations.
These changes do not look related to your patch, so split them.
>
> properties:
> compatible:
> @@ -28,11 +28,55 @@ properties:
> - xlnx,zynqmp-ddrc-2.40a
>
> interrupts:
> - maxItems: 1
> + description:
> + DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
> + ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
> + Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
> + signals merged before they reach the IRQ controller or have some of them
> + absent in case if the corresponding feature is unavailable/disabled.
> + minItems: 1
> + maxItems: 5
List has to be strictly ordered, so instead list and describe the
items... unless you are sure that any of these interrupt lines can be
merged into any other one?
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 5
> + oneOf:
> + - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
> + items:
> + - const: ecc
> + - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
> + items:
> + enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
>
> reg:
> maxItems: 1
>
> + clocks:
> + description:
> + A standard set of the clock sources contains CSRs bus clock, AXI-ports
> + reference clock, DDRC core clock, Scrubber standalone clock
> + (synchronous to the DDRC clock).
> + minItems: 1
> + maxItems: 4
I expect list to be strictly defined, not flexible.
> +
> + clock-names:
> + minItems: 1
> + maxItems: 4
> + items:
> + enum: [ pclk, aclk, core, sbr ]
> +
> + resets:
> + description:
> + Each clock domain can have separate reset signal.
> + minItems: 1
> + maxItems: 4
> +
> + reset-names:
> + minItems: 1
> + maxItems: 4
> + items:
> + enum: [ prst, arst, core, sbr ]
The same.
> +
> required:
> - compatible
> - reg
> @@ -48,4 +92,15 @@ examples:
> interrupt-parent = <&gic>;
> interrupts = <0 112 4>;
> };
> + - |
> + memory-controller@fd070000 {
> + compatible = "snps,ddrc-3.80a";
> + reg = <0x3d400000 0x400000>;
> +
> + interrupts = <0 147 4>, <0 148 4>, <0 149 4>, <0 150 4>;
Use proper defines.
> + interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";
> +
> + clocks = <&rcu 0>, <&rcu 5>, <&rcu 6>, <&rcu 7>;
> + clock-names = "pclk", "aclk", "core", "sbr";
> + };
> ...
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-08-23 8:22 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-22 19:19 [PATCH 00/13] EDAC/synopsys: Add generic resources and Baikal-T1 support Serge Semin
2022-08-22 19:19 ` [PATCH 01/13] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props Serge Semin
2022-08-23 8:11 ` Krzysztof Kozlowski [this message]
2022-08-26 8:47 ` Serge Semin
2022-08-30 15:01 ` Krzysztof Kozlowski
2022-09-09 7:49 ` Serge Semin
2022-08-22 19:19 ` [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support Serge Semin
2022-08-23 8:12 ` Krzysztof Kozlowski
2022-08-26 9:54 ` Serge Semin
2022-09-05 10:14 ` Krzysztof Kozlowski
2022-09-08 9:46 ` Serge Semin
2022-09-08 9:58 ` Krzysztof Kozlowski
2022-09-08 15:08 ` Serge Semin
2022-09-08 15:27 ` Krzysztof Kozlowski
2022-09-08 15:40 ` Serge Semin
2022-08-30 18:00 ` Rob Herring
2022-09-09 12:57 ` Serge Semin
2022-08-22 19:19 ` [PATCH 03/13] EDAC/synopsys: Add multi-ranked memory support Serge Semin
2022-08-22 19:19 ` [PATCH 04/13] EDAC/synopsys: Add optional ECC Scrub support Serge Semin
2022-08-22 19:19 ` [PATCH 05/13] EDAC/synopsys: Drop ECC poison address from private data Serge Semin
2022-08-22 19:19 ` [PATCH 06/13] EDAC/synopsys: Add data poisoning disable support Serge Semin
2022-08-22 19:19 ` [PATCH 07/13] EDAC/synopsys: Split up ECC UE/CE IRQs handler Serge Semin
2022-08-22 19:19 ` [PATCH 08/13] EDAC/synopsys: Add individual named ECC IRQs support Serge Semin
2022-08-22 19:19 ` [PATCH 09/13] EDAC/synopsys: Add DFI alert_n IRQ support Serge Semin
2022-08-22 19:19 ` [PATCH 10/13] EDAC/synopsys: Add reference clocks support Serge Semin
2022-08-22 19:19 ` [PATCH 11/13] EDAC/synopsys: Add ECC Scrubber support Serge Semin
2022-08-22 19:19 ` [PATCH 12/13] EDAC/synopsys: Drop vendor-specific arch dependency Serge Semin
2022-08-22 19:19 ` [PATCH 13/13] EDAC/synopsys: Add Baikal-T1 DDRC support Serge Semin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6a803554-bc1a-9f53-b7e2-7571fffea7e0@linaro.org \
--to=krzysztof.kozlowski@linaro.org \
--cc=Alexey.Malahov@baikalelectronics.ru \
--cc=Michail.Ivanov@baikalelectronics.ru \
--cc=Pavel.Parkhomenko@baikalelectronics.ru \
--cc=Sergey.Semin@baikalelectronics.ru \
--cc=bp@alien8.de \
--cc=devicetree@vger.kernel.org \
--cc=dinguyen@kernel.org \
--cc=fancer.lancer@gmail.com \
--cc=james.morse@arm.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=manish.narani@xilinx.com \
--cc=mchehab@kernel.org \
--cc=michal.simek@xilinx.com \
--cc=punnaiah.choudary.kalluri@xilinx.com \
--cc=robh+dt@kernel.org \
--cc=rric@kernel.org \
--cc=tony.luck@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).