From: Serge Semin <fancer.lancer@gmail.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>,
Michal Simek <michal.simek@xilinx.com>,
Borislav Petkov <bp@alien8.de>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Tony Luck <tony.luck@intel.com>, Rob Herring <robh+dt@kernel.org>,
Manish Narani <manish.narani@xilinx.com>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Michail Ivanov <Michail.Ivanov@baikalelectronics.ru>,
Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com>,
Dinh Nguyen <dinguyen@kernel.org>,
James Morse <james.morse@arm.com>,
Robert Richter <rric@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support
Date: Fri, 26 Aug 2022 12:54:47 +0300 [thread overview]
Message-ID: <20220826095447.qxfvty6xq4tufe75@mobilestation> (raw)
In-Reply-To: <0bda4ff9-fc08-77f2-0e06-7469dcaec6d8@linaro.org>
On Tue, Aug 23, 2022 at 11:12:28AM +0300, Krzysztof Kozlowski wrote:
> On 22/08/2022 22:19, Serge Semin wrote:
> > Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a
> > with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There
> > are individual IRQs for each ECC and DFI events.The dedicated scrubber
>
> Missing space before "The".
Ok. Thanks.
>
> > clock source is absent since it's fully synchronous to the core clock.
>
> You need allOf:if-then restricting this per variant.
I really don't like the allOf-if-if-etc pattern because it gets to be
very bulky if all the vendor-specific and generic platform
peculiarities are placed in there. I am more keen of having a
generic DT-schema which would be then allOf-ed by the vendor-specific
device bindings. What do you think I'd provide such design in this
case too?
But I'll need to move the compatible property definition to the
"select" property. Like this:
Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml:
+[...]
+# Please create a separate DT-schema for your DW uMCTL2 DDR controller
+# and make sure it's assigned with the vendor-specific compatible string.
+select:
+ properties:
+ compatible:
+ oneOf:
+ - deprecated: true
+ description: Synopsys DW uMCTL2 DDR controller v3.80a
+ const: snps,ddrc-3.80a
+ - description: Synopsys DW uMCTL2 DDR controller
+ const: snps,dw-umctl2-ddrc
+ - description: Xilinx ZynqMP DDR controller v2.40a
+ const: xlnx,zynqmp-ddrc-2.40a
+ required:
+ - compatible
+
+properties:
+ compatible: true
+[...]
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: true
After that the "snps,dw-umctl2-ddrc.yaml" schema can be referenced in the
allOf composition. Like this:
Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml:
+[...]
+allOf:
+ - $ref: /schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
+[...]
At the same time the generic DT-schema will be used to evaluate the
"snps,ddrc-3.80a", "snps,dw-umctl2-ddrc" and "xlnx,zynqmp-ddrc-2.40a"
device nodes as before. What do you think about that?
One big positive side of this that even though the generic schema
can't define the IRQ/resets/clocks phandlers order because various
platforms may have different external signals setup, the
vendor-specific schema can and should. So I'll be able to describe the
Baikal-T1 DDRC specific properties (clocks, clock-names, interrupts,
interrupt-names, etc) in much more details including the reference
signals order what you asked in the previous patch review.
-Sergey
>
> > In addition to that the DFI-DDR PHY CSRs can be accessed via a separate
> > registers space.
> >
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > ---
> > .../memory-controllers/snps,dw-umctl2-ddrc.yaml | 10 +++++++++-
> > 1 file changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> > index 8db92210cfe1..899a6c5f9806 100644
> > --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> > +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
> > @@ -26,6 +26,7 @@ properties:
> > enum:
> > - snps,ddrc-3.80a
> > - xlnx,zynqmp-ddrc-2.40a
> > + - baikal,bt1-ddrc
>
> Messed order. Don't add stuff at the end, but in alphabetical order.
Ok. But could you please give me a reference with this requirement
documented? I've submitted many DT-bindings patches with the
compatible property updates and none of them received such comment
from Rob.
>
> >
> > interrupts:
> > description:
> > @@ -49,7 +50,14 @@ properties:
> > enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
> > +
> > + reg-names:
> > + minItems: 1
> > + items:
> > + - const: umctl2
> > + - const: phy
>
> You need allOf:if-then restricting this per variant.
Please see my comment above regarding possible solution of this.
-Sergey
>
> Best regards,
> Krzysztof
next prev parent reply other threads:[~2022-08-26 9:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-22 19:19 [PATCH 00/13] EDAC/synopsys: Add generic resources and Baikal-T1 support Serge Semin
2022-08-22 19:19 ` [PATCH 01/13] dt-bindings: memory: snps: Extend schema with IRQs/resets/clocks props Serge Semin
2022-08-23 8:11 ` Krzysztof Kozlowski
2022-08-26 8:47 ` Serge Semin
2022-08-30 15:01 ` Krzysztof Kozlowski
2022-09-09 7:49 ` Serge Semin
2022-08-22 19:19 ` [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support Serge Semin
2022-08-23 8:12 ` Krzysztof Kozlowski
2022-08-26 9:54 ` Serge Semin [this message]
2022-09-05 10:14 ` Krzysztof Kozlowski
2022-09-08 9:46 ` Serge Semin
2022-09-08 9:58 ` Krzysztof Kozlowski
2022-09-08 15:08 ` Serge Semin
2022-09-08 15:27 ` Krzysztof Kozlowski
2022-09-08 15:40 ` Serge Semin
2022-08-30 18:00 ` Rob Herring
2022-09-09 12:57 ` Serge Semin
2022-08-22 19:19 ` [PATCH 03/13] EDAC/synopsys: Add multi-ranked memory support Serge Semin
2022-08-22 19:19 ` [PATCH 04/13] EDAC/synopsys: Add optional ECC Scrub support Serge Semin
2022-08-22 19:19 ` [PATCH 05/13] EDAC/synopsys: Drop ECC poison address from private data Serge Semin
2022-08-22 19:19 ` [PATCH 06/13] EDAC/synopsys: Add data poisoning disable support Serge Semin
2022-08-22 19:19 ` [PATCH 07/13] EDAC/synopsys: Split up ECC UE/CE IRQs handler Serge Semin
2022-08-22 19:19 ` [PATCH 08/13] EDAC/synopsys: Add individual named ECC IRQs support Serge Semin
2022-08-22 19:19 ` [PATCH 09/13] EDAC/synopsys: Add DFI alert_n IRQ support Serge Semin
2022-08-22 19:19 ` [PATCH 10/13] EDAC/synopsys: Add reference clocks support Serge Semin
2022-08-22 19:19 ` [PATCH 11/13] EDAC/synopsys: Add ECC Scrubber support Serge Semin
2022-08-22 19:19 ` [PATCH 12/13] EDAC/synopsys: Drop vendor-specific arch dependency Serge Semin
2022-08-22 19:19 ` [PATCH 13/13] EDAC/synopsys: Add Baikal-T1 DDRC support Serge Semin
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