* [PATCH v2 1/5] dt-bindings: arm: bcm: NSP: add Meraki MX64/MX65
2021-06-10 23:27 [PATCH v2 0/5] ARM: dts: NSP: add Meraki MX64/MX65 Matthew Hagan
@ 2021-06-10 23:27 ` Matthew Hagan
2021-06-11 19:46 ` Vladimir Oltean
2021-06-10 23:27 ` [PATCH v2 2/5] ARM: dts: NSP: Add Meraki MX64/MX65 to Makefile Matthew Hagan
` (3 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Matthew Hagan @ 2021-06-10 23:27 UTC (permalink / raw)
Cc: Florian Fainelli, Vladimir Oltean, Andrew Lunn, Matthew Hagan,
Rob Herring, Arnd Bergmann, Olof Johansson, soc, Ray Jui,
Scott Branden, bcm-kernel-feedback-list, Geert Uytterhoeven,
Krzysztof Kozlowski, Sam Ravnborg, devicetree, linux-kernel,
linux-arm-kernel
Add bindings for the Meraki MX64/MX65 series. Note this patch should be
applied on top of "dt-bindings: arm: bcm: add NSP devices to SoCs".
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
index 78dfa315f3d0..7d184ba7d180 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
@@ -62,6 +62,12 @@ properties:
- enum:
- brcm,bcm958625hr
- brcm,bcm958625k
+ - meraki,mx64
+ - meraki,mx64-a0
+ - meraki,mx64w
+ - meraki,mx64w-a0
+ - meraki,mx65
+ - meraki,mx65w
- const: brcm,bcm58625
- const: brcm,nsp
--
2.26.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 1/5] dt-bindings: arm: bcm: NSP: add Meraki MX64/MX65
2021-06-10 23:27 ` [PATCH v2 1/5] dt-bindings: arm: bcm: " Matthew Hagan
@ 2021-06-11 19:46 ` Vladimir Oltean
2021-06-12 9:21 ` Matthew Hagan
0 siblings, 1 reply; 16+ messages in thread
From: Vladimir Oltean @ 2021-06-11 19:46 UTC (permalink / raw)
To: Matthew Hagan
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Geert Uytterhoeven,
Krzysztof Kozlowski, Sam Ravnborg, devicetree, linux-kernel,
linux-arm-kernel
On Fri, Jun 11, 2021 at 12:27:13AM +0100, Matthew Hagan wrote:
> Add bindings for the Meraki MX64/MX65 series. Note this patch should be
> applied on top of "dt-bindings: arm: bcm: add NSP devices to SoCs".
>
> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
> index 78dfa315f3d0..7d184ba7d180 100644
> --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
> @@ -62,6 +62,12 @@ properties:
> - enum:
> - brcm,bcm958625hr
> - brcm,bcm958625k
> + - meraki,mx64
> + - meraki,mx64-a0
> + - meraki,mx64w
> + - meraki,mx64w-a0
> + - meraki,mx65
> + - meraki,mx65w
> - const: brcm,bcm58625
> - const: brcm,nsp
>
> --
> 2.26.3
>
I think these compatibles describe SoCs, whereas Meraki MX64/MX65 are
boards, so this is a miscategorization. Can you not just describe the
Northstar Plus SoC that you are using in your compatible string?
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: arm: bcm: NSP: add Meraki MX64/MX65
2021-06-11 19:46 ` Vladimir Oltean
@ 2021-06-12 9:21 ` Matthew Hagan
2021-06-12 15:07 ` Vladimir Oltean
0 siblings, 1 reply; 16+ messages in thread
From: Matthew Hagan @ 2021-06-12 9:21 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Geert Uytterhoeven,
Krzysztof Kozlowski, Sam Ravnborg, devicetree, linux-kernel,
linux-arm-kernel
Hi Vladimir,
Many thanks for taking the time to review the submission.
On 11/06/2021 20:46, Vladimir Oltean wrote:
> On Fri, Jun 11, 2021 at 12:27:13AM +0100, Matthew Hagan wrote:
>> Add bindings for the Meraki MX64/MX65 series. Note this patch should be
>> applied on top of "dt-bindings: arm: bcm: add NSP devices to SoCs".
>>
>> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
>> ---
>> Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
>> index 78dfa315f3d0..7d184ba7d180 100644
>> --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
>> @@ -62,6 +62,12 @@ properties:
>> - enum:
>> - brcm,bcm958625hr
>> - brcm,bcm958625k
>> + - meraki,mx64
>> + - meraki,mx64-a0
>> + - meraki,mx64w
>> + - meraki,mx64w-a0
>> + - meraki,mx65
>> + - meraki,mx65w
>> - const: brcm,bcm58625
>> - const: brcm,nsp
>>
>> --
>> 2.26.3
>>
> I think these compatibles describe SoCs, whereas Meraki MX64/MX65 are
> boards, so this is a miscategorization. Can you not just describe the
> Northstar Plus SoC that you are using in your compatible string?
My understanding is that the bcm958625hr and bcm958625k are dev boards
using the BCM58625 SoC variant of NSP. For reference, a close example
can be found in brcm,bcm4708.yaml in the same directory:
- description: BCM53012 based boards
items:
- enum:
- brcm,bcm953012er
- brcm,bcm953012hr
- brcm,bcm953012k
- meraki,mr32
- const: brcm,brcm53012
- const: brcm,brcm53016
- const: brcm,bcm4708
For the compatible string we would definitely need to specify a unique
device name for identification by the OS, rather than just the SoC.
Of course I could be mistaken. Will await confirmation on this.
Matthew
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 1/5] dt-bindings: arm: bcm: NSP: add Meraki MX64/MX65
2021-06-12 9:21 ` Matthew Hagan
@ 2021-06-12 15:07 ` Vladimir Oltean
0 siblings, 0 replies; 16+ messages in thread
From: Vladimir Oltean @ 2021-06-12 15:07 UTC (permalink / raw)
To: Matthew Hagan
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Geert Uytterhoeven,
Krzysztof Kozlowski, Sam Ravnborg, devicetree, linux-kernel,
linux-arm-kernel
On Sat, Jun 12, 2021 at 10:21:31AM +0100, Matthew Hagan wrote:
> Hi Vladimir,
>
> Many thanks for taking the time to review the submission.
>
> On 11/06/2021 20:46, Vladimir Oltean wrote:
>
> > On Fri, Jun 11, 2021 at 12:27:13AM +0100, Matthew Hagan wrote:
> >> Add bindings for the Meraki MX64/MX65 series. Note this patch should be
> >> applied on top of "dt-bindings: arm: bcm: add NSP devices to SoCs".
> >>
> >> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> >> ---
> >> Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml | 6 ++++++
> >> 1 file changed, 6 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
> >> index 78dfa315f3d0..7d184ba7d180 100644
> >> --- a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
> >> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml
> >> @@ -62,6 +62,12 @@ properties:
> >> - enum:
> >> - brcm,bcm958625hr
> >> - brcm,bcm958625k
> >> + - meraki,mx64
> >> + - meraki,mx64-a0
> >> + - meraki,mx64w
> >> + - meraki,mx64w-a0
> >> + - meraki,mx65
> >> + - meraki,mx65w
> >> - const: brcm,bcm58625
> >> - const: brcm,nsp
> >>
> >> --
> >> 2.26.3
> >>
> > I think these compatibles describe SoCs, whereas Meraki MX64/MX65 are
> > boards, so this is a miscategorization. Can you not just describe the
> > Northstar Plus SoC that you are using in your compatible string?
>
> My understanding is that the bcm958625hr and bcm958625k are dev boards
> using the BCM58625 SoC variant of NSP. For reference, a close example
> can be found in brcm,bcm4708.yaml in the same directory:
>
> - description: BCM53012 based boards
> items:
> - enum:
> - brcm,bcm953012er
> - brcm,bcm953012hr
> - brcm,bcm953012k
> - meraki,mr32
> - const: brcm,brcm53012
> - const: brcm,brcm53016
> - const: brcm,bcm4708
>
> For the compatible string we would definitely need to specify a unique
> device name for identification by the OS, rather than just the SoC.
>
> Of course I could be mistaken. Will await confirmation on this.
Yeah, ok, fair, after rechecking I think you're right. I'm dropping this charge.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 2/5] ARM: dts: NSP: Add Meraki MX64/MX65 to Makefile
2021-06-10 23:27 [PATCH v2 0/5] ARM: dts: NSP: add Meraki MX64/MX65 Matthew Hagan
2021-06-10 23:27 ` [PATCH v2 1/5] dt-bindings: arm: bcm: " Matthew Hagan
@ 2021-06-10 23:27 ` Matthew Hagan
2021-06-11 20:24 ` Vladimir Oltean
2021-06-10 23:27 ` [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65 Matthew Hagan
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Matthew Hagan @ 2021-06-10 23:27 UTC (permalink / raw)
Cc: Florian Fainelli, Vladimir Oltean, Andrew Lunn, Matthew Hagan,
Rob Herring, Arnd Bergmann, Olof Johansson, soc, Ray Jui,
Scott Branden, bcm-kernel-feedback-list, Krzysztof Kozlowski,
Viresh Kumar, Sam Ravnborg, devicetree, linux-kernel,
linux-arm-kernel
Add Makefile entries for the Meraki MX64/MX65 series devices.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
arch/arm/boot/dts/Makefile | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f8f09c5066e7..033d9604db60 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -154,6 +154,12 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
bcm958525xmc.dtb \
bcm958622hr.dtb \
bcm958623hr.dtb \
+ bcm958625-meraki-mx64.dtb \
+ bcm958625-meraki-mx64-a0.dtb \
+ bcm958625-meraki-mx64w.dtb \
+ bcm958625-meraki-mx64w-a0.dtb \
+ bcm958625-meraki-mx65.dtb \
+ bcm958625-meraki-mx65w.dtb \
bcm958625hr.dtb \
bcm988312hr.dtb \
bcm958625k.dtb
--
2.26.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 2/5] ARM: dts: NSP: Add Meraki MX64/MX65 to Makefile
2021-06-10 23:27 ` [PATCH v2 2/5] ARM: dts: NSP: Add Meraki MX64/MX65 to Makefile Matthew Hagan
@ 2021-06-11 20:24 ` Vladimir Oltean
2021-06-12 9:23 ` Matthew Hagan
0 siblings, 1 reply; 16+ messages in thread
From: Vladimir Oltean @ 2021-06-11 20:24 UTC (permalink / raw)
To: Matthew Hagan
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Krzysztof Kozlowski, Viresh Kumar,
Sam Ravnborg, devicetree, linux-kernel, linux-arm-kernel
On Fri, Jun 11, 2021 at 12:27:14AM +0100, Matthew Hagan wrote:
> Add Makefile entries for the Meraki MX64/MX65 series devices.
>
> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> ---
> arch/arm/boot/dts/Makefile | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f8f09c5066e7..033d9604db60 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -154,6 +154,12 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
> bcm958525xmc.dtb \
> bcm958622hr.dtb \
> bcm958623hr.dtb \
> + bcm958625-meraki-mx64.dtb \
> + bcm958625-meraki-mx64-a0.dtb \
> + bcm958625-meraki-mx64w.dtb \
> + bcm958625-meraki-mx64w-a0.dtb \
> + bcm958625-meraki-mx65.dtb \
> + bcm958625-meraki-mx65w.dtb \
> bcm958625hr.dtb \
> bcm988312hr.dtb \
> bcm958625k.dtb
> --
> 2.26.3
>
It is odd to add the device trees to the Makefile in a separate patch
compared to their actual introduction. Does the tree even compile at
this stage?
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/5] ARM: dts: NSP: Add Meraki MX64/MX65 to Makefile
2021-06-11 20:24 ` Vladimir Oltean
@ 2021-06-12 9:23 ` Matthew Hagan
0 siblings, 0 replies; 16+ messages in thread
From: Matthew Hagan @ 2021-06-12 9:23 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Krzysztof Kozlowski, Viresh Kumar,
Sam Ravnborg, devicetree, linux-kernel, linux-arm-kernel
On 11/06/2021 21:24, Vladimir Oltean wrote:
> On Fri, Jun 11, 2021 at 12:27:14AM +0100, Matthew Hagan wrote:
>> Add Makefile entries for the Meraki MX64/MX65 series devices.
>>
>> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
>> ---
>> arch/arm/boot/dts/Makefile | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index f8f09c5066e7..033d9604db60 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -154,6 +154,12 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
>> bcm958525xmc.dtb \
>> bcm958622hr.dtb \
>> bcm958623hr.dtb \
>> + bcm958625-meraki-mx64.dtb \
>> + bcm958625-meraki-mx64-a0.dtb \
>> + bcm958625-meraki-mx64w.dtb \
>> + bcm958625-meraki-mx64w-a0.dtb \
>> + bcm958625-meraki-mx65.dtb \
>> + bcm958625-meraki-mx65w.dtb \
>> bcm958625hr.dtb \
>> bcm988312hr.dtb \
>> bcm958625k.dtb
>> --
>> 2.26.3
>>
> It is odd to add the device trees to the Makefile in a separate patch
> compared to their actual introduction. Does the tree even compile at
> this stage?
Will rectify this. Thanks!
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65
2021-06-10 23:27 [PATCH v2 0/5] ARM: dts: NSP: add Meraki MX64/MX65 Matthew Hagan
2021-06-10 23:27 ` [PATCH v2 1/5] dt-bindings: arm: bcm: " Matthew Hagan
2021-06-10 23:27 ` [PATCH v2 2/5] ARM: dts: NSP: Add Meraki MX64/MX65 to Makefile Matthew Hagan
@ 2021-06-10 23:27 ` Matthew Hagan
2021-06-11 20:30 ` Vladimir Oltean
2021-06-10 23:27 ` [PATCH v2 4/5] ARM: dts: NSP: Add DT files for Meraki MX64 series Matthew Hagan
2021-06-10 23:27 ` [PATCH v2 5/5] ARM: dts: NSP: Add DT files for Meraki MX65 series Matthew Hagan
4 siblings, 1 reply; 16+ messages in thread
From: Matthew Hagan @ 2021-06-10 23:27 UTC (permalink / raw)
Cc: Florian Fainelli, Vladimir Oltean, Andrew Lunn, Matthew Hagan,
Rob Herring, Arnd Bergmann, Olof Johansson, soc, Ray Jui,
Scott Branden, bcm-kernel-feedback-list, Sam Ravnborg,
Geert Uytterhoeven, Viresh Kumar, devicetree, linux-kernel,
linux-arm-kernel
These bindings are required for all Meraki MX64/MX65 devices.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
.../dts/bcm958625-meraki-mx6x-common.dtsi | 148 ++++++++++++++++++
1 file changed, 148 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
new file mode 100644
index 000000000000..47a30dedf7b3
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm-nsp.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ red {
+ label = "red:led";
+ pwms = <&pwm 1 50000>;
+ };
+
+ green {
+ label = "green:led";
+ pwms = <&pwm 2 50000>;
+ };
+
+ blue {
+ label = "blue:led";
+ pwms = <&pwm 3 50000>;
+ };
+ };
+};
+
+&L2 {
+ arm,io-coherent;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+};
+
+&uart0 {
+ clock-frequency = <62500000>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ at24@50 {
+ compatible = "atmel,24c64";
+ pagesize = <32>;
+ reg = <0x50>;
+ };
+};
+
+&amac2 {
+ status = "okay";
+};
+
+&nand {
+ nandcs@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-ecc-strength = <24>;
+ nand-ecc-step-size = <1024>;
+
+ brcm,nand-oob-sector-size = <27>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "shmoo";
+ reg = <0x80000 0x80000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "bootkernel1";
+ reg = <0x100000 0x300000>;
+ };
+
+ partition@400000 {
+ label = "senao_nvram";
+ reg = <0x400000 0x100000>;
+ };
+
+ partition@500000 {
+ label = "bootkernel2";
+ reg = <0x500000 0x300000>;
+ };
+
+ partition@800000 {
+ label = "ubi";
+ reg = <0x800000 0x3f700000>;
+ };
+ };
+};
+
+&qspi {
+ status = "disabled";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pwm {
+ status = "okay";
+ #pwm-cells = <2>;
+ chan0 {
+ channel = <1>;
+ active_low = <1>;
+ };
+ chan1 {
+ channel = <2>;
+ active_low = <1>;
+ };
+ chan2 {
+ channel = <3>;
+ active_low = <1>;
+ };
+};
+
+&ccbtimer1 {
+ status = "disabled";
+};
+
+&sata_phy {
+ status = "disabled";
+};
--
2.26.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65
2021-06-10 23:27 ` [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65 Matthew Hagan
@ 2021-06-11 20:30 ` Vladimir Oltean
2021-06-12 23:14 ` Matthew Hagan
0 siblings, 1 reply; 16+ messages in thread
From: Vladimir Oltean @ 2021-06-11 20:30 UTC (permalink / raw)
To: Matthew Hagan
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Sam Ravnborg, Geert Uytterhoeven,
Viresh Kumar, devicetree, linux-kernel, linux-arm-kernel
On Fri, Jun 11, 2021 at 12:27:15AM +0100, Matthew Hagan wrote:
> These bindings are required for all Meraki MX64/MX65 devices.
>
> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> ---
> .../dts/bcm958625-meraki-mx6x-common.dtsi | 148 ++++++++++++++++++
> 1 file changed, 148 insertions(+)
> create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
>
> diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
> new file mode 100644
> index 000000000000..47a30dedf7b3
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
> @@ -0,0 +1,148 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.
> + *
> + * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
> + */
> +
> +#include "bcm-nsp.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x60000000 0x80000000>;
> + };
> +
> + pwm-leds {
> + compatible = "pwm-leds";
> +
> + red {
> + label = "red:led";
> + pwms = <&pwm 1 50000>;
> + };
> +
> + green {
> + label = "green:led";
> + pwms = <&pwm 2 50000>;
> + };
> +
> + blue {
> + label = "blue:led";
> + pwms = <&pwm 3 50000>;
> + };
> + };
> +};
> +
> +&L2 {
> + arm,io-coherent;
> + prefetch-data = <1>;
> + prefetch-instr = <1>;
> +};
It is common practice to sort labels alphabetically and nodes by unit address.
> +
> +&uart0 {
> + clock-frequency = <62500000>;
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + at24@50 {
> + compatible = "atmel,24c64";
> + pagesize = <32>;
> + reg = <0x50>;
> + };
> +};
> +
> +&amac2 {
> + status = "okay";
> +};
> +
> +&nand {
> + nandcs@0 {
> + compatible = "brcm,nandcs";
> + reg = <0>;
> + nand-on-flash-bbt;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + nand-ecc-strength = <24>;
> + nand-ecc-step-size = <1024>;
> +
> + brcm,nand-oob-sector-size = <27>;
> +
> + partition@0 {
> + label = "u-boot";
> + reg = <0x0 0x80000>;
> + read-only;
> + };
> +
> + partition@80000 {
> + label = "shmoo";
> + reg = <0x80000 0x80000>;
> + read-only;
> + };
> +
> + partition@100000 {
> + label = "bootkernel1";
> + reg = <0x100000 0x300000>;
> + };
> +
> + partition@400000 {
> + label = "senao_nvram";
> + reg = <0x400000 0x100000>;
> + };
> +
> + partition@500000 {
> + label = "bootkernel2";
> + reg = <0x500000 0x300000>;
> + };
> +
> + partition@800000 {
> + label = "ubi";
> + reg = <0x800000 0x3f700000>;
> + };
> + };
> +};
> +
> +&qspi {
> + status = "disabled";
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&pwm {
> + status = "okay";
> + #pwm-cells = <2>;
What is the reason for overriding this to 2?
> + chan0 {
> + channel = <1>;
> + active_low = <1>;
> + };
Bad indentation for this bracket.
> + chan1 {
> + channel = <2>;
> + active_low = <1>;
> + };
> + chan2 {
> + channel = <3>;
> + active_low = <1>;
> + };
> +};
> +
> +&ccbtimer1 {
> + status = "disabled";
> +};
> +
> +&sata_phy {
> + status = "disabled";
> +};
It is common practice to disable these in the common SoC dtsi and let
individual boards enable them as necessary, instead of the opposite.
> --
> 2.26.3
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65
2021-06-11 20:30 ` Vladimir Oltean
@ 2021-06-12 23:14 ` Matthew Hagan
2021-06-13 2:03 ` Florian Fainelli
0 siblings, 1 reply; 16+ messages in thread
From: Matthew Hagan @ 2021-06-12 23:14 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Sam Ravnborg, Geert Uytterhoeven,
Viresh Kumar, devicetree, linux-kernel, linux-arm-kernel
On 11/06/2021 21:30, Vladimir Oltean wrote:
> On Fri, Jun 11, 2021 at 12:27:15AM +0100, Matthew Hagan wrote:
>> These bindings are required for all Meraki MX64/MX65 devices.
>>
>> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
>> ---
>> .../dts/bcm958625-meraki-mx6x-common.dtsi | 148 ++++++++++++++++++
>> 1 file changed, 148 insertions(+)
>> create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
>>
>> diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
>> new file mode 100644
>> index 000000000000..47a30dedf7b3
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi
>> @@ -0,0 +1,148 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>> +/*
>> + * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.
>> + *
>> + * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
>> + */
>> +
>> +#include "bcm-nsp.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory {
>> + device_type = "memory";
>> + reg = <0x60000000 0x80000000>;
>> + };
>> +
>> + pwm-leds {
>> + compatible = "pwm-leds";
>> +
>> + red {
>> + label = "red:led";
>> + pwms = <&pwm 1 50000>;
>> + };
>> +
>> + green {
>> + label = "green:led";
>> + pwms = <&pwm 2 50000>;
>> + };
>> +
>> + blue {
>> + label = "blue:led";
>> + pwms = <&pwm 3 50000>;
>> + };
>> + };
>> +};
>> +
>> +&L2 {
>> + arm,io-coherent;
>> + prefetch-data = <1>;
>> + prefetch-instr = <1>;
>> +};
> It is common practice to sort labels alphabetically and nodes by unit address.
This will be done. Thanks.
>
>> +
>> +&uart0 {
>> + clock-frequency = <62500000>;
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> + at24@50 {
>> + compatible = "atmel,24c64";
>> + pagesize = <32>;
>> + reg = <0x50>;
>> + };
>> +};
>> +
>> +&amac2 {
>> + status = "okay";
>> +};
>> +
>> +&nand {
>> + nandcs@0 {
>> + compatible = "brcm,nandcs";
>> + reg = <0>;
>> + nand-on-flash-bbt;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + nand-ecc-strength = <24>;
>> + nand-ecc-step-size = <1024>;
>> +
>> + brcm,nand-oob-sector-size = <27>;
>> +
>> + partition@0 {
>> + label = "u-boot";
>> + reg = <0x0 0x80000>;
>> + read-only;
>> + };
>> +
>> + partition@80000 {
>> + label = "shmoo";
>> + reg = <0x80000 0x80000>;
>> + read-only;
>> + };
>> +
>> + partition@100000 {
>> + label = "bootkernel1";
>> + reg = <0x100000 0x300000>;
>> + };
>> +
>> + partition@400000 {
>> + label = "senao_nvram";
>> + reg = <0x400000 0x100000>;
>> + };
>> +
>> + partition@500000 {
>> + label = "bootkernel2";
>> + reg = <0x500000 0x300000>;
>> + };
>> +
>> + partition@800000 {
>> + label = "ubi";
>> + reg = <0x800000 0x3f700000>;
>> + };
>> + };
>> +};
>> +
>> +&qspi {
>> + status = "disabled";
>> +};
>> +
>> +&ehci0 {
>> + status = "okay";
>> +};
>> +
>> +&ohci0 {
>> + status = "okay";
>> +};
>> +
>> +&pwm {
>> + status = "okay";
>> + #pwm-cells = <2>;
> What is the reason for overriding this to 2?
I can't provide an explanation other than that it only works at 2.
When set to 3 I get the following:
[ 0.784051] OF: /pwm-leds/red: #pwm-cells = 3 found -1
[ 0.789201] of_pwm_get(): can't parse "pwms" property
[ 0.794295] leds_pwm pwm-leds: error -EINVAL: unable to request PWM for red:led
[ 0.801628] leds_pwm: probe of pwm-leds failed with error -22
>> + chan0 {
>> + channel = <1>;
>> + active_low = <1>;
>> + };
> Bad indentation for this bracket.
This will be removed in v3
>
>> + chan1 {
>> + channel = <2>;
>> + active_low = <1>;
>> + };
>> + chan2 {
>> + channel = <3>;
>> + active_low = <1>;
>> + };
>> +};
>> +
>> +&ccbtimer1 {
>> + status = "disabled";
>> +};
>> +
>> +&sata_phy {
>> + status = "disabled";
>> +};
> It is common practice to disable these in the common SoC dtsi and let
> individual boards enable them as necessary, instead of the opposite.
Will add patches in v3 to disable ccbtimers and qspi by default. The sata_phy one is not required.
>
>> --
>> 2.26.3
>>
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65
2021-06-12 23:14 ` Matthew Hagan
@ 2021-06-13 2:03 ` Florian Fainelli
0 siblings, 0 replies; 16+ messages in thread
From: Florian Fainelli @ 2021-06-13 2:03 UTC (permalink / raw)
To: Matthew Hagan, Vladimir Oltean
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Sam Ravnborg, Geert Uytterhoeven,
Viresh Kumar, devicetree, linux-kernel, linux-arm-kernel
On 6/12/2021 4:14 PM, Matthew Hagan wrote:
[snip]
>>> + pwm-leds {
>>> + compatible = "pwm-leds";
>>> +
>>> + red {
>>> + label = "red:led";
>>> + pwms = <&pwm 1 50000>;
>>> + };
>>> +
>>> + green {
>>> + label = "green:led";
>>> + pwms = <&pwm 2 50000>;
>>> + };
>>> +
>>> + blue {
>>> + label = "blue:led";
>>> + pwms = <&pwm 3 50000>;
>>> + };
>>> + };
[snip]
>> What is the reason for overriding this to 2?
>
> I can't provide an explanation other than that it only works at 2.
>
> When set to 3 I get the following:
>
> [ 0.784051] OF: /pwm-leds/red: #pwm-cells = 3 found -1
> [ 0.789201] of_pwm_get(): can't parse "pwms" property
> [ 0.794295] leds_pwm pwm-leds: error -EINVAL: unable to request PWM for red:led
> [ 0.801628] leds_pwm: probe of pwm-leds failed with error -22
Strange because with a #pwm-cells value of 3, of_pwm_xlate_with_flags()
would treat the flags as optional so the way you have put it looks
correct to me. I am not sure what the channel sub-nodes are supposed to
do, they do not appear to be documented properties or parsed by the PWM
core?
Is your Device Tree possibly corrupted here?
--
Florian
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 4/5] ARM: dts: NSP: Add DT files for Meraki MX64 series
2021-06-10 23:27 [PATCH v2 0/5] ARM: dts: NSP: add Meraki MX64/MX65 Matthew Hagan
` (2 preceding siblings ...)
2021-06-10 23:27 ` [PATCH v2 3/5] ARM: dts: NSP: Add common bindings for MX64/MX65 Matthew Hagan
@ 2021-06-10 23:27 ` Matthew Hagan
2021-06-10 23:27 ` [PATCH v2 5/5] ARM: dts: NSP: Add DT files for Meraki MX65 series Matthew Hagan
4 siblings, 0 replies; 16+ messages in thread
From: Matthew Hagan @ 2021-06-10 23:27 UTC (permalink / raw)
Cc: Florian Fainelli, Vladimir Oltean, Andrew Lunn, Matthew Hagan,
Rob Herring, Arnd Bergmann, Olof Johansson, soc, Ray Jui,
Scott Branden, bcm-kernel-feedback-list, Viresh Kumar,
Krzysztof Kozlowski, Geert Uytterhoeven, devicetree,
linux-kernel, linux-arm-kernel
MX64 Hardware info:
- CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz
- RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)
- Storage: 1 GB (Micron MT29F8G08ABACA)
- Networking: BCM58625 internal switch (5x 1GbE ports)
- USB: 1x USB2.0
- Serial: Internal header
This patch adds the Meraki MX64 series. Since some devices make use of
the older A0 SoC, changes need to be made to accommodate this device,
including removal of dma-coherent and change in the secondary-cpu
address. The MX64W devices have 2x Broadcom BCM43520KMLG on the PCI bus.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
.../boot/dts/bcm958625-meraki-kingpin.dtsi | 131 ++++++++++++++++++
.../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 45 ++++++
arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 15 ++
.../boot/dts/bcm958625-meraki-mx64w-a0.dts | 55 ++++++++
arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 23 +++
5 files changed, 269 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts
diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
new file mode 100644
index 000000000000..8c4834f3496b
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin).
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm958625-meraki-mx6x-common.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+
+ orange_power {
+ label = "orange:power";
+ gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ lan1_right {
+ label = "green:lan1-right";
+ gpios = <&gpioa 18 GPIO_ACTIVE_LOW>;
+ };
+
+ lan1_left {
+ label = "green:lan1-left";
+ gpios = <&gpioa 19 GPIO_ACTIVE_LOW>;
+ };
+
+ lan2_right {
+ label = "green:lan2-right";
+ gpios = <&gpioa 20 GPIO_ACTIVE_LOW>;
+ };
+
+ lan2_left {
+ label = "green:lan2-left";
+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
+ };
+
+ lan3_right {
+ label = "green:lan3-right";
+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
+ };
+
+ lan3_left {
+ label = "green:lan3-left";
+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
+ };
+
+ lan4_right {
+ label = "green:lan4-right";
+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
+ };
+
+ lan4_left {
+ label = "green:lan4-left";
+ gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
+ };
+
+ wan_right {
+ label = "green:wan-right";
+ gpios = <&gpioa 29 GPIO_ACTIVE_LOW>;
+ };
+
+ wan_left {
+ label = "green:wan-left";
+ gpios = <&gpioa 30 GPIO_ACTIVE_LOW>;
+ };
+
+ white_status {
+ label = "white:status";
+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ autorepeat;
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&srab {
+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
+ status = "okay";
+
+ ports {
+ port@0 {
+ label = "lan1";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "lan2";
+ reg = <1>;
+ };
+
+ port@2 {
+ label = "lan3";
+ reg = <2>;
+ };
+
+ port@3 {
+ label = "lan4";
+ reg = <3>;
+ };
+
+ port@4 {
+ label = "wan";
+ reg = <4>;
+ };
+
+ port@8 {
+ ethernet = <&amac2>;
+ label = "cpu";
+ reg = <8>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts
new file mode 100644
index 000000000000..aed9eb9fccd7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC.
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64(A0)";
+ compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";
+};
+
+&cpu1 {
+ secondary-boot-reg = <0xffff042c>;
+};
+
+&L2 {
+ /delete-property/ arm,io-coherent;
+ /delete-property/ prefetch-data;
+ /delete-property/ prefetch-instr;
+};
+
+&amac2 {
+ /delete-property/ dma-coherent;
+};
+
+&mailbox {
+ /delete-property/ dma-coherent;
+};
+
+&ehci0 {
+ /delete-property/ dma-coherent;
+};
+
+&ohci0 {
+ /delete-property/ dma-coherent;
+};
+
+&i2c0 {
+ /delete-property/ dma-coherent;
+};
diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts
new file mode 100644
index 000000000000..fe787fd7d660
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64";
+ compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp";
+};
diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts
new file mode 100644
index 000000000000..b7d88c542943
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC.
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64(A0)";
+ compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";
+};
+
+&cpu1 {
+ secondary-boot-reg = <0xffff042c>;
+};
+
+&L2 {
+ /delete-property/ arm,io-coherent;
+ /delete-property/ prefetch-data;
+ /delete-property/ prefetch-instr;
+};
+
+&amac2 {
+ /delete-property/ dma-coherent;
+};
+
+&mailbox {
+ /delete-property/ dma-coherent;
+};
+
+&ehci0 {
+ /delete-property/ dma-coherent;
+};
+
+&ohci0 {
+ /delete-property/ dma-coherent;
+};
+
+&i2c0 {
+ /delete-property/ dma-coherent;
+};
+
+&pcie0 {
+ /delete-property/ dma-coherent;
+ status = "okay";
+};
+
+&pcie1 {
+ /delete-property/ dma-coherent;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts
new file mode 100644
index 000000000000..aa29c96f2871
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC.
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-kingpin.dtsi"
+
+/ {
+ model = "Cisco Meraki MX64W";
+ compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
--
2.26.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 5/5] ARM: dts: NSP: Add DT files for Meraki MX65 series
2021-06-10 23:27 [PATCH v2 0/5] ARM: dts: NSP: add Meraki MX64/MX65 Matthew Hagan
` (3 preceding siblings ...)
2021-06-10 23:27 ` [PATCH v2 4/5] ARM: dts: NSP: Add DT files for Meraki MX64 series Matthew Hagan
@ 2021-06-10 23:27 ` Matthew Hagan
2021-06-11 19:02 ` Matthew Hagan
2021-06-11 20:48 ` Vladimir Oltean
4 siblings, 2 replies; 16+ messages in thread
From: Matthew Hagan @ 2021-06-10 23:27 UTC (permalink / raw)
Cc: Florian Fainelli, Vladimir Oltean, Andrew Lunn, Matthew Hagan,
Rob Herring, Arnd Bergmann, Olof Johansson, soc, Ray Jui,
Scott Branden, bcm-kernel-feedback-list, Geert Uytterhoeven,
Sam Ravnborg, Viresh Kumar, devicetree, linux-kernel,
linux-arm-kernel
MX65 Hardware info:
- CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz
- RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)
- Storage: 1 GB (Micron MT29F8G08ABACA)
- Networking: BCM58625 switch (2x 1GbE ports, used for WAN ports 1 & 2)
2x Qualcomm QCA8337 switches (10x 1GbE ports, used for LAN ports 3-12)
- PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12
- USB: 1x USB2.0
- Serial: Internal header
As with the MX64, the MX65 has 2x Broadcom BCM43520KMLG on the PCI bus.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 298 ++++++++++++++++++
arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 15 +
arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 23 ++
3 files changed, 336 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts
create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
new file mode 100644
index 000000000000..0ff78fb89b6d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+#include "bcm958625-meraki-mx6x-common.dtsi"
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ mdio-mux-mmio = &mdiomux0;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ orange_power {
+ label = "orange:power";
+ gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ wan1_right {
+ label = "green:wan1-right";
+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
+ };
+
+ wan1_left {
+ label = "green:wan1-left";
+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
+ };
+
+ wan2_right {
+ label = "green:wan2-right";
+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
+ };
+
+ wan2_left {
+ label = "green:wan2-left";
+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
+ };
+
+ white_status {
+ label = "white:status";
+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ autorepeat;
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ mdio: mdio@18032000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x18032000 0x8>;
+ #size-cells = <0>;
+ #address-cells = <1>;
+ };
+
+ mdiomux0: mdio-mux {
+ compatible = "mdio-mux-mmioreg";
+ reg = <0x18032000 0x4>;
+ mux-mask = <0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mdio-parent-bus = <&mdio>;
+
+ mdio_ext: mdio@200 {
+ reg = <0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio-mii-mux {
+ compatible = "mdio-mux-mmioreg";
+ reg = <0x1803f1c0 0x4>;
+ mux-mask = <0x2000>;
+ mdio-parent-bus = <&mdio_ext>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port6: phy@0 {
+ reg = <0>;
+ };
+
+ phy_port7: phy@1 {
+ reg = <1>;
+ };
+
+ phy_port8: phy@2 {
+ reg = <2>;
+ };
+
+ phy_port9: phy@3 {
+ reg = <3>;
+ };
+
+ phy_port10: phy@4 {
+ reg = <4>;
+ };
+
+ switch@10 {
+ compatible = "qca,qca8337";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10>;
+ dsa,member = <1 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&sgmii1>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan8";
+ phy-handle = <&phy_port6>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan9";
+ phy-handle = <&phy_port7>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan10";
+ phy-handle = <&phy_port8>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan11";
+ phy-handle = <&phy_port9>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan12";
+ phy-handle = <&phy_port10>;
+ };
+ };
+ };
+ };
+
+ mdio-mii@2000 {
+ reg = <0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port1: phy@0 {
+ reg = <0>;
+ };
+
+ phy_port2: phy@1 {
+ reg = <1>;
+ };
+
+ phy_port3: phy@2 {
+ reg = <2>;
+ };
+
+ phy_port4: phy@3 {
+ reg = <3>;
+ };
+
+ phy_port5: phy@4 {
+ reg = <4>;
+ };
+
+ switch@10 {
+ compatible = "qca,qca8337";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10>;
+ dsa,member = <2 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&sgmii0>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan3";
+ phy-handle = <&phy_port1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan4";
+ phy-handle = <&phy_port2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan5";
+ phy-handle = <&phy_port3>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan6";
+ phy-handle = <&phy_port4>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan7";
+ phy-handle = <&phy_port5>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&srab {
+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
+ status = "okay";
+ dsa,member = <0 0>;
+
+ ports {
+ port@0 {
+ label = "wan1";
+ reg = <0>;
+ };
+
+ port@1 {
+ label = "wan2";
+ reg = <1>;
+ };
+
+ sgmii0: port@4 {
+ label = "sw0";
+ reg = <4>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ sgmii1: port@5 {
+ label = "sw1";
+ reg = <5>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@8 {
+ ethernet = <&amac2>;
+ label = "cpu";
+ reg = <8>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts
new file mode 100644
index 000000000000..aec86c3a4d05
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65.
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-alamo.dtsi"
+
+/ {
+ model = "Cisco Meraki MX65";
+ compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";
+};
diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
new file mode 100644
index 000000000000..0045a33055c1
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65W.
+ *
+ * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-mx65x.dtsi"
+
+/ {
+ model = "Cisco Meraki MX65W";
+ compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
--
2.26.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 5/5] ARM: dts: NSP: Add DT files for Meraki MX65 series
2021-06-10 23:27 ` [PATCH v2 5/5] ARM: dts: NSP: Add DT files for Meraki MX65 series Matthew Hagan
@ 2021-06-11 19:02 ` Matthew Hagan
2021-06-11 20:48 ` Vladimir Oltean
1 sibling, 0 replies; 16+ messages in thread
From: Matthew Hagan @ 2021-06-11 19:02 UTC (permalink / raw)
Cc: Florian Fainelli, Vladimir Oltean, Andrew Lunn, Rob Herring,
Arnd Bergmann, Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Geert Uytterhoeven, Sam Ravnborg,
Viresh Kumar, devicetree, linux-kernel, linux-arm-kernel
On 11/06/2021 00:27, Matthew Hagan wrote:
> diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
> new file mode 100644
> index 000000000000..0045a33055c1
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Device Tree Bindings for Cisco Meraki MX65W.
> + *
> + * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "bcm958625-meraki-mx65x.dtsi"
Should be including "bcm958625-meraki-alamo.dtsi". Will fix in next version, subject to any other feedback.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 5/5] ARM: dts: NSP: Add DT files for Meraki MX65 series
2021-06-10 23:27 ` [PATCH v2 5/5] ARM: dts: NSP: Add DT files for Meraki MX65 series Matthew Hagan
2021-06-11 19:02 ` Matthew Hagan
@ 2021-06-11 20:48 ` Vladimir Oltean
1 sibling, 0 replies; 16+ messages in thread
From: Vladimir Oltean @ 2021-06-11 20:48 UTC (permalink / raw)
To: Matthew Hagan
Cc: Florian Fainelli, Andrew Lunn, Rob Herring, Arnd Bergmann,
Olof Johansson, soc, Ray Jui, Scott Branden,
bcm-kernel-feedback-list, Geert Uytterhoeven, Sam Ravnborg,
Viresh Kumar, devicetree, linux-kernel, linux-arm-kernel
On Fri, Jun 11, 2021 at 12:27:17AM +0100, Matthew Hagan wrote:
> MX65 Hardware info:
> - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz
> - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)
> - Storage: 1 GB (Micron MT29F8G08ABACA)
> - Networking: BCM58625 switch (2x 1GbE ports, used for WAN ports 1 & 2)
> 2x Qualcomm QCA8337 switches (10x 1GbE ports, used for LAN ports 3-12)
> - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12
> - USB: 1x USB2.0
> - Serial: Internal header
>
> As with the MX64, the MX65 has 2x Broadcom BCM43520KMLG on the PCI bus.
>
> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
> ---
> arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 298 ++++++++++++++++++
> arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 15 +
> arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 23 ++
> 3 files changed, 336 insertions(+)
> create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
> create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts
> create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
>
> diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
> new file mode 100644
> index 000000000000..0ff78fb89b6d
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
> @@ -0,0 +1,298 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
> + *
> + * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
> + */
> +
> +#include "bcm958625-meraki-mx6x-common.dtsi"
> +
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + aliases {
> + mdio-mux-mmio = &mdiomux0;
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + orange_power {
> + label = "orange:power";
> + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + wan1_right {
> + label = "green:wan1-right";
> + gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
> + };
> +
> + wan1_left {
> + label = "green:wan1-left";
> + gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
> + };
> +
> + wan2_right {
> + label = "green:wan2-right";
> + gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
> + };
> +
> + wan2_left {
> + label = "green:wan2-left";
> + gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
> + };
> +
> + white_status {
> + label = "white:status";
> + gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + keys {
> + compatible = "gpio-keys-polled";
> + autorepeat;
> + poll-interval = <20>;
> +
> + reset {
> + label = "reset";
> + linux,code = <KEY_RESTART>;
> + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + mdio: mdio@18032000 {
> + compatible = "brcm,iproc-mdio";
> + reg = <0x18032000 0x8>;
> + #size-cells = <0>;
> + #address-cells = <1>;
> + };
Odd that mdio@18032000 is under the / node and not under /soc? I don't
think you can combine nodes with a unit address with nodes without in
the same level of the hierarchy.
Also, it is odd that you define something SoC-specific like this in a
board file. Isn't this actually stray and not used?
> +
> + mdiomux0: mdio-mux {
> + compatible = "mdio-mux-mmioreg";
> + reg = <0x18032000 0x4>;
> + mux-mask = <0x200>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mdio-parent-bus = <&mdio>;
> +
> + mdio_ext: mdio@200 {
> + reg = <0x200>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + mdio-mii-mux {
> + compatible = "mdio-mux-mmioreg";
> + reg = <0x1803f1c0 0x4>;
> + mux-mask = <0x2000>;
> + mdio-parent-bus = <&mdio_ext>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mdio@0 {
> + reg = <0x0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phy_port6: phy@0 {
> + reg = <0>;
> + };
> +
> + phy_port7: phy@1 {
> + reg = <1>;
> + };
> +
> + phy_port8: phy@2 {
> + reg = <2>;
> + };
> +
> + phy_port9: phy@3 {
> + reg = <3>;
> + };
> +
> + phy_port10: phy@4 {
> + reg = <4>;
> + };
> +
> + switch@10 {
> + compatible = "qca,qca8337";
> + #address-cells = <1>;
> + #size-cells = <0>;
The "ports" node is adimensional, so address-cells and size-cells are
not needed.
> + reg = <0x10>;
> + dsa,member = <1 0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + label = "cpu";
'label' property for the CPU port is not needed/used. We know it is a
CPU port because it has the 'ethernet' property.
> + ethernet = <&sgmii1>;
> + phy-mode = "sgmii";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "lan8";
> + phy-handle = <&phy_port6>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "lan9";
> + phy-handle = <&phy_port7>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "lan10";
> + phy-handle = <&phy_port8>;
> + };
> +
> + port@4 {
> + reg = <4>;
> + label = "lan11";
> + phy-handle = <&phy_port9>;
> + };
> +
> + port@5 {
> + reg = <5>;
> + label = "lan12";
> + phy-handle = <&phy_port10>;
> + };
> + };
> + };
> + };
> +
> + mdio-mii@2000 {
> + reg = <0x2000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phy_port1: phy@0 {
> + reg = <0>;
> + };
> +
> + phy_port2: phy@1 {
> + reg = <1>;
> + };
> +
> + phy_port3: phy@2 {
> + reg = <2>;
> + };
> +
> + phy_port4: phy@3 {
> + reg = <3>;
> + };
> +
> + phy_port5: phy@4 {
> + reg = <4>;
> + };
> +
> + switch@10 {
> + compatible = "qca,qca8337";
> + #address-cells = <1>;
> + #size-cells = <0>;
Similar comment.
> + reg = <0x10>;
> + dsa,member = <2 0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + label = "cpu";
> + ethernet = <&sgmii0>;
> + phy-mode = "sgmii";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "lan3";
> + phy-handle = <&phy_port1>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "lan4";
> + phy-handle = <&phy_port2>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "lan5";
> + phy-handle = <&phy_port3>;
> + };
> +
> + port@4 {
> + reg = <4>;
> + label = "lan6";
> + phy-handle = <&phy_port4>;
> + };
> +
> + port@5 {
> + reg = <5>;
> + label = "lan7";
> + phy-handle = <&phy_port5>;
> + };
> + };
> + };
> + };
> + };
> +};
> +
> +&srab {
> + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
> + status = "okay";
> + dsa,member = <0 0>;
> +
> + ports {
> + port@0 {
> + label = "wan1";
> + reg = <0>;
> + };
> +
> + port@1 {
> + label = "wan2";
> + reg = <1>;
> + };
> +
> + sgmii0: port@4 {
> + label = "sw0";
> + reg = <4>;
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + sgmii1: port@5 {
> + label = "sw1";
> + reg = <5>;
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@8 {
> + ethernet = <&amac2>;
> + label = "cpu";
> + reg = <8>;
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts
> new file mode 100644
> index 000000000000..aec86c3a4d05
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Device Tree Bindings for Cisco Meraki MX65.
> + *
> + * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "bcm958625-meraki-alamo.dtsi"
> +
> +/ {
> + model = "Cisco Meraki MX65";
> + compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";
> +};
> diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
> new file mode 100644
> index 000000000000..0045a33055c1
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Device Tree Bindings for Cisco Meraki MX65W.
> + *
> + * Copyright (C) 2021 Matthew Hagan <mnhagan88@gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "bcm958625-meraki-mx65x.dtsi"
> +
> +/ {
> + model = "Cisco Meraki MX65W";
> + compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
> +};
> +
> +&pcie0 {
> + status = "okay";
> +};
> +
> +&pcie1 {
> + status = "okay";
> +};
> --
> 2.26.3
>
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