From: Andi Kleen <andi@firstfloor.org>
To: linux-kernel@vger.kernel.org
Cc: acme@redhat.com, peterz@infradead.org, jolsa@redhat.com,
eranian@google.com, mingo@kernel.org, namhyung@kernel.org,
Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 01/32] perf, x86: Add PEBSv2 record support
Date: Fri, 9 Nov 2012 17:27:17 -0800 [thread overview]
Message-ID: <1352510868-7911-2-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1352510868-7911-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
Add support for the v2 PEBS format. It has a superset of the v1 PEBS
fields, but has a longer record so we need to adjust the code paths.
The main advantage is the new "EventingRip" support which directly
gives the instruction, not off-by-one instruction. So with precise == 2
we use that directly and don't try to use LBRs and walking basic blocks.
This lowers the overhead significantly.
Some other features are added in later patches.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event.c | 2 +-
arch/x86/kernel/cpu/perf_event_intel_ds.c | 101 ++++++++++++++++++++++-------
2 files changed, 79 insertions(+), 24 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 4428fd1..ec3c549 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -403,7 +403,7 @@ int x86_pmu_hw_config(struct perf_event *event)
* check that PEBS LBR correction does not conflict with
* whatever the user is asking with attr->branch_sample_type
*/
- if (event->attr.precise_ip > 1) {
+ if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
u64 *br_type = &event->attr.branch_sample_type;
if (has_branch_stack(event)) {
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 826054a..9d0dae0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -41,6 +41,12 @@ struct pebs_record_nhm {
u64 status, dla, dse, lat;
};
+struct pebs_record_v2 {
+ struct pebs_record_nhm nhm;
+ u64 eventingrip;
+ u64 tsx_tuning;
+};
+
void init_debug_store_on_cpu(int cpu)
{
struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
@@ -559,8 +565,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
{
/*
* We cast to pebs_record_core since that is a subset of
- * both formats and we don't use the other fields in this
- * routine.
+ * both formats.
*/
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
struct pebs_record_core *pebs = __pebs;
@@ -588,7 +593,10 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
regs.bp = pebs->bp;
regs.sp = pebs->sp;
- if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
+ if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
+ regs.ip = ((struct pebs_record_v2 *)pebs)->eventingrip;
+ regs.flags |= PERF_EFLAGS_EXACT;
+ } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
regs.flags |= PERF_EFLAGS_EXACT;
else
regs.flags &= ~PERF_EFLAGS_EXACT;
@@ -641,35 +649,21 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
__intel_pmu_pebs_event(event, iregs, at);
}
-static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
+static void intel_pmu_drain_pebs_common(struct pt_regs *iregs, void *at,
+ void *top)
{
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
struct debug_store *ds = cpuc->ds;
- struct pebs_record_nhm *at, *top;
struct perf_event *event = NULL;
u64 status = 0;
- int bit, n;
-
- if (!x86_pmu.pebs_active)
- return;
-
- at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
- top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
+ int bit;
ds->pebs_index = ds->pebs_buffer_base;
- n = top - at;
- if (n <= 0)
- return;
+ for ( ; at < top; at += x86_pmu.pebs_record_size) {
+ struct pebs_record_nhm *p = at;
- /*
- * Should not happen, we program the threshold at 1 and do not
- * set a reset value.
- */
- WARN_ONCE(n > x86_pmu.max_pebs_events, "Unexpected number of pebs records %d\n", n);
-
- for ( ; at < top; at++) {
- for_each_set_bit(bit, (unsigned long *)&at->status, x86_pmu.max_pebs_events) {
+ for_each_set_bit(bit, (unsigned long *)&p->status, x86_pmu.max_pebs_events) {
event = cpuc->events[bit];
if (!test_bit(bit, cpuc->active_mask))
continue;
@@ -692,6 +686,61 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
}
}
+static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct debug_store *ds = cpuc->ds;
+ struct pebs_record_nhm *at, *top;
+ int n;
+
+ if (!x86_pmu.pebs_active)
+ return;
+
+ at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
+ top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
+
+ ds->pebs_index = ds->pebs_buffer_base;
+
+ n = top - at;
+ if (n <= 0)
+ return;
+
+ /*
+ * Should not happen, we program the threshold at 1 and do not
+ * set a reset value.
+ */
+ WARN_ONCE(n > x86_pmu.max_pebs_events,
+ "Unexpected number of pebs records %d\n", n);
+
+ return intel_pmu_drain_pebs_common(iregs, at, top);
+}
+
+static void intel_pmu_drain_pebs_v2(struct pt_regs *iregs)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct debug_store *ds = cpuc->ds;
+ struct pebs_record_v2 *at, *top;
+ int n;
+
+ if (!x86_pmu.pebs_active)
+ return;
+
+ at = (struct pebs_record_v2 *)(unsigned long)ds->pebs_buffer_base;
+ top = (struct pebs_record_v2 *)(unsigned long)ds->pebs_index;
+
+ n = top - at;
+ if (n <= 0)
+ return;
+ /*
+ * Should not happen, we program the threshold at 1 and do not
+ * set a reset value.
+ */
+ WARN_ONCE(n > x86_pmu.max_pebs_events,
+ "Unexpected number of pebs records %d\n", n);
+
+ return intel_pmu_drain_pebs_common(iregs, at, top);
+}
+
/*
* BTS, PEBS probe and setup
*/
@@ -723,6 +772,12 @@ void intel_ds_init(void)
x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
break;
+ case 2:
+ printk(KERN_CONT "PEBS fmt2%c, ", pebs_type);
+ x86_pmu.pebs_record_size = sizeof(struct pebs_record_v2);
+ x86_pmu.drain_pebs = intel_pmu_drain_pebs_v2;
+ break;
+
default:
printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
x86_pmu.pebs = 0;
--
1.7.7.6
next prev parent reply other threads:[~2012-11-10 1:34 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-10 1:27 perf PMU support for Haswell v6 Andi Kleen
2012-11-10 1:27 ` Andi Kleen [this message]
2012-11-10 1:27 ` [PATCH 02/32] perf, x86: Basic Haswell PMU support v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 03/32] perf, x86: Basic Haswell PEBS support v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 04/32] perf, x86: Support the TSX intx/intx_cp qualifiers v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 05/32] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v4 Andi Kleen
2012-11-12 12:43 ` Gleb Natapov
2012-11-10 1:27 ` [PATCH 06/32] perf, x86: Support PERF_SAMPLE_ADDR on Haswell Andi Kleen
2012-11-10 1:27 ` [PATCH 07/32] perf, x86: Support Haswell v4 LBR format Andi Kleen
2012-11-10 1:27 ` [PATCH 08/32] perf, x86: Disable LBR recording for unknown LBR_FMT Andi Kleen
2012-11-10 1:27 ` [PATCH 09/32] perf, x86: Support LBR filtering by INTX/NOTX/ABORT v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 10/32] perf, tools: Add abort_tx,no_tx,in_tx branch filter options to perf record -j v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 11/32] perf, tools: Support sorting by intx, abort branch flags Andi Kleen
2012-11-10 1:27 ` [PATCH 12/32] perf, x86: Support full width counting Andi Kleen
2012-11-10 1:27 ` [PATCH 13/32] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 14/32] perf, core: Add a concept of a weightened sample Andi Kleen
2012-11-10 1:27 ` [PATCH 15/32] perf, x86: Support weight samples for PEBS Andi Kleen
2012-11-10 1:27 ` [PATCH 16/32] perf, tools: Add support for weight v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 17/32] perf, tools: Handle XBEGIN like a jump Andi Kleen
2012-11-10 1:27 ` [PATCH 18/32] perf, x86: Support for printing PMU state on spurious PMIs v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 19/32] perf, core: Add generic transaction flags v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 20/32] perf, x86: Add Haswell specific transaction flag reporting Andi Kleen
2012-11-10 1:27 ` [PATCH 21/32] perf, tools: Add support for record transaction flags v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 22/32] perf, tools: Point --sort documentation to --help Andi Kleen
2012-11-10 1:27 ` [PATCH 23/32] perf, tools: Add browser support for transaction flags v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 24/32] perf, tools: Add arbitary aliases and support names with - Andi Kleen
2012-11-10 1:27 ` [PATCH 25/32] tools, perf: Add a precise event qualifier Andi Kleen
2012-11-28 15:40 ` Jiri Olsa
2012-11-28 20:37 ` Andi Kleen
2012-11-10 1:27 ` [PATCH 26/32] perf, x86: improve sysfs event mapping with event string Andi Kleen
2012-11-10 1:27 ` [PATCH 27/32] perf, x86: Support CPU specific sysfs events Andi Kleen
2012-11-10 1:27 ` [PATCH 28/32] perf, x86: Add Haswell TSX event aliases v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 29/32] perf, tools: Add perf stat --transaction v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 30/32] perf, x86: Add a Haswell precise instructions event v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 31/32] perf, tools: Default to cpu// for events v3 Andi Kleen
2012-11-28 15:53 ` Jiri Olsa
2012-11-28 19:04 ` Andi Kleen
2012-11-28 19:42 ` Arnaldo Carvalho de Melo
2012-11-10 1:27 ` [PATCH 32/32] perf, tools: List kernel supplied event aliases in perf list v2 Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2012-10-31 0:33 perf PMU support for Haswell v5 Andi Kleen
2012-10-31 0:33 ` [PATCH 01/32] perf, x86: Add PEBSv2 record support Andi Kleen
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