From: Gleb Natapov <gleb@redhat.com>
To: Andi Kleen <andi@firstfloor.org>
Cc: linux-kernel@vger.kernel.org, acme@redhat.com,
peterz@infradead.org, jolsa@redhat.com, eranian@google.com,
mingo@kernel.org, namhyung@kernel.org,
Andi Kleen <ak@linux.intel.com>,
avi@redhat.com
Subject: Re: [PATCH 05/32] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v4
Date: Mon, 12 Nov 2012 14:43:52 +0200 [thread overview]
Message-ID: <20121112124352.GT25650@redhat.com> (raw)
In-Reply-To: <1352510868-7911-6-git-send-email-andi@firstfloor.org>
On Fri, Nov 09, 2012 at 05:27:21PM -0800, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> This is not arch perfmon, but older CPUs will just ignore it. This makes
> it possible to do at least some TSX measurements from a KVM guest
>
> Cc: avi@redhat.com
> Cc: gleb@redhat.com
> v2: Various fixes to address review feedback
> v3: Ignore the bits when no CPUID. No #GP. Force raw events with TSX bits.
> v4: Use reserved bits for #GP
> Cc: gleb@redhat.com
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> ---
> arch/x86/include/asm/kvm_host.h | 1 +
> arch/x86/kvm/pmu.c | 32 ++++++++++++++++++++++++--------
> 2 files changed, 25 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index b2e11f4..63d4be4 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -318,6 +318,7 @@ struct kvm_pmu {
> u64 global_ovf_ctrl;
> u64 counter_bitmask[2];
> u64 global_ctrl_mask;
> + u64 reserved_bits;
> u8 version;
> struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
> struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
> index cfc258a..89405d0 100644
> --- a/arch/x86/kvm/pmu.c
> +++ b/arch/x86/kvm/pmu.c
> @@ -160,7 +160,7 @@ static void stop_counter(struct kvm_pmc *pmc)
>
> static void reprogram_counter(struct kvm_pmc *pmc, u32 type,
> unsigned config, bool exclude_user, bool exclude_kernel,
> - bool intr)
> + bool intr, bool intx, bool intx_cp)
> {
> struct perf_event *event;
> struct perf_event_attr attr = {
> @@ -173,6 +173,10 @@ static void reprogram_counter(struct kvm_pmc *pmc, u32 type,
> .exclude_kernel = exclude_kernel,
> .config = config,
> };
> + if (intx)
> + attr.config |= HSW_INTX;
> + if (intx_cp)
> + attr.config |= HSW_INTX_CHECKPOINTED;
>
> attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc);
>
> @@ -206,7 +210,8 @@ static unsigned find_arch_event(struct kvm_pmu *pmu, u8 event_select,
> return arch_events[i].event_type;
> }
>
> -static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
> +static void reprogram_gp_counter(struct kvm_pmu *pmu, struct kvm_pmc *pmc,
> + u64 eventsel)
> {
pmu parameter is no longer used in this patch version. Otherwise looks
good.
> unsigned config, type = PERF_TYPE_RAW;
> u8 event_select, unit_mask;
> @@ -226,7 +231,9 @@ static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
>
> if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
> ARCH_PERFMON_EVENTSEL_INV |
> - ARCH_PERFMON_EVENTSEL_CMASK))) {
> + ARCH_PERFMON_EVENTSEL_CMASK |
> + HSW_INTX |
> + HSW_INTX_CHECKPOINTED))) {
> config = find_arch_event(&pmc->vcpu->arch.pmu, event_select,
> unit_mask);
> if (config != PERF_COUNT_HW_MAX)
> @@ -239,7 +246,9 @@ static void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
> reprogram_counter(pmc, type, config,
> !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
> !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
> - eventsel & ARCH_PERFMON_EVENTSEL_INT);
> + eventsel & ARCH_PERFMON_EVENTSEL_INT,
> + (eventsel & HSW_INTX),
> + (eventsel & HSW_INTX_CHECKPOINTED));
> }
>
> static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 en_pmi, int idx)
> @@ -256,7 +265,7 @@ static void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 en_pmi, int idx)
> arch_events[fixed_pmc_events[idx]].event_type,
> !(en & 0x2), /* exclude user */
> !(en & 0x1), /* exclude kernel */
> - pmi);
> + pmi, false, false);
> }
>
> static inline u8 fixed_en_pmi(u64 ctrl, int idx)
> @@ -289,7 +298,7 @@ static void reprogram_idx(struct kvm_pmu *pmu, int idx)
> return;
>
> if (pmc_is_gp(pmc))
> - reprogram_gp_counter(pmc, pmc->eventsel);
> + reprogram_gp_counter(pmu, pmc, pmc->eventsel);
> else {
> int fidx = idx - INTEL_PMC_IDX_FIXED;
> reprogram_fixed_counter(pmc,
> @@ -400,8 +409,8 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
> } else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
> if (data == pmc->eventsel)
> return 0;
> - if (!(data & 0xffffffff00200000ull)) {
> - reprogram_gp_counter(pmc, data);
> + if (!(data & pmu->reserved_bits)) {
> + reprogram_gp_counter(pmu, pmc, data);
> return 0;
> }
> }
> @@ -442,6 +451,7 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
> pmu->counter_bitmask[KVM_PMC_GP] = 0;
> pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
> pmu->version = 0;
> + pmu->reserved_bits = 0xffffffff00200000ull;
>
> entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
> if (!entry)
> @@ -470,6 +480,12 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
> pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
> (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
> pmu->global_ctrl_mask = ~pmu->global_ctrl;
> +
> + entry = kvm_find_cpuid_entry(vcpu, 7, 0);
> + if (entry &&
> + (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
> + (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM)))
> + pmu->reserved_bits ^= HSW_INTX|HSW_INTX_CHECKPOINTED;
> }
>
> void kvm_pmu_init(struct kvm_vcpu *vcpu)
> --
> 1.7.7.6
--
Gleb.
next prev parent reply other threads:[~2012-11-12 12:44 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-10 1:27 perf PMU support for Haswell v6 Andi Kleen
2012-11-10 1:27 ` [PATCH 01/32] perf, x86: Add PEBSv2 record support Andi Kleen
2012-11-10 1:27 ` [PATCH 02/32] perf, x86: Basic Haswell PMU support v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 03/32] perf, x86: Basic Haswell PEBS support v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 04/32] perf, x86: Support the TSX intx/intx_cp qualifiers v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 05/32] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v4 Andi Kleen
2012-11-12 12:43 ` Gleb Natapov [this message]
2012-11-10 1:27 ` [PATCH 06/32] perf, x86: Support PERF_SAMPLE_ADDR on Haswell Andi Kleen
2012-11-10 1:27 ` [PATCH 07/32] perf, x86: Support Haswell v4 LBR format Andi Kleen
2012-11-10 1:27 ` [PATCH 08/32] perf, x86: Disable LBR recording for unknown LBR_FMT Andi Kleen
2012-11-10 1:27 ` [PATCH 09/32] perf, x86: Support LBR filtering by INTX/NOTX/ABORT v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 10/32] perf, tools: Add abort_tx,no_tx,in_tx branch filter options to perf record -j v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 11/32] perf, tools: Support sorting by intx, abort branch flags Andi Kleen
2012-11-10 1:27 ` [PATCH 12/32] perf, x86: Support full width counting Andi Kleen
2012-11-10 1:27 ` [PATCH 13/32] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 14/32] perf, core: Add a concept of a weightened sample Andi Kleen
2012-11-10 1:27 ` [PATCH 15/32] perf, x86: Support weight samples for PEBS Andi Kleen
2012-11-10 1:27 ` [PATCH 16/32] perf, tools: Add support for weight v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 17/32] perf, tools: Handle XBEGIN like a jump Andi Kleen
2012-11-10 1:27 ` [PATCH 18/32] perf, x86: Support for printing PMU state on spurious PMIs v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 19/32] perf, core: Add generic transaction flags v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 20/32] perf, x86: Add Haswell specific transaction flag reporting Andi Kleen
2012-11-10 1:27 ` [PATCH 21/32] perf, tools: Add support for record transaction flags v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 22/32] perf, tools: Point --sort documentation to --help Andi Kleen
2012-11-10 1:27 ` [PATCH 23/32] perf, tools: Add browser support for transaction flags v3 Andi Kleen
2012-11-10 1:27 ` [PATCH 24/32] perf, tools: Add arbitary aliases and support names with - Andi Kleen
2012-11-10 1:27 ` [PATCH 25/32] tools, perf: Add a precise event qualifier Andi Kleen
2012-11-28 15:40 ` Jiri Olsa
2012-11-28 20:37 ` Andi Kleen
2012-11-10 1:27 ` [PATCH 26/32] perf, x86: improve sysfs event mapping with event string Andi Kleen
2012-11-10 1:27 ` [PATCH 27/32] perf, x86: Support CPU specific sysfs events Andi Kleen
2012-11-10 1:27 ` [PATCH 28/32] perf, x86: Add Haswell TSX event aliases v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 29/32] perf, tools: Add perf stat --transaction v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 30/32] perf, x86: Add a Haswell precise instructions event v2 Andi Kleen
2012-11-10 1:27 ` [PATCH 31/32] perf, tools: Default to cpu// for events v3 Andi Kleen
2012-11-28 15:53 ` Jiri Olsa
2012-11-28 19:04 ` Andi Kleen
2012-11-28 19:42 ` Arnaldo Carvalho de Melo
2012-11-10 1:27 ` [PATCH 32/32] perf, tools: List kernel supplied event aliases in perf list v2 Andi Kleen
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