[PATCH v2 00/16] usb: dwc3: add support for AMD NL SoC

[PATCH v2 00/16] usb: dwc3: add support for AMD NL SoC

[Huang Rui]

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Hi,

The series of patches add AMD NL SoC support for DesignWare USB3 OTG IP with
PCI bus glue layer. This controller supported hibernation, LPM erratum and used
the 2.80a IP version and amd own phy. Current implementation support both
simulation and SoC platform. And already tested with gadget zero and msc tool.
It works well on file storage gadget.


These patches are generated on balbi/testing/next

Changes from v1 -> v2
- remove dual role function temporarily
- add pci quirk to avoid to bind with xhci driver
- distinguish between simulation board and soc
- break down all the special quirks


Patch 1:
- add PCI device id into pci bus glue

Patch 2:
- add PCI quirk to avoid to bind with xhci

Patch 3:
- enable hibernation

Patch 4:
- distinguish between simulation board and soc

Patch 5:
- add quirks flag to be compatible for kinds of soc

Patch 6 - 16:
- as felipe's suggestion, break down all the special quirks of amd nl


Patch set already passed all the MSC testing, detailed result is below:

root@hr-ub:/home/ray/felipe/usb-tools# ./msc.sh -o /dev/sdb1
Starting test suite: 2014年 10月 09日 星期四 18:02:41 CST
test 0a: simple 4k read/write
test  0: sent       3.91 MB read       0.03 MB/s write       0.03 MB/s ... success
test 0b: simple 8k read/write
test  0: sent       7.81 MB read       6.15 MB/s write       5.96 MB/s ... success
test 0c: simple 16k read/write
test  0: sent      15.62 MB read      14.30 MB/s write      12.97 MB/s ... success
test 0d: simple 32k read/write
test  0: sent      31.25 MB read      18.26 MB/s write      17.10 MB/s ... success
test 0e: simple 64k read/write
test  0: sent      62.50 MB read      22.00 MB/s write      16.33 MB/s ... success
test 1: simple 1-sector read/write
test  1: sent     500.00 kB read       1.05 MB/s write       0.93 MB/s ... success
test 2: simple 8-sectors read/write
test  2: sent       3.91 MB read       6.52 MB/s write       6.10 MB/s ... success
test 3: simple 32-sectors read/write
test  3: sent      15.62 MB read      14.33 MB/s write      13.14 MB/s ... success
test 4: simple 64-sectors read/write
test  4: sent      31.25 MB read      17.79 MB/s write      16.38 MB/s ... success
test 5a: scatter/gather for 2-sectors buflen 4k
test  5: sent    1000.00 kB read       1.85 MB/s write       1.56 MB/s ... success
test 5b: scatter/gather for 2-sectors buflen 8k
test  5: sent    1000.00 kB read       1.91 MB/s write       1.63 MB/s ... success
test 5c: scatter/gather for 2-sectors buflen 16k
test  5: sent    1000.00 kB read       1.94 MB/s write       1.62 MB/s ... success
test 5d: scatter/gather for 2-sectors buflen 32k
test  5: sent    1000.00 kB read       1.93 MB/s write       1.64 MB/s ... success
test 5e: scatter/gather for 2-sectors buflen 64k
test  5: sent    1000.00 kB read       1.96 MB/s write       1.68 MB/s ... success
test 6a: scatter/gather for 8-sectors buflen 4k
test  6: sent       3.91 MB read       6.53 MB/s write       6.05 MB/s ... success
test 6b: scatter/gather for 8-sectors buflen 8k
test  6: sent       3.91 MB read       6.56 MB/s write       5.98 MB/s ... success
test 6c: scatter/gather for 8-sectors buflen 16k
test  6: sent       3.91 MB read       6.55 MB/s write       6.15 MB/s ... success
test 6d: scatter/gather for 8-sectors buflen 32k
test  6: sent       3.91 MB read       6.51 MB/s write       6.06 MB/s ... success
test 6e: scatter/gather for 8-sectors buflen 64k
test  6: sent       3.91 MB read       6.50 MB/s write       6.06 MB/s ... success
test 7a: scatter/gather for 32-sectors buflen 16k
test  7: sent      15.62 MB read      14.23 MB/s write      12.99 MB/s ... success
test 7b: scatter/gather for 32-sectors buflen 32k
test  7: sent      15.62 MB read      14.27 MB/s write      12.91 MB/s ... success
test 7c: scatter/gather for 32-sectors buflen 64k
test  7: sent      15.62 MB read      14.73 MB/s write      13.00 MB/s ... success
test 8a: scatter/gather for 64-sectors buflen 32k
test  8: sent      31.25 MB read      18.42 MB/s write      16.65 MB/s ... success
test 8b: scatter/gather for 64-sectors buflen 64k
test  8: sent      31.25 MB read      17.70 MB/s write      16.39 MB/s ... success
test 9: scatter/gather for 128-sectors buflen 64k
test  9: sent      62.50 MB read      21.14 MB/s write      16.07 MB/s ... success
test 10: read over the end of the block device
test 10: sent      62.01 MB read       0.00 MB/s write       0.00 MB/s ... success
test 11: lseek past the end of the block device
test 11: sent       0.00 B read       0.00 MB/s write       0.00 MB/s ... success
test 12: write over the end of the block device
test 12: sent       0.00 B read       0.00 MB/s write       0.00 MB/s ... success
test 13: write 1 sg, read 8 random size sgs
test 13: sent      62.50 MB read      21.61 MB/s write      16.21 MB/s ... success
test 14: write 8 random size sgs, read 1 sg
test 14: sent      62.50 MB read      22.52 MB/s write      18.61 MB/s ... success
test 15: write and read 8 random size sgs
test 15: sent      62.50 MB read      22.31 MB/s write      19.28 MB/s ... success
test 16a: read with heap allocated buffer
test 16: sent      62.50 MB read      21.69 MB/s write       0.00 MB/s ... success
test 16b: read with stack allocated buffer
test 16: sent      62.50 MB read      21.42 MB/s write       0.00 MB/s ... success
test 17a: write with heap allocated buffer
test 17: sent       0.00 B read       0.00 MB/s write      19.94 MB/s ... success
test 17b: write with stack allocated buffer
test 17: sent       0.00 B read       0.00 MB/s write      20.09 MB/s ... success
test 18a: write 0x00 and read it back
test 18: sent      62.50 MB read      21.94 MB/s write      16.96 MB/s ... success
test 18b: write 0xff and read it back
test 18: sent      62.50 MB read      19.89 MB/s write      15.51 MB/s ... success
test 18c: write 0x55 and read it back
test 18: sent      62.50 MB read      22.00 MB/s write      16.62 MB/s ... success
test 18d: write 0xaa and read it back
test 18: sent      62.50 MB read      21.81 MB/s write      16.53 MB/s ... success
test 18e: write 0x11 and read it back
test 18: sent      62.50 MB read      22.33 MB/s write      17.00 MB/s ... success
test 18f: write 0x22 and read it back
test 18: sent      62.50 MB read      21.66 MB/s write      16.44 MB/s ... success
test 18g: write 0x44 and read it back
test 18: sent      62.50 MB read      22.23 MB/s write      17.08 MB/s ... success
test 18h: write 0x88 and read it back
test 18: sent      62.50 MB read      21.54 MB/s write      16.17 MB/s ... success
test 18i: write 0x33 and read it back
test 18: sent      62.50 MB read      21.20 MB/s write      16.58 MB/s ... success
test 18j: write 0x66 and read it back
test 18: sent      62.50 MB read      21.82 MB/s write      16.13 MB/s ... success
test 18k: write 0x99 and read it back
test 18: sent      62.50 MB read      21.92 MB/s write      16.36 MB/s ... success
test 18l: write 0xcc and read it back
test 18: sent      62.50 MB read      22.37 MB/s write      16.74 MB/s ... success
test 18m: write 0x77 and read it back
test 18: sent      62.50 MB read      22.34 MB/s write      16.24 MB/s ... success
test 18n: write 0xbb and read it back
test 18: sent      62.50 MB read      21.82 MB/s write      16.23 MB/s ... success
test 18o: write 0xdd and read it back
test 18: sent      62.50 MB read      21.38 MB/s write      16.48 MB/s ... success
test 18p: write 0xee and read it back
test 18: sent      62.50 MB read      22.33 MB/s write      16.15 MB/s ... success
Test suite ended: 2014年 10月 09日 星期四 18:13:36 CST


Thanks,
Rui

Huang Rui (16):
  usb: dwc3: add AMD NL support
  pci: quirks: add quirk to avoid AMD NL to bind with xhci
  usb: dwc3: enable hibernation if to be supported
  usb: dwc3: add a flag to check if it is fpga board
  usb: dwc3: add quirks support to be compatible for kinds of SoCs
  usb: dwc3: add disscramble quirk
  usb: dwc3: add lpm erratum support
  usb: dwc3: add u2exit lfps quirk
  usb: dwc3: add P3 in U2 SS inactive quirk
  usb: dwc3: add request p1p2p3 quirk
  usb: dwc3: add delay p1p2p3 quirk
  usb: dwc3: add delay phy power change quirk
  usb: dwc3: add lfps filter quirk
  usb: dwc3: enable rx_detect to polling lfps quirk
  usb: dwc3: add tx demphasis quirk
  usb: dwc3: enable usb suspend phy

 drivers/pci/quirks.c             | 20 ++++++++++++
 drivers/usb/dwc3/core.c          | 66 +++++++++++++++++++++++++++++++++++++++-
 drivers/usb/dwc3/core.h          | 42 +++++++++++++++++++------
 drivers/usb/dwc3/dwc3-pci.c      | 26 ++++++++++++++++
 drivers/usb/dwc3/gadget.c        |  7 +++++
 drivers/usb/dwc3/platform_data.h | 16 ++++++++++
 6 files changed, 167 insertions(+), 10 deletions(-)

-- 
1.9.1

[PATCH v2 01/16] usb: dwc3: add AMD NL support

[Huang Rui]

Add PCI device ID of AMD NL SoC.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/dwc3-pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index a36cf66..3806547 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -31,6 +31,7 @@
 #define PCI_DEVICE_ID_INTEL_BYT		0x0f37
 #define PCI_DEVICE_ID_INTEL_MRFLD	0x119e
 #define PCI_DEVICE_ID_INTEL_BSW		0x22B7
+#define PCI_DEVICE_ID_AMD_NL		0x7912
 
 struct dwc3_pci {
 	struct device		*dev;
@@ -185,6 +186,7 @@ static const struct pci_device_id dwc3_pci_id_table[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL), },
 	{  }	/* Terminating Entry */
 };
 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
-- 
1.9.1

[PATCH v2 02/16] pci: quirks: add quirk to avoid AMD NL to bind with xhci

[Huang Rui]

The dwc3 controller is the PCI-E device in AMD NL platform, but the class code
of PCI header is 0x0c0330, the same with xHC. That's because it needs to meet
the windows enviroment. The dwc3 controller acted as only host mode to bind with
windows xhci driver.
But on linux, sometimes, it would auto-bind with xhci driver as well (class code
0x0c0330) despite it uses Pid/Vid on dwc3 driver.

Heikki suggested to use the quirk to fix this issue, and the detailed discussion
is at below thread:
http://marc.info/?l=linux-usb&m=141197934712824&w=2

Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/pci/quirks.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 90acb32..3c911b7 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -378,6 +378,26 @@ static void quirk_ati_exploding_mce(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
 
+/* FIXME should define in <linux/pci_ids.h> */
+#define PCI_DEVICE_ID_AMD_NL	0x7912
+
+/*
+ * AMD NL SoC 7912 PCI device is dwc3 controller, but the class code of PCI
+ * header is 0x0c0330, the same with xHC. That's because it need to meet the
+ * windows enviroment. The dwc3 controller acted as only host mode to bind with
+ * windows xhci driver. But on linux, sometimes, we auto-bind with xhci driver
+ * as well (class code 0x0c0330) despite we use Pid/Vid on dwc3 driver. So this
+ * quirk used a dummy class code to avoid to bind with xhci driver at booting
+ * phase.
+ */
+static void quirk_amd_nl_class(struct pci_dev *pdev)
+{
+	/* Use a dummy class value instead of PCI header provided */
+	pdev->class = 0x0c03fe;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL,
+		quirk_amd_nl_class);
+
 /*
  * Let's make the southbridge information explicit instead
  * of having to worry about people probing the ACPI areas,
-- 
1.9.1

[PATCH v2 03/16] usb: dwc3: enable hibernation if to be supported

[Huang Rui]

It enables hibernation if the function is set in coreConsultant.

Suggested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index fa396fc..bf77509 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -449,6 +449,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 		/* enable hibernation here */
 		dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
+		reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 		break;
 	default:
 		dev_dbg(dwc->dev, "No power optimization available\n");
-- 
1.9.1

[PATCH v2 04/16] usb: dwc3: add a flag to check if it is fpga board

[Huang Rui]

Some chip vendor is on pre-silicon phase, which needs to use the simulation
board. It should have the same product and vendor id with the true soc, but
might have some minor different configurations.

Below thread discussion proposes to find a method to distinguish between
simulation board and soc.

http://marc.info/?l=linux-usb&m=141194772206369&w=2

In Andvanced Configuration of coreConsultant, there is the parameter of
DWC_USB_EN_FPGA. This bit has the function we need. And it would response as 7
bit of GHWPARAMS6 register. So it's able to check this functional bit to confirm
if works on FPGA board.

Reported-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c | 6 ++++++
 drivers/usb/dwc3/core.h | 5 +++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index bf77509..ddac372 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -455,6 +455,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
 		dev_dbg(dwc->dev, "No power optimization available\n");
 	}
 
+	/* check if current dwc3 is on simulation board */
+	if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
+		dev_dbg(dwc->dev, "it is on FPGA board\n");
+		dwc->is_fpga = true;
+	}
+
 	/*
 	 * WORKAROUND: DWC3 revisions <1.90a have a bug
 	 * where the device can fail to connect at SuperSpeed
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a715ee1..f6ee623 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -210,6 +210,9 @@
 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)
 #define DWC3_MAX_HIBER_SCRATCHBUFS		15
 
+/* Global HWPARAMS6 Register */
+#define DWC3_GHWPARAMS6_EN_FPGA			(1 << 7)
+
 /* Device Configuration Register */
 #define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)
 #define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)
@@ -662,6 +665,7 @@ struct dwc3_scratchpad_array {
  * @ep0_expect_in: true when we expect a DATA IN transfer
  * @has_hibernation: true when dwc3 was configured with Hibernation
  * @is_selfpowered: true when we are selfpowered
+ * @is_fpga: true when we are using the FPGA board
  * @needs_fifo_resize: not all users might want fifo resizing, flag it
  * @pullups_connected: true when Run/Stop bit is set
  * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
@@ -765,6 +769,7 @@ struct dwc3 {
 	unsigned		ep0_expect_in:1;
 	unsigned		has_hibernation:1;
 	unsigned		is_selfpowered:1;
+	unsigned		is_fpga:1;
 	unsigned		needs_fifo_resize:1;
 	unsigned		pullups_connected:1;
 	unsigned		resize_fifos:1;
-- 
1.9.1

[PATCH v2 05/16] usb: dwc3: add quirks support to be compatible for kinds of SoCs

[Huang Rui]

This patch adds a quirks flag at dwc3 structure, and SoCs platform vendor is
able to define this flag in platform data at bus glue layer. Then do some
independent behaviors at dwc3 core level.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 2 ++
 drivers/usb/dwc3/core.h          | 3 +++
 drivers/usb/dwc3/dwc3-pci.c      | 9 +++++++++
 drivers/usb/dwc3/platform_data.h | 2 ++
 4 files changed, 16 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ddac372..50c0eae 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -710,6 +710,8 @@ static int dwc3_probe(struct platform_device *pdev)
 
 		dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 		dwc->dr_mode = pdata->dr_mode;
+
+		dwc->quirks = pdata->quirks;
 	}
 
 	/* default to superspeed if no maximum_speed passed */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index f6ee623..cfe0d57 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -636,6 +636,7 @@ struct dwc3_scratchpad_array {
  * @u1u2: only used on revisions <1.83a for workaround
  * @maximum_speed: maximum speed requested (mainly for testing purposes)
  * @revision: revision register contents
+ * @quirks: represents different SOCs hardware work-arounds and quirks
  * @dr_mode: requested mode of operation
  * @usb2_phy: pointer to USB2 PHY
  * @usb3_phy: pointer to USB3 PHY
@@ -740,6 +741,8 @@ struct dwc3 {
 #define DWC3_REVISION_270A	0x5533270a
 #define DWC3_REVISION_280A	0x5533280a
 
+	u32			quirks;
+
 	enum dwc3_ep0_next	ep0_next_event;
 	enum dwc3_ep0_state	ep0state;
 	enum dwc3_link_state	link_state;
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 3806547..18569a4 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -25,6 +25,8 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/usb_phy_generic.h>
 
+#include "platform_data.h"
+
 /* FIXME define these in <linux/pci_ids.h> */
 #define PCI_VENDOR_ID_SYNOPSYS		0x16c3
 #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3	0xabcd
@@ -103,6 +105,9 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 	struct dwc3_pci		*glue;
 	int			ret;
 	struct device		*dev = &pci->dev;
+	struct dwc3_platform_data dwc3_pdata;
+
+	memset(&dwc3_pdata, 0x00, sizeof(dwc3_pdata));
 
 	glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
 	if (!glue)
@@ -149,6 +154,10 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 
 	pci_set_drvdata(pci, glue);
 
+	ret = platform_device_add_data(dwc3, &dwc3_pdata, sizeof(dwc3_pdata));
+	if (ret)
+		goto err3;
+
 	dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
 
 	dwc3->dev.dma_mask = dev->dma_mask;
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 7db34f0..1d3d65f 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -24,4 +24,6 @@ struct dwc3_platform_data {
 	enum usb_device_speed maximum_speed;
 	enum usb_dr_mode dr_mode;
 	bool tx_fifo_resize;
+
+	u32     quirks;
 };
-- 
1.9.1

[PATCH v2 06/16] usb: dwc3: add disscramble quirk

[Huang Rui]

AMD NL fpga needs to enable disscramble quirk. And this quirk doesn't need on
the true soc.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 8 +++++++-
 drivers/usb/dwc3/dwc3-pci.c      | 5 +++++
 drivers/usb/dwc3/platform_data.h | 4 ++++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 50c0eae..819e501 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -422,7 +422,6 @@ static int dwc3_core_init(struct dwc3 *dwc)
 
 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
-	reg &= ~DWC3_GCTL_DISSCRAMBLE;
 
 	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
@@ -461,6 +460,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
 		dwc->is_fpga = true;
 	}
 
+	if ((dwc->quirks & DWC3_QUIRK_AMD_NL) && dwc->is_fpga)
+		dwc->quirks |= DWC3_QUIRK_DISSCRAMBLE;
+
+	if (dwc->quirks & DWC3_QUIRK_DISSCRAMBLE)
+		reg |= DWC3_GCTL_DISSCRAMBLE;
+	else
+		reg &= ~DWC3_GCTL_DISSCRAMBLE;
 	/*
 	 * WORKAROUND: DWC3 revisions <1.90a have a bug
 	 * where the device can fail to connect at SuperSpeed
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 18569a4..a89db6c 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -146,6 +146,11 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 	res[1].name	= "dwc_usb3";
 	res[1].flags	= IORESOURCE_IRQ;
 
+	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
+			PCI_DEVICE_ID_AMD_NL) {
+		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
+	}
+
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
 	if (ret) {
 		dev_err(dev, "couldn't add resources to dwc3 device\n");
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 1d3d65f..9c5f074 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -26,4 +26,8 @@ struct dwc3_platform_data {
 	bool tx_fifo_resize;
 
 	u32     quirks;
+
+#define DWC3_QUIRK_AMD_NL		(1 << 0)
+#define DWC3_QUIRK_DISSCRAMBLE		(1 << 1)
+
 };
-- 
1.9.1

[PATCH v2 07/16] usb: dwc3: add lpm erratum support

[Huang Rui]

When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced Configuration
of coreConsultant, it supports of xHCI BESL Errata Dated 10/19/2011 is enabled
in host mode. In device mode it adds the capability to send NYET response based
on the BESL value received in the LPM token.

This patch add an entry that soc platform is able to define the lpm capacity
with their own device tree or bus glue layer.

Suggested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          |  2 ++
 drivers/usb/dwc3/core.h          | 24 +++++++++++++++---------
 drivers/usb/dwc3/dwc3-pci.c      |  1 +
 drivers/usb/dwc3/gadget.c        |  7 +++++++
 drivers/usb/dwc3/platform_data.h |  1 +
 5 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 819e501..25db533 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -708,11 +708,13 @@ static int dwc3_probe(struct platform_device *pdev)
 
 	if (node) {
 		dwc->maximum_speed = of_usb_get_maximum_speed(node);
+		dwc->has_lpm_erratum = of_property_read_bool(node, "snps,has-lpm-erratum");
 
 		dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
 		dwc->dr_mode = of_usb_get_dr_mode(node);
 	} else if (pdata) {
 		dwc->maximum_speed = pdata->maximum_speed;
+		dwc->has_lpm_erratum = pdata->has_lpm_erratum;
 
 		dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 		dwc->dr_mode = pdata->dr_mode;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index cfe0d57..d58479e 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -246,16 +246,19 @@
 #define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))
 
 /* These apply for core versions 1.94a and later */
-#define DWC3_DCTL_KEEP_CONNECT	(1 << 19)
-#define DWC3_DCTL_L1_HIBER_EN	(1 << 18)
-#define DWC3_DCTL_CRS		(1 << 17)
-#define DWC3_DCTL_CSS		(1 << 16)
+#define DWC3_DCTL_LPM_ERRATA_MASK	DWC3_DCTL_LPM_ERRATA(0xf)
+#define DWC3_DCTL_LPM_ERRATA(n)		((n) << 20)
 
-#define DWC3_DCTL_INITU2ENA	(1 << 12)
-#define DWC3_DCTL_ACCEPTU2ENA	(1 << 11)
-#define DWC3_DCTL_INITU1ENA	(1 << 10)
-#define DWC3_DCTL_ACCEPTU1ENA	(1 << 9)
-#define DWC3_DCTL_TSTCTRL_MASK	(0xf << 1)
+#define DWC3_DCTL_KEEP_CONNECT		(1 << 19)
+#define DWC3_DCTL_L1_HIBER_EN		(1 << 18)
+#define DWC3_DCTL_CRS			(1 << 17)
+#define DWC3_DCTL_CSS			(1 << 16)
+
+#define DWC3_DCTL_INITU2ENA		(1 << 12)
+#define DWC3_DCTL_ACCEPTU2ENA		(1 << 11)
+#define DWC3_DCTL_INITU1ENA		(1 << 10)
+#define DWC3_DCTL_ACCEPTU1ENA		(1 << 9)
+#define DWC3_DCTL_TSTCTRL_MASK		(0xf << 1)
 
 #define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
@@ -665,6 +668,8 @@ struct dwc3_scratchpad_array {
  * @ep0_bounced: true when we used bounce buffer
  * @ep0_expect_in: true when we expect a DATA IN transfer
  * @has_hibernation: true when dwc3 was configured with Hibernation
+ * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
+ *			there's now way for software to detect this in runtime.
  * @is_selfpowered: true when we are selfpowered
  * @is_fpga: true when we are using the FPGA board
  * @needs_fifo_resize: not all users might want fifo resizing, flag it
@@ -771,6 +776,7 @@ struct dwc3 {
 	unsigned		ep0_bounced:1;
 	unsigned		ep0_expect_in:1;
 	unsigned		has_hibernation:1;
+	unsigned		has_lpm_erratum:1;
 	unsigned		is_selfpowered:1;
 	unsigned		is_fpga:1;
 	unsigned		needs_fifo_resize:1;
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index a89db6c..bbe946c 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -148,6 +148,7 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 
 	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
 			PCI_DEVICE_ID_AMD_NL) {
+		dwc3_pdata.has_lpm_erratum = true;
 		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
 	}
 
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 1f2a719..33bfc70 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1581,6 +1581,13 @@ static int dwc3_gadget_start(struct usb_gadget *g,
 	}
 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 
+	if (dwc->has_lpm_erratum) {
+		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
+		/* REVISIT should this be configurable ? */
+		reg |= DWC3_DCTL_LPM_ERRATA(0xf);
+		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
+	}
+
 	dwc->start_config_issued = false;
 
 	/* Start with SuperSpeed Default */
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 9c5f074..098ab04 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -25,6 +25,7 @@ struct dwc3_platform_data {
 	enum usb_dr_mode dr_mode;
 	bool tx_fifo_resize;
 
+	unsigned has_lpm_erratum:1;
 	u32     quirks;
 
 #define DWC3_QUIRK_AMD_NL		(1 << 0)
-- 
1.9.1

[PATCH v2 08/16] usb: dwc3: add u2exit lfps quirk

[Huang Rui]

AMD NL needs to enable u2exit lfps quirk.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 4 ++++
 drivers/usb/dwc3/core.h          | 1 +
 drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
 drivers/usb/dwc3/platform_data.h | 1 +
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 25db533..7322d85 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -467,6 +467,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
 		reg |= DWC3_GCTL_DISSCRAMBLE;
 	else
 		reg &= ~DWC3_GCTL_DISSCRAMBLE;
+
+	if (dwc->quirks & DWC3_QUIRK_U2EXIT_LFPS)
+		reg |= DWC3_GCTL_U2EXIT_LFPS;
+
 	/*
 	 * WORKAROUND: DWC3 revisions <1.90a have a bug
 	 * where the device can fail to connect at SuperSpeed
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index d58479e..3d27f10 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -166,6 +166,7 @@
 #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
 #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
 #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)
+#define DWC3_GCTL_U2EXIT_LFPS		(1 << 2)
 #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
 #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
 
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index bbe946c..cdb9b04 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -149,7 +149,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
 			PCI_DEVICE_ID_AMD_NL) {
 		dwc3_pdata.has_lpm_erratum = true;
-		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
+		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
+			| DWC3_QUIRK_U2EXIT_LFPS;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 098ab04..a6463c0 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -30,5 +30,6 @@ struct dwc3_platform_data {
 
 #define DWC3_QUIRK_AMD_NL		(1 << 0)
 #define DWC3_QUIRK_DISSCRAMBLE		(1 << 1)
+#define DWC3_QUIRK_U2EXIT_LFPS		(1 << 2)
 
 };
-- 
1.9.1

[PATCH v2 09/16] usb: dwc3: add P3 in U2 SS inactive quirk

[Huang Rui]

AMD NL needs to enable P3 OK for U2/SSInactive on USB3PIPE register.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 20 ++++++++++++++++++++
 drivers/usb/dwc3/core.h          |  1 +
 drivers/usb/dwc3/dwc3-pci.c      |  3 ++-
 drivers/usb/dwc3/platform_data.h |  1 +
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 7322d85..9d0a249 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -365,6 +365,24 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
 }
 
 /**
+ * dwc3_phy_setup - Configure USB3 PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ */
+static void dwc3_phy_setup(struct dwc3 *dwc)
+{
+	u32 reg;
+
+	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+
+	if (dwc->quirks & DWC3_QUIRK_U2SSINP3OK)
+		reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
+
+	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+
+	mdelay(100);
+}
+
+/**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
  *
@@ -484,6 +502,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
 
 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 
+	dwc3_phy_setup(dwc);
+
 	ret = dwc3_alloc_scratch_buffers(dwc);
 	if (ret)
 		goto err1;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 3d27f10..71cb255 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -176,6 +176,7 @@
 
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
+#define DWC3_GUSB3PIPECTL_U2SSINP3OK	(1 << 29)
 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
 
 /* Global TX Fifo Size Register */
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index cdb9b04..1235eb3 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -150,7 +150,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 			PCI_DEVICE_ID_AMD_NL) {
 		dwc3_pdata.has_lpm_erratum = true;
 		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
-			| DWC3_QUIRK_U2EXIT_LFPS;
+			| DWC3_QUIRK_U2EXIT_LFPS
+			| DWC3_QUIRK_U2SSINP3OK;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index a6463c0..ad03563 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -31,5 +31,6 @@ struct dwc3_platform_data {
 #define DWC3_QUIRK_AMD_NL		(1 << 0)
 #define DWC3_QUIRK_DISSCRAMBLE		(1 << 1)
 #define DWC3_QUIRK_U2EXIT_LFPS		(1 << 2)
+#define DWC3_QUIRK_U2SSINP3OK		(1 << 3)
 
 };
-- 
1.9.1

[PATCH v2 10/16] usb: dwc3: add request p1p2p3 quirk

[Huang Rui]

AMD NL needs to enable always request P1/P2/P3 for U1/U2/U3 for AMD own phy.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 3 +++
 drivers/usb/dwc3/core.h          | 1 +
 drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
 drivers/usb/dwc3/platform_data.h | 1 +
 4 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 9d0a249..ec8b667 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -377,6 +377,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->quirks & DWC3_QUIRK_U2SSINP3OK)
 		reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 
+	if (dwc->quirks & DWC3_QUIRK_REQP1P2P3)
+		reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	mdelay(100);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 71cb255..8f47ade18 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -177,6 +177,7 @@
 /* Global USB3 PIPE Control Register */
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB3PIPECTL_U2SSINP3OK	(1 << 29)
+#define DWC3_GUSB3PIPECTL_REQP1P2P3	(1 << 24)
 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
 
 /* Global TX Fifo Size Register */
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 1235eb3..7154d18 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -151,7 +151,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 		dwc3_pdata.has_lpm_erratum = true;
 		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
 			| DWC3_QUIRK_U2EXIT_LFPS
-			| DWC3_QUIRK_U2SSINP3OK;
+			| DWC3_QUIRK_U2SSINP3OK
+			| DWC3_QUIRK_REQP1P2P3;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index ad03563..850883f 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -32,5 +32,6 @@ struct dwc3_platform_data {
 #define DWC3_QUIRK_DISSCRAMBLE		(1 << 1)
 #define DWC3_QUIRK_U2EXIT_LFPS		(1 << 2)
 #define DWC3_QUIRK_U2SSINP3OK		(1 << 3)
+#define DWC3_QUIRK_REQP1P2P3		(1 << 4)
 
 };
-- 
1.9.1

[PATCH v2 11/16] usb: dwc3: add delay p1p2p3 quirk

[Huang Rui]

AMD NL needs to delay P0 to P1/P2/P3 request when entering U1/U2/U3.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 3 +++
 drivers/usb/dwc3/core.h          | 2 ++
 drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
 drivers/usb/dwc3/platform_data.h | 1 +
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ec8b667..a9f1d4c 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -380,6 +380,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->quirks & DWC3_QUIRK_REQP1P2P3)
 		reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 
+	if (dwc->quirks & DWC3_QUIRK_DEPP1P2P3)
+		reg |= DWC3_GUSB3PIPECTL_DEP1P2P3(1);
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	mdelay(100);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 8f47ade18..cf70fa6 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -178,6 +178,8 @@
 #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
 #define DWC3_GUSB3PIPECTL_U2SSINP3OK	(1 << 29)
 #define DWC3_GUSB3PIPECTL_REQP1P2P3	(1 << 24)
+#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK	DWC3_GUSB3PIPECTL_DEP1P2P3(7)
+#define DWC3_GUSB3PIPECTL_DEP1P2P3(n)	((n) << 19)
 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
 
 /* Global TX Fifo Size Register */
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 7154d18..23ae6a7 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -152,7 +152,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
 			| DWC3_QUIRK_U2EXIT_LFPS
 			| DWC3_QUIRK_U2SSINP3OK
-			| DWC3_QUIRK_REQP1P2P3;
+			| DWC3_QUIRK_REQP1P2P3
+			| DWC3_QUIRK_DEPP1P2P3;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 850883f..e668c1f 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -33,5 +33,6 @@ struct dwc3_platform_data {
 #define DWC3_QUIRK_U2EXIT_LFPS		(1 << 2)
 #define DWC3_QUIRK_U2SSINP3OK		(1 << 3)
 #define DWC3_QUIRK_REQP1P2P3		(1 << 4)
+#define DWC3_QUIRK_DEPP1P2P3		(1 << 5)
 
 };
-- 
1.9.1

[PATCH v2 12/16] usb: dwc3: add delay phy power change quirk

[Huang Rui]

AMD NL needs to delay PHY power change from P0 to P1/P2/P3 when link state
changing from U0 to U1/U2/U3 respectively.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 3 +++
 drivers/usb/dwc3/core.h          | 1 +
 drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
 drivers/usb/dwc3/platform_data.h | 1 +
 4 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index a9f1d4c..920a8ab 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -383,6 +383,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->quirks & DWC3_QUIRK_DEPP1P2P3)
 		reg |= DWC3_GUSB3PIPECTL_DEP1P2P3(1);
 
+	if (dwc->quirks & DWC3_QUIRK_DEPOCHANGE)
+		reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	mdelay(100);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index cf70fa6..4c0200f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -180,6 +180,7 @@
 #define DWC3_GUSB3PIPECTL_REQP1P2P3	(1 << 24)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK	DWC3_GUSB3PIPECTL_DEP1P2P3(7)
 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)	((n) << 19)
+#define DWC3_GUSB3PIPECTL_DEPOCHANGE	(1 << 18)
 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
 
 /* Global TX Fifo Size Register */
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 23ae6a7..0eb8b2a 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -153,7 +153,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 			| DWC3_QUIRK_U2EXIT_LFPS
 			| DWC3_QUIRK_U2SSINP3OK
 			| DWC3_QUIRK_REQP1P2P3
-			| DWC3_QUIRK_DEPP1P2P3;
+			| DWC3_QUIRK_DEPP1P2P3
+			| DWC3_QUIRK_DEPOCHANGE;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index e668c1f..934c5e1 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -34,5 +34,6 @@ struct dwc3_platform_data {
 #define DWC3_QUIRK_U2SSINP3OK		(1 << 3)
 #define DWC3_QUIRK_REQP1P2P3		(1 << 4)
 #define DWC3_QUIRK_DEPP1P2P3		(1 << 5)
+#define DWC3_QUIRK_DEPOCHANGE		(1 << 6)
 
 };
-- 
1.9.1

[PATCH v2 13/16] usb: dwc3: add lfps filter quirk

[Huang Rui]

AMD NL needs to enable lfps filter quirk.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 3 +++
 drivers/usb/dwc3/core.h          | 1 +
 drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
 drivers/usb/dwc3/platform_data.h | 1 +
 4 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 920a8ab..a1ee586 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -386,6 +386,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->quirks & DWC3_QUIRK_DEPOCHANGE)
 		reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 
+	if (dwc->quirks & DWC3_QUIRK_LFPSFILT)
+		reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	mdelay(100);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4c0200f..5bdd5f5 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -182,6 +182,7 @@
 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n)	((n) << 19)
 #define DWC3_GUSB3PIPECTL_DEPOCHANGE	(1 << 18)
 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
+#define DWC3_GUSB3PIPECTL_LFPSFILT	(1 << 9)
 
 /* Global TX Fifo Size Register */
 #define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 0eb8b2a..d1f0901 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -154,7 +154,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 			| DWC3_QUIRK_U2SSINP3OK
 			| DWC3_QUIRK_REQP1P2P3
 			| DWC3_QUIRK_DEPP1P2P3
-			| DWC3_QUIRK_DEPOCHANGE;
+			| DWC3_QUIRK_DEPOCHANGE
+			| DWC3_QUIRK_LFPSFILT;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 934c5e1..ac7860ab 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -35,5 +35,6 @@ struct dwc3_platform_data {
 #define DWC3_QUIRK_REQP1P2P3		(1 << 4)
 #define DWC3_QUIRK_DEPP1P2P3		(1 << 5)
 #define DWC3_QUIRK_DEPOCHANGE		(1 << 6)
+#define DWC3_QUIRK_LFPSFILT		(1 << 7)
 
 };
-- 
1.9.1

[PATCH v2 14/16] usb: dwc3: enable rx_detect to polling lfps quirk

[Huang Rui]

AMD NL needs to enable RX_DETECT to Polling.LFPS control quirk.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 3 +++
 drivers/usb/dwc3/core.h          | 1 +
 drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
 drivers/usb/dwc3/platform_data.h | 1 +
 4 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index a1ee586..f3c9699 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -389,6 +389,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->quirks & DWC3_QUIRK_LFPSFILT)
 		reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 
+	if (dwc->quirks & DWC3_QUIRK_RX_DETOPOLL)
+		reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	mdelay(100);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 5bdd5f5..1952759 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -183,6 +183,7 @@
 #define DWC3_GUSB3PIPECTL_DEPOCHANGE	(1 << 18)
 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
 #define DWC3_GUSB3PIPECTL_LFPSFILT	(1 << 9)
+#define DWC3_GUSB3PIPECTL_RX_DETOPOLL	(1 << 8)
 
 /* Global TX Fifo Size Register */
 #define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index d1f0901..6f789fd 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -155,7 +155,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 			| DWC3_QUIRK_REQP1P2P3
 			| DWC3_QUIRK_DEPP1P2P3
 			| DWC3_QUIRK_DEPOCHANGE
-			| DWC3_QUIRK_LFPSFILT;
+			| DWC3_QUIRK_LFPSFILT
+			| DWC3_QUIRK_RX_DETOPOLL;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index ac7860ab..5df3419 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -36,5 +36,6 @@ struct dwc3_platform_data {
 #define DWC3_QUIRK_DEPP1P2P3		(1 << 5)
 #define DWC3_QUIRK_DEPOCHANGE		(1 << 6)
 #define DWC3_QUIRK_LFPSFILT		(1 << 7)
+#define DWC3_QUIRK_RX_DETOPOLL		(1 << 8)
 
 };
-- 
1.9.1

[PATCH v2 15/16] usb: dwc3: add tx demphasis quirk

[Huang Rui]

AMD NL needs to enable Tx Deemphasis quirk.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 3 +++
 drivers/usb/dwc3/core.h          | 2 ++
 drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
 drivers/usb/dwc3/platform_data.h | 1 +
 4 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index f3c9699..3ccfe41 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -392,6 +392,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->quirks & DWC3_QUIRK_RX_DETOPOLL)
 		reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 
+	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
+		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	mdelay(100);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 1952759..1b137f4 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -184,6 +184,8 @@
 #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
 #define DWC3_GUSB3PIPECTL_LFPSFILT	(1 << 9)
 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL	(1 << 8)
+#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK	DWC3_GUSB3PIPECTL_TX_DEEPH(3)
+#define DWC3_GUSB3PIPECTL_TX_DEEPH(n)	((n) << 1)
 
 /* Global TX Fifo Size Register */
 #define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 6f789fd..146eb2f 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -156,7 +156,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 			| DWC3_QUIRK_DEPP1P2P3
 			| DWC3_QUIRK_DEPOCHANGE
 			| DWC3_QUIRK_LFPSFILT
-			| DWC3_QUIRK_RX_DETOPOLL;
+			| DWC3_QUIRK_RX_DETOPOLL
+			| DWC3_QUIRK_TX_DEEPH;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 5df3419..54f0e45 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -37,5 +37,6 @@ struct dwc3_platform_data {
 #define DWC3_QUIRK_DEPOCHANGE		(1 << 6)
 #define DWC3_QUIRK_LFPSFILT		(1 << 7)
 #define DWC3_QUIRK_RX_DETOPOLL		(1 << 8)
+#define DWC3_QUIRK_TX_DEEPH		(1 << 9)
 
 };
-- 
1.9.1

[PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Huang Rui]

AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
board.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/usb/dwc3/core.c          | 7 ++++++-
 drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
 drivers/usb/dwc3/platform_data.h | 1 +
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 3ccfe41..4a98696 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
 		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
 
+	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
+		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	mdelay(100);
@@ -496,8 +499,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
 		dwc->is_fpga = true;
 	}
 
-	if ((dwc->quirks & DWC3_QUIRK_AMD_NL) && dwc->is_fpga)
+	if ((dwc->quirks & DWC3_QUIRK_AMD_NL) && dwc->is_fpga) {
 		dwc->quirks |= DWC3_QUIRK_DISSCRAMBLE;
+		dwc->quirks &= ~DWC3_QUIRK_SUSPHY;
+	}
 
 	if (dwc->quirks & DWC3_QUIRK_DISSCRAMBLE)
 		reg |= DWC3_GCTL_DISSCRAMBLE;
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 146eb2f..71401a3 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -157,7 +157,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
 			| DWC3_QUIRK_DEPOCHANGE
 			| DWC3_QUIRK_LFPSFILT
 			| DWC3_QUIRK_RX_DETOPOLL
-			| DWC3_QUIRK_TX_DEEPH;
+			| DWC3_QUIRK_TX_DEEPH
+			| DWC3_QUIRK_SUSPHY;
 	}
 
 	ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
index 54f0e45..f68cd97 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -38,5 +38,6 @@ struct dwc3_platform_data {
 #define DWC3_QUIRK_LFPSFILT		(1 << 7)
 #define DWC3_QUIRK_RX_DETOPOLL		(1 << 8)
 #define DWC3_QUIRK_TX_DEEPH		(1 << 9)
+#define DWC3_QUIRK_SUSPHY		(1 << 10)
 
 };
-- 
1.9.1

Re: [PATCH v2 05/16] usb: dwc3: add quirks support to be compatible for kinds of SoCs

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 3572 bytes --]

HI,

On Fri, Oct 17, 2014 at 04:53:30PM +0800, Huang Rui wrote:
> This patch adds a quirks flag at dwc3 structure, and SoCs platform vendor is
> able to define this flag in platform data at bus glue layer. Then do some
> independent behaviors at dwc3 core level.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 2 ++
>  drivers/usb/dwc3/core.h          | 3 +++
>  drivers/usb/dwc3/dwc3-pci.c      | 9 +++++++++
>  drivers/usb/dwc3/platform_data.h | 2 ++
>  4 files changed, 16 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ddac372..50c0eae 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -710,6 +710,8 @@ static int dwc3_probe(struct platform_device *pdev)
>  
>  		dwc->needs_fifo_resize = pdata->tx_fifo_resize;
>  		dwc->dr_mode = pdata->dr_mode;
> +
> +		dwc->quirks = pdata->quirks;
>  	}
>  
>  	/* default to superspeed if no maximum_speed passed */
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index f6ee623..cfe0d57 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -636,6 +636,7 @@ struct dwc3_scratchpad_array {
>   * @u1u2: only used on revisions <1.83a for workaround
>   * @maximum_speed: maximum speed requested (mainly for testing purposes)
>   * @revision: revision register contents
> + * @quirks: represents different SOCs hardware work-arounds and quirks
>   * @dr_mode: requested mode of operation
>   * @usb2_phy: pointer to USB2 PHY
>   * @usb3_phy: pointer to USB3 PHY
> @@ -740,6 +741,8 @@ struct dwc3 {
>  #define DWC3_REVISION_270A	0x5533270a
>  #define DWC3_REVISION_280A	0x5533280a
>  
> +	u32			quirks;
> +
>  	enum dwc3_ep0_next	ep0_next_event;
>  	enum dwc3_ep0_state	ep0state;
>  	enum dwc3_link_state	link_state;
> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 3806547..18569a4 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -25,6 +25,8 @@
>  #include <linux/usb/otg.h>
>  #include <linux/usb/usb_phy_generic.h>
>  
> +#include "platform_data.h"
> +
>  /* FIXME define these in <linux/pci_ids.h> */
>  #define PCI_VENDOR_ID_SYNOPSYS		0x16c3
>  #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3	0xabcd
> @@ -103,6 +105,9 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  	struct dwc3_pci		*glue;
>  	int			ret;
>  	struct device		*dev = &pci->dev;
> +	struct dwc3_platform_data dwc3_pdata;
> +
> +	memset(&dwc3_pdata, 0x00, sizeof(dwc3_pdata));
>  
>  	glue = devm_kzalloc(dev, sizeof(*glue), GFP_KERNEL);
>  	if (!glue)
> @@ -149,6 +154,10 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  
>  	pci_set_drvdata(pci, glue);
>  
> +	ret = platform_device_add_data(dwc3, &dwc3_pdata, sizeof(dwc3_pdata));
> +	if (ret)
> +		goto err3;
> +
>  	dma_set_coherent_mask(&dwc3->dev, dev->coherent_dma_mask);
>  
>  	dwc3->dev.dma_mask = dev->dma_mask;
> diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
> index 7db34f0..1d3d65f 100644
> --- a/drivers/usb/dwc3/platform_data.h
> +++ b/drivers/usb/dwc3/platform_data.h
> @@ -24,4 +24,6 @@ struct dwc3_platform_data {
>  	enum usb_device_speed maximum_speed;
>  	enum usb_dr_mode dr_mode;
>  	bool tx_fifo_resize;
> +
> +	u32     quirks;

I prefer to have one-bit fields like we already have for delayed_status,
ep0_bounced, ep0_expect_in, and so on. That makes it easier to support
the same quirks through devicetree as well.

-- 
balbi

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

Re: [PATCH v2 06/16] usb: dwc3: add disscramble quirk

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 2331 bytes --]

Hi,

On Fri, Oct 17, 2014 at 04:53:31PM +0800, Huang Rui wrote:
> AMD NL fpga needs to enable disscramble quirk. And this quirk doesn't need on
> the true soc.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 8 +++++++-
>  drivers/usb/dwc3/dwc3-pci.c      | 5 +++++
>  drivers/usb/dwc3/platform_data.h | 4 ++++
>  3 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 50c0eae..819e501 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -422,7 +422,6 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  
>  	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
>  	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> -	reg &= ~DWC3_GCTL_DISSCRAMBLE;
>  
>  	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
>  	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
> @@ -461,6 +460,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  		dwc->is_fpga = true;
>  	}
>  
> +	if ((dwc->quirks & DWC3_QUIRK_AMD_NL) && dwc->is_fpga)
> +		dwc->quirks |= DWC3_QUIRK_DISSCRAMBLE;
> +
> +	if (dwc->quirks & DWC3_QUIRK_DISSCRAMBLE)

this should only be set if is_fpga, and this quirk should be a 1-bit
flag, so here's what you should do:

	WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
		"disable_scramble cannot be used on non-FPGA builds\n");

	if (dwc->disable_scramble && dwc->is_fpga)
		reg |= DWC3_GCTL_DISSCRAMBLE;
	else
		reg &= ~DWC3_GCTL_DISSCRAMBLE;

> +		reg |= DWC3_GCTL_DISSCRAMBLE;
> +	else
> +		reg &= ~DWC3_GCTL_DISSCRAMBLE;

add a blank line here, to aid readability.

>  	/*
>  	 * WORKAROUND: DWC3 revisions <1.90a have a bug
>  	 * where the device can fail to connect at SuperSpeed
> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 18569a4..a89db6c 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -146,6 +146,11 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  	res[1].name	= "dwc_usb3";
>  	res[1].flags	= IORESOURCE_IRQ;
>  
> +	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> +			PCI_DEVICE_ID_AMD_NL) {
> +		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> +	}

should be part of another patch and the quirk is
"disable_scramble_quirk", not AMD.

-- 
balbi

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Re: [PATCH v2 07/16] usb: dwc3: add lpm erratum support

[Felipe Balbi]

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On Fri, Oct 17, 2014 at 04:53:32PM +0800, Huang Rui wrote:
> When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced Configuration
> of coreConsultant, it supports of xHCI BESL Errata Dated 10/19/2011 is enabled
> in host mode. In device mode it adds the capability to send NYET response based
> on the BESL value received in the LPM token.
> 
> This patch add an entry that soc platform is able to define the lpm capacity
> with their own device tree or bus glue layer.
> 
> Suggested-by: Felipe Balbi <balbi@ti.com>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          |  2 ++
>  drivers/usb/dwc3/core.h          | 24 +++++++++++++++---------
>  drivers/usb/dwc3/dwc3-pci.c      |  1 +
>  drivers/usb/dwc3/gadget.c        |  7 +++++++
>  drivers/usb/dwc3/platform_data.h |  1 +
>  5 files changed, 26 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 819e501..25db533 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -708,11 +708,13 @@ static int dwc3_probe(struct platform_device *pdev)
>  
>  	if (node) {
>  		dwc->maximum_speed = of_usb_get_maximum_speed(node);
> +		dwc->has_lpm_erratum = of_property_read_bool(node, "snps,has-lpm-erratum");
>  
>  		dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
>  		dwc->dr_mode = of_usb_get_dr_mode(node);
>  	} else if (pdata) {
>  		dwc->maximum_speed = pdata->maximum_speed;
> +		dwc->has_lpm_erratum = pdata->has_lpm_erratum;
>  
>  		dwc->needs_fifo_resize = pdata->tx_fifo_resize;
>  		dwc->dr_mode = pdata->dr_mode;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index cfe0d57..d58479e 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -246,16 +246,19 @@
>  #define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))
>  
>  /* These apply for core versions 1.94a and later */
> -#define DWC3_DCTL_KEEP_CONNECT	(1 << 19)
> -#define DWC3_DCTL_L1_HIBER_EN	(1 << 18)
> -#define DWC3_DCTL_CRS		(1 << 17)
> -#define DWC3_DCTL_CSS		(1 << 16)
> +#define DWC3_DCTL_LPM_ERRATA_MASK	DWC3_DCTL_LPM_ERRATA(0xf)
> +#define DWC3_DCTL_LPM_ERRATA(n)		((n) << 20)
> -#define DWC3_DCTL_INITU2ENA	(1 << 12)
> -#define DWC3_DCTL_ACCEPTU2ENA	(1 << 11)
> -#define DWC3_DCTL_INITU1ENA	(1 << 10)
> -#define DWC3_DCTL_ACCEPTU1ENA	(1 << 9)
> -#define DWC3_DCTL_TSTCTRL_MASK	(0xf << 1)
> +#define DWC3_DCTL_KEEP_CONNECT		(1 << 19)
> +#define DWC3_DCTL_L1_HIBER_EN		(1 << 18)
> +#define DWC3_DCTL_CRS			(1 << 17)
> +#define DWC3_DCTL_CSS			(1 << 16)
> +
> +#define DWC3_DCTL_INITU2ENA		(1 << 12)
> +#define DWC3_DCTL_ACCEPTU2ENA		(1 << 11)
> +#define DWC3_DCTL_INITU1ENA		(1 << 10)
> +#define DWC3_DCTL_ACCEPTU1ENA		(1 << 9)
> +#define DWC3_DCTL_TSTCTRL_MASK		(0xf << 1)
>  
>  #define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
>  #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
> @@ -665,6 +668,8 @@ struct dwc3_scratchpad_array {
>   * @ep0_bounced: true when we used bounce buffer
>   * @ep0_expect_in: true when we expect a DATA IN transfer
>   * @has_hibernation: true when dwc3 was configured with Hibernation
> + * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
> + *			there's now way for software to detect this in runtime.
>   * @is_selfpowered: true when we are selfpowered
>   * @is_fpga: true when we are using the FPGA board
>   * @needs_fifo_resize: not all users might want fifo resizing, flag it
> @@ -771,6 +776,7 @@ struct dwc3 {
>  	unsigned		ep0_bounced:1;
>  	unsigned		ep0_expect_in:1;
>  	unsigned		has_hibernation:1;
> +	unsigned		has_lpm_erratum:1;
>  	unsigned		is_selfpowered:1;
>  	unsigned		is_fpga:1;
>  	unsigned		needs_fifo_resize:1;
> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index a89db6c..bbe946c 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -148,6 +148,7 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  
>  	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
>  			PCI_DEVICE_ID_AMD_NL) {
> +		dwc3_pdata.has_lpm_erratum = true;
>  		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
>  	}
>  

let's combine all AMD patches as the last patch in the series so we add
AMD support with all quirks in one place.

> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
> index 1f2a719..33bfc70 100644
> --- a/drivers/usb/dwc3/gadget.c
> +++ b/drivers/usb/dwc3/gadget.c
> @@ -1581,6 +1581,13 @@ static int dwc3_gadget_start(struct usb_gadget *g,
>  	}
>  	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
>  
> +	if (dwc->has_lpm_erratum) {
> +		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
> +		/* REVISIT should this be configurable ? */
> +		reg |= DWC3_DCTL_LPM_ERRATA(0xf);

as Paul mentioned, this should definitely be configurable. So we need to
discuss how to make that configurable too.

-- 
balbi

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Re: [PATCH v2 08/16] usb: dwc3: add u2exit lfps quirk

[Felipe Balbi]

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Hi,

On Fri, Oct 17, 2014 at 04:53:33PM +0800, Huang Rui wrote:
> AMD NL needs to enable u2exit lfps quirk.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 4 ++++
>  drivers/usb/dwc3/core.h          | 1 +
>  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
>  drivers/usb/dwc3/platform_data.h | 1 +
>  4 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 25db533..7322d85 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -467,6 +467,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  		reg |= DWC3_GCTL_DISSCRAMBLE;
>  	else
>  		reg &= ~DWC3_GCTL_DISSCRAMBLE;
> +
> +	if (dwc->quirks & DWC3_QUIRK_U2EXIT_LFPS)

this should be:

	if (dwc->u2_exit_lfps_quirk)

> +		reg |= DWC3_GCTL_U2EXIT_LFPS;
> +
>  	/*
>  	 * WORKAROUND: DWC3 revisions <1.90a have a bug
>  	 * where the device can fail to connect at SuperSpeed
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index d58479e..3d27f10 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -166,6 +166,7 @@
>  #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
>  #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
>  #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)
> +#define DWC3_GCTL_U2EXIT_LFPS		(1 << 2)
>  #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
>  #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
>  
> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index bbe946c..cdb9b04 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -149,7 +149,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
>  			PCI_DEVICE_ID_AMD_NL) {
>  		dwc3_pdata.has_lpm_erratum = true;
> -		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> +		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
> +			| DWC3_QUIRK_U2EXIT_LFPS;
>  	}

should be combined and the last patch in the series.

-- 
balbi

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Re: [PATCH v2 09/16] usb: dwc3: add P3 in U2 SS inactive quirk

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 2549 bytes --]

On Fri, Oct 17, 2014 at 04:53:34PM +0800, Huang Rui wrote:
> AMD NL needs to enable P3 OK for U2/SSInactive on USB3PIPE register.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 20 ++++++++++++++++++++
>  drivers/usb/dwc3/core.h          |  1 +
>  drivers/usb/dwc3/dwc3-pci.c      |  3 ++-
>  drivers/usb/dwc3/platform_data.h |  1 +
>  4 files changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 7322d85..9d0a249 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -365,6 +365,24 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
>  }
>  
>  /**
> + * dwc3_phy_setup - Configure USB3 PHY Interface of DWC3 Core
> + * @dwc: Pointer to our controller context structure
> + */
> +static void dwc3_phy_setup(struct dwc3 *dwc)
> +{
> +	u32 reg;
> +
> +	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
> +
> +	if (dwc->quirks & DWC3_QUIRK_U2SSINP3OK)

	if (dwc->p3_ok_on_ss_inactive_quirk)

> +		reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
> +
> +	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
> +
> +	mdelay(100);
> +}
> +
> +/**
>   * dwc3_core_init - Low-level initialization of DWC3 Core
>   * @dwc: Pointer to our controller context structure
>   *
> @@ -484,6 +502,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  
>  	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
>  
> +	dwc3_phy_setup(dwc);
> +
>  	ret = dwc3_alloc_scratch_buffers(dwc);
>  	if (ret)
>  		goto err1;
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 3d27f10..71cb255 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -176,6 +176,7 @@
>  
>  /* Global USB3 PIPE Control Register */
>  #define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
> +#define DWC3_GUSB3PIPECTL_U2SSINP3OK	(1 << 29)
>  #define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)
>  
>  /* Global TX Fifo Size Register */
> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index cdb9b04..1235eb3 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -150,7 +150,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  			PCI_DEVICE_ID_AMD_NL) {
>  		dwc3_pdata.has_lpm_erratum = true;
>  		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
> -			| DWC3_QUIRK_U2EXIT_LFPS;
> +			| DWC3_QUIRK_U2EXIT_LFPS
> +			| DWC3_QUIRK_U2SSINP3OK;
>  	}

again to be combined in a single patch as the last patch in the series.

-- 
balbi

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Re: [PATCH v2 10/16] usb: dwc3: add request p1p2p3 quirk

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1371 bytes --]

On Fri, Oct 17, 2014 at 04:53:35PM +0800, Huang Rui wrote:
> AMD NL needs to enable always request P1/P2/P3 for U1/U2/U3 for AMD own phy.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 3 +++
>  drivers/usb/dwc3/core.h          | 1 +
>  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
>  drivers/usb/dwc3/platform_data.h | 1 +
>  4 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 9d0a249..ec8b667 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -377,6 +377,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
>  	if (dwc->quirks & DWC3_QUIRK_U2SSINP3OK)
>  		reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
>  
> +	if (dwc->quirks & DWC3_QUIRK_REQP1P2P3)

	if (dwc->request_p1p2p3_quirk)

> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 1235eb3..7154d18 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -151,7 +151,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  		dwc3_pdata.has_lpm_erratum = true;
>  		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
>  			| DWC3_QUIRK_U2EXIT_LFPS
> -			| DWC3_QUIRK_U2SSINP3OK;
> +			| DWC3_QUIRK_U2SSINP3OK
> +			| DWC3_QUIRK_REQP1P2P3;

to be combined with the last patch in this series.

-- 
balbi

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Re: [PATCH v2 11/16] usb: dwc3: add delay p1p2p3 quirk

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1330 bytes --]

Hi,

On Fri, Oct 17, 2014 at 04:53:36PM +0800, Huang Rui wrote:
> AMD NL needs to delay P0 to P1/P2/P3 request when entering U1/U2/U3.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 3 +++
>  drivers/usb/dwc3/core.h          | 2 ++
>  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
>  drivers/usb/dwc3/platform_data.h | 1 +
>  4 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ec8b667..a9f1d4c 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -380,6 +380,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
>  	if (dwc->quirks & DWC3_QUIRK_REQP1P2P3)
>  		reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
>  
> +	if (dwc->quirks & DWC3_QUIRK_DEPP1P2P3)

	if (dwc->delay_p1p2p3_quirk)

> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 7154d18..23ae6a7 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -152,7 +152,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
>  			| DWC3_QUIRK_U2EXIT_LFPS
>  			| DWC3_QUIRK_U2SSINP3OK
> -			| DWC3_QUIRK_REQP1P2P3;
> +			| DWC3_QUIRK_REQP1P2P3
> +			| DWC3_QUIRK_DEPP1P2P3;

combined with last patch.

-- 
balbi

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Re: [PATCH v2 12/16] usb: dwc3: add delay phy power change quirk

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1376 bytes --]

Hi,

On Fri, Oct 17, 2014 at 04:53:37PM +0800, Huang Rui wrote:
> AMD NL needs to delay PHY power change from P0 to P1/P2/P3 when link state
> changing from U0 to U1/U2/U3 respectively.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 3 +++
>  drivers/usb/dwc3/core.h          | 1 +
>  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
>  drivers/usb/dwc3/platform_data.h | 1 +
>  4 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index a9f1d4c..920a8ab 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -383,6 +383,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
>  	if (dwc->quirks & DWC3_QUIRK_DEPP1P2P3)
>  		reg |= DWC3_GUSB3PIPECTL_DEP1P2P3(1);
>  
> +	if (dwc->quirks & DWC3_QUIRK_DEPOCHANGE)

	if (dwc->delay_p0_change_quirk)

> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 23ae6a7..0eb8b2a 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -153,7 +153,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  			| DWC3_QUIRK_U2EXIT_LFPS
>  			| DWC3_QUIRK_U2SSINP3OK
>  			| DWC3_QUIRK_REQP1P2P3
> -			| DWC3_QUIRK_DEPP1P2P3;
> +			| DWC3_QUIRK_DEPP1P2P3
> +			| DWC3_QUIRK_DEPOCHANGE;

combined with the last patch

-- 
balbi

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Re: [PATCH v2 13/16] usb: dwc3: add lfps filter quirk

[Felipe Balbi]

[-- Attachment #1: Type: text/plain, Size: 1264 bytes --]

On Fri, Oct 17, 2014 at 04:53:38PM +0800, Huang Rui wrote:
> AMD NL needs to enable lfps filter quirk.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 3 +++
>  drivers/usb/dwc3/core.h          | 1 +
>  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
>  drivers/usb/dwc3/platform_data.h | 1 +
>  4 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 920a8ab..a1ee586 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -386,6 +386,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
>  	if (dwc->quirks & DWC3_QUIRK_DEPOCHANGE)
>  		reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
>  
> +	if (dwc->quirks & DWC3_QUIRK_LFPSFILT)

	if (dwc->lfps_filter_quirk)

> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 0eb8b2a..d1f0901 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -154,7 +154,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  			| DWC3_QUIRK_U2SSINP3OK
>  			| DWC3_QUIRK_REQP1P2P3
>  			| DWC3_QUIRK_DEPP1P2P3
> -			| DWC3_QUIRK_DEPOCHANGE;
> +			| DWC3_QUIRK_DEPOCHANGE
> +			| DWC3_QUIRK_LFPSFILT;

last patch

-- 
balbi

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Re: [PATCH v2 14/16] usb: dwc3: enable rx_detect to polling lfps quirk

[Felipe Balbi]

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On Fri, Oct 17, 2014 at 04:53:39PM +0800, Huang Rui wrote:
> AMD NL needs to enable RX_DETECT to Polling.LFPS control quirk.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 3 +++
>  drivers/usb/dwc3/core.h          | 1 +
>  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
>  drivers/usb/dwc3/platform_data.h | 1 +
>  4 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index a1ee586..f3c9699 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -389,6 +389,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
>  	if (dwc->quirks & DWC3_QUIRK_LFPSFILT)
>  		reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
>  
> +	if (dwc->quirks & DWC3_QUIRK_RX_DETOPOLL)

	if (dwc->rx_detect_to_polling_quirk)

> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index d1f0901..6f789fd 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -155,7 +155,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  			| DWC3_QUIRK_REQP1P2P3
>  			| DWC3_QUIRK_DEPP1P2P3
>  			| DWC3_QUIRK_DEPOCHANGE
> -			| DWC3_QUIRK_LFPSFILT;
> +			| DWC3_QUIRK_LFPSFILT
> +			| DWC3_QUIRK_RX_DETOPOLL;

last patch.

-- 
balbi

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Re: [PATCH v2 15/16] usb: dwc3: add tx demphasis quirk

[Felipe Balbi]

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HI,

On Fri, Oct 17, 2014 at 04:53:40PM +0800, Huang Rui wrote:
> AMD NL needs to enable Tx Deemphasis quirk.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 3 +++
>  drivers/usb/dwc3/core.h          | 2 ++
>  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
>  drivers/usb/dwc3/platform_data.h | 1 +
>  4 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index f3c9699..3ccfe41 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -392,6 +392,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
>  	if (dwc->quirks & DWC3_QUIRK_RX_DETOPOLL)
>  		reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
>  
> +	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)

	if (dwc->tx_deemphasis_quirk)

> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 6f789fd..146eb2f 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -156,7 +156,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  			| DWC3_QUIRK_DEPP1P2P3
>  			| DWC3_QUIRK_DEPOCHANGE
>  			| DWC3_QUIRK_LFPSFILT
> -			| DWC3_QUIRK_RX_DETOPOLL;
> +			| DWC3_QUIRK_RX_DETOPOLL
> +			| DWC3_QUIRK_TX_DEEPH;

last patch.

-- 
balbi

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Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Felipe Balbi]

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Hi,

On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> board.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/usb/dwc3/core.c          | 7 ++++++-
>  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
>  drivers/usb/dwc3/platform_data.h | 1 +
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 3ccfe41..4a98696 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
>  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
>  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
>  
> +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)

should be:

	if (!dwc->suspend_usb3_phy_quirk)

> +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;

IIRC, databook asks us to set that bit anyway, so the quirk is disabling
that bit. Am I missing something ? Paul ?

> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 146eb2f..71401a3 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -157,7 +157,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
>  			| DWC3_QUIRK_DEPOCHANGE
>  			| DWC3_QUIRK_LFPSFILT
>  			| DWC3_QUIRK_RX_DETOPOLL
> -			| DWC3_QUIRK_TX_DEEPH;
> +			| DWC3_QUIRK_TX_DEEPH
> +			| DWC3_QUIRK_SUSPHY;

last patch

-- 
balbi

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Re: [PATCH v2 01/16] usb: dwc3: add AMD NL support

[Felipe Balbi]

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HI,

On Fri, Oct 17, 2014 at 04:53:26PM +0800, Huang Rui wrote:
> Add PCI device ID of AMD NL SoC.
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>

this should be the last patch in the series, with all quirk flags
already in place. This avoids bisection points where AMD's platform
won't work.

-- 
balbi

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Re: [PATCH v2 00/16] usb: dwc3: add support for AMD NL SoC

[Felipe Balbi]

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Hi,

On Fri, Oct 17, 2014 at 04:53:25PM +0800, Huang Rui wrote:
> The series of patches add AMD NL SoC support for DesignWare USB3 OTG
> IP with PCI bus glue layer. This controller supported hibernation, LPM
> erratum and used the 2.80a IP version and amd own phy. Current
> implementation support both simulation and SoC platform. And already
> tested with gadget zero and msc tool.  It works well on file storage
> gadget.

patches look much, much nicer there are still a few things to fix. A
global set of issues which I see:

1) Let's get confirmation that all those quirks will be needed in
production as well, I have a feeling quite a few of them won't be.

2) All quirks should become 1-bit fields insteads of single-bits on a
32-bit variable.

3) All quirks should have DeviceTree counterparts. They should all
become boolean properties should we can:

	dwc->tx_deemphasis_quirk = of_property_read_bool(node,
		"snps,tx_deemphasis_quirk");

> These patches are generated on balbi/testing/next
> 
> Changes from v1 -> v2
> - remove dual role function temporarily
> - add pci quirk to avoid to bind with xhci driver
> - distinguish between simulation board and soc
> - break down all the special quirks
> 
> 
> Patch 1:
> - add PCI device id into pci bus glue

this guy should be the last in the series, with all AMD quirks being
enabled at once. This will avoid bisection points where AMD's platforms
don't work.

> Patch 2:

this should become as patch one :-)

> - add PCI quirk to avoid to bind with xhci
> 
> Patch 3:
> - enable hibernation
> 
> Patch 4:
> - distinguish between simulation board and soc
> 
> Patch 5:
> - add quirks flag to be compatible for kinds of soc
> 
> Patch 6 - 16:
> - as felipe's suggestion, break down all the special quirks of amd nl
> 
> 
> Patch set already passed all the MSC testing, detailed result is below:
> 
> root@hr-ub:/home/ray/felipe/usb-tools# ./msc.sh -o /dev/sdb1
> test 0e: simple 64k read/write
> test  0: sent      62.50 MB read      22.00 MB/s write      16.33 MB/s ... success

Are you still running with VERBOSE_DEBUG on USB2 ? Here's what I get on
USB2 connected to my PC with DWC3 running on a single-core cortex-a9
board:

$ ./msc -t0 -o /dev/sdh -s 65536 -c 5000
test  0: sent     312.50 MB read      31.63 MB/s write      29.10 MB/s ... success

And with RAM as backend:

$ ./msc -t0 -o /dev/sdh -s 65536 -c 5000
test  0: sent     312.50 MB read      31.64 MB/s write      29.04 MB/s ... success

cheers

-- 
balbi

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RE: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Paul Zimmerman]

> From: Felipe Balbi [mailto:balbi@ti.com]
> Sent: Friday, October 17, 2014 8:00 AM
> 
> On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> > board.
> >
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/usb/dwc3/core.c          | 7 ++++++-
> >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> >  drivers/usb/dwc3/platform_data.h | 1 +
> >  3 files changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 3ccfe41..4a98696 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> >  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> >  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> >
> > +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> 
> should be:
> 
> 	if (!dwc->suspend_usb3_phy_quirk)
> 
> > +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> 
> IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> that bit. Am I missing something ? Paul ?

It looks to me that Huang's patch is enabling that bit, not disabling
it.

Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
series you just posted). According to the databook, both of those
bits should be set to 1 after the core initialization has completed.

So I think the driver should be changed to enable both of those by
default, and then maybe you want quirks to disable them if there is
some platform out there which needs that.

-- 
Paul

Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Felipe Balbi]

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Hi,

On Fri, Oct 17, 2014 at 06:41:04PM +0000, Paul Zimmerman wrote:
> > From: Felipe Balbi [mailto:balbi@ti.com]
> > Sent: Friday, October 17, 2014 8:00 AM
> > 
> > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> > > board.
> > >
> > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > ---
> > >  drivers/usb/dwc3/core.c          | 7 ++++++-
> > >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> > >  drivers/usb/dwc3/platform_data.h | 1 +
> > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 3ccfe41..4a98696 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > >  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > >  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > >
> > > +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > 
> > should be:
> > 
> > 	if (!dwc->suspend_usb3_phy_quirk)
> > 
> > > +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > 
> > IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> > that bit. Am I missing something ? Paul ?
> 
> It looks to me that Huang's patch is enabling that bit, not disabling
> it.

right, but that's what's actually quirky right ? IIRC, Databook asks us
to set usb2 and usb3 suspend phy bits and we're just not doing it.

> Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> series you just posted). According to the databook, both of those
> bits should be set to 1 after the core initialization has completed.

there you go. So unless that quirk bit flag is set, we're safe of
setting SUSPHY bit for everybody.

> So I think the driver should be changed to enable both of those by
> default, and then maybe you want quirks to disable them if there is
> some platform out there which needs that.

Yeah, that's what I thought too :-) Thanks for confirming

-- 
balbi

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Re: [PATCH v2 05/16] usb: dwc3: add quirks support to be compatible for kinds of SoCs

[Huang Rui]

On Fri, Oct 17, 2014 at 09:41:44AM -0500, Felipe Balbi wrote:
> HI,
> 
> On Fri, Oct 17, 2014 at 04:53:30PM +0800, Huang Rui wrote:
> > This patch adds a quirks flag at dwc3 structure, and SoCs platform vendor is
> > able to define this flag in platform data at bus glue layer. Then do some
> > independent behaviors at dwc3 core level.
> > 
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/usb/dwc3/core.c          | 2 ++
> >  drivers/usb/dwc3/core.h          | 3 +++
> >  drivers/usb/dwc3/dwc3-pci.c      | 9 +++++++++
> >  drivers/usb/dwc3/platform_data.h | 2 ++
> >  4 files changed, 16 insertions(+)
> > 

<snip>

> > diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
> > index 7db34f0..1d3d65f 100644
> > --- a/drivers/usb/dwc3/platform_data.h
> > +++ b/drivers/usb/dwc3/platform_data.h
> > @@ -24,4 +24,6 @@ struct dwc3_platform_data {
> >  	enum usb_device_speed maximum_speed;
> >  	enum usb_dr_mode dr_mode;
> >  	bool tx_fifo_resize;
> > +
> > +	u32     quirks;
> 
> I prefer to have one-bit fields like we already have for delayed_status,
> ep0_bounced, ep0_expect_in, and so on. That makes it easier to support
> the same quirks through devicetree as well.
> 

So it should define like below:

struct dwc3_platform_data {
        ...
        unsigned one_quirk:1;
}

Then also defined it in dwc3 structure. And when dwc3 probed, put this
value from glue layer to dwc3, right?

Thanks,
Rui

Re: [PATCH v2 06/16] usb: dwc3: add disscramble quirk

[Huang Rui]

On Fri, Oct 17, 2014 at 09:45:32AM -0500, Felipe Balbi wrote:
> Hi,
> 
> On Fri, Oct 17, 2014 at 04:53:31PM +0800, Huang Rui wrote:
> > AMD NL fpga needs to enable disscramble quirk. And this quirk doesn't need on
> > the true soc.
> > 
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/usb/dwc3/core.c          | 8 +++++++-
> >  drivers/usb/dwc3/dwc3-pci.c      | 5 +++++
> >  drivers/usb/dwc3/platform_data.h | 4 ++++
> >  3 files changed, 16 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 50c0eae..819e501 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -422,7 +422,6 @@ static int dwc3_core_init(struct dwc3 *dwc)
> >  
> >  	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> >  	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> > -	reg &= ~DWC3_GCTL_DISSCRAMBLE;
> >  
> >  	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
> >  	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
> > @@ -461,6 +460,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
> >  		dwc->is_fpga = true;
> >  	}
> >  
> > +	if ((dwc->quirks & DWC3_QUIRK_AMD_NL) && dwc->is_fpga)
> > +		dwc->quirks |= DWC3_QUIRK_DISSCRAMBLE;
> > +
> > +	if (dwc->quirks & DWC3_QUIRK_DISSCRAMBLE)
> 
> this should only be set if is_fpga, and this quirk should be a 1-bit
> flag, so here's what you should do:
> 
> 	WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
> 		"disable_scramble cannot be used on non-FPGA builds\n");
> 
> 	if (dwc->disable_scramble && dwc->is_fpga)
> 		reg |= DWC3_GCTL_DISSCRAMBLE;
> 	else
> 		reg &= ~DWC3_GCTL_DISSCRAMBLE;
> 

OK, will update it in V3.

> > +		reg |= DWC3_GCTL_DISSCRAMBLE;
> > +	else
> > +		reg &= ~DWC3_GCTL_DISSCRAMBLE;
> 
> add a blank line here, to aid readability.
> 

OK, will add it.

> >  	/*
> >  	 * WORKAROUND: DWC3 revisions <1.90a have a bug
> >  	 * where the device can fail to connect at SuperSpeed
> > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > index 18569a4..a89db6c 100644
> > --- a/drivers/usb/dwc3/dwc3-pci.c
> > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > @@ -146,6 +146,11 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> >  	res[1].name	= "dwc_usb3";
> >  	res[1].flags	= IORESOURCE_IRQ;
> >  
> > +	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> > +			PCI_DEVICE_ID_AMD_NL) {
> > +		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> > +	}
> 
> should be part of another patch and the quirk is
> "disable_scramble_quirk", not AMD.
> 

Got it, you would like to keep this patch just for fpga disscramble
quirk and do not add any 3rd platform info, right?

Thanks,
Rui

Re: [PATCH v2 08/16] usb: dwc3: add u2exit lfps quirk

[Huang Rui]

On Fri, Oct 17, 2014 at 09:50:00AM -0500, Felipe Balbi wrote:
> Hi,
> 
> On Fri, Oct 17, 2014 at 04:53:33PM +0800, Huang Rui wrote:
> > AMD NL needs to enable u2exit lfps quirk.
> > 
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/usb/dwc3/core.c          | 4 ++++
> >  drivers/usb/dwc3/core.h          | 1 +
> >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> >  drivers/usb/dwc3/platform_data.h | 1 +
> >  4 files changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 25db533..7322d85 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -467,6 +467,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
> >  		reg |= DWC3_GCTL_DISSCRAMBLE;
> >  	else
> >  		reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > +
> > +	if (dwc->quirks & DWC3_QUIRK_U2EXIT_LFPS)
> 
> this should be:
> 
> 	if (dwc->u2_exit_lfps_quirk)
> 

OK, will update it in V3.

> > +		reg |= DWC3_GCTL_U2EXIT_LFPS;
> > +
> >  	/*
> >  	 * WORKAROUND: DWC3 revisions <1.90a have a bug
> >  	 * where the device can fail to connect at SuperSpeed
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index d58479e..3d27f10 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -166,6 +166,7 @@
> >  #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
> >  #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
> >  #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)
> > +#define DWC3_GCTL_U2EXIT_LFPS		(1 << 2)
> >  #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
> >  #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
> >  
> > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > index bbe946c..cdb9b04 100644
> > --- a/drivers/usb/dwc3/dwc3-pci.c
> > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > @@ -149,7 +149,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> >  	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> >  			PCI_DEVICE_ID_AMD_NL) {
> >  		dwc3_pdata.has_lpm_erratum = true;
> > -		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> > +		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
> > +			| DWC3_QUIRK_U2EXIT_LFPS;
> >  	}
> 
> should be combined and the last patch in the series.
> 

You want to make all the AMD quirks enablement info and device id at
last patch, right?

Thanks,
Rui

Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Huang Rui]

On Fri, Oct 17, 2014 at 01:48:19PM -0500, Felipe Balbi wrote:
> Hi,
> 
> On Fri, Oct 17, 2014 at 06:41:04PM +0000, Paul Zimmerman wrote:
> > > From: Felipe Balbi [mailto:balbi@ti.com]
> > > Sent: Friday, October 17, 2014 8:00 AM
> > > 
> > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> > > > board.
> > > >
> > > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > > ---
> > > >  drivers/usb/dwc3/core.c          | 7 ++++++-
> > > >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> > > >  drivers/usb/dwc3/platform_data.h | 1 +
> > > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > index 3ccfe41..4a98696 100644
> > > > --- a/drivers/usb/dwc3/core.c
> > > > +++ b/drivers/usb/dwc3/core.c
> > > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > > >  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > > >  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > > >
> > > > +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > > 
> > > should be:
> > > 
> > > 	if (!dwc->suspend_usb3_phy_quirk)
> > > 
> > > > +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > > 
> > > IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> > > that bit. Am I missing something ? Paul ?
> > 
> > It looks to me that Huang's patch is enabling that bit, not disabling
> > it.
> 
> right, but that's what's actually quirky right ? IIRC, Databook asks us
> to set usb2 and usb3 suspend phy bits and we're just not doing it.
> 
> > Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> > DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> > series you just posted). According to the databook, both of those
> > bits should be set to 1 after the core initialization has completed.
> 
> there you go. So unless that quirk bit flag is set, we're safe of
> setting SUSPHY bit for everybody.
> 

So I can update to set these two suspend phy bits defaultly in my next
patch set, is it OK? :)

Thanks,
Rui

> > So I think the driver should be changed to enable both of those by
> > default, and then maybe you want quirks to disable them if there is
> > some platform out there which needs that.
> 
> Yeah, that's what I thought too :-) Thanks for confirming
> 
> -- 
> balbi

Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Huang Rui]

On Mon, Oct 20, 2014 at 04:41:54PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 01:48:19PM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 06:41:04PM +0000, Paul Zimmerman wrote:
> > > > From: Felipe Balbi [mailto:balbi@ti.com]
> > > > Sent: Friday, October 17, 2014 8:00 AM
> > > > 
> > > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> > > > > board.
> > > > >
> > > > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > > > ---
> > > > >  drivers/usb/dwc3/core.c          | 7 ++++++-
> > > > >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> > > > >  drivers/usb/dwc3/platform_data.h | 1 +
> > > > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > index 3ccfe41..4a98696 100644
> > > > > --- a/drivers/usb/dwc3/core.c
> > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > > > >  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > > > >  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > > > >
> > > > > +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > > > 
> > > > should be:
> > > > 
> > > > 	if (!dwc->suspend_usb3_phy_quirk)
> > > > 
> > > > > +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > > > 
> > > > IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> > > > that bit. Am I missing something ? Paul ?
> > > 
> > > It looks to me that Huang's patch is enabling that bit, not disabling
> > > it.
> > 
> > right, but that's what's actually quirky right ? IIRC, Databook asks us
> > to set usb2 and usb3 suspend phy bits and we're just not doing it.
> > 
> > > Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> > > DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> > > series you just posted). According to the databook, both of those
> > > bits should be set to 1 after the core initialization has completed.
> > 
> > there you go. So unless that quirk bit flag is set, we're safe of
> > setting SUSPHY bit for everybody.
> > 
> 

I read the databook again, below words (DWC3_GUSB3PIPECTL_SUSPHY) is
copied from databook:

For DRD/OTG configurations, it is recommended that this bit is set to‘
0’ during coreConsultant configuration. If it is set to ’1’, then the
application should clear this bit after power-on reset. Application
needs to set it to ’1’ after the core initialization is completed.
For all other configurations, this bit can be set to ’1’ during core
configuration.

I see it's recommended to set '0' if on DRD/OTG configuration.

Thanks,
Rui

Re: [PATCH v2 00/16] usb: dwc3: add support for AMD NL SoC

[Huang Rui]

On Fri, Oct 17, 2014 at 10:10:26AM -0500, Felipe Balbi wrote:
> Hi,
> 
> On Fri, Oct 17, 2014 at 04:53:25PM +0800, Huang Rui wrote:
> > The series of patches add AMD NL SoC support for DesignWare USB3 OTG
> > IP with PCI bus glue layer. This controller supported hibernation, LPM
> > erratum and used the 2.80a IP version and amd own phy. Current
> > implementation support both simulation and SoC platform. And already
> > tested with gadget zero and msc tool.  It works well on file storage
> > gadget.
> 
> patches look much, much nicer there are still a few things to fix. A
> global set of issues which I see:
> 
> 1) Let's get confirmation that all those quirks will be needed in
> production as well, I have a feeling quite a few of them won't be.
> 
> 2) All quirks should become 1-bit fields insteads of single-bits on a
> 32-bit variable.
> 
> 3) All quirks should have DeviceTree counterparts. They should all
> become boolean properties should we can:
> 
> 	dwc->tx_deemphasis_quirk = of_property_read_bool(node,
> 		"snps,tx_deemphasis_quirk");
> 

Thanks to summarize them. Will update in V3.

> > These patches are generated on balbi/testing/next
> > 
> > Changes from v1 -> v2
> > - remove dual role function temporarily
> > - add pci quirk to avoid to bind with xhci driver
> > - distinguish between simulation board and soc
> > - break down all the special quirks
> > 
> > 
> > Patch 1:
> > - add PCI device id into pci bus glue
> 
> this guy should be the last in the series, with all AMD quirks being
> enabled at once. This will avoid bisection points where AMD's platforms
> don't work.
> 

So all the AMD special configuration and device id should be in one
patch, right?

> > Patch 2:
> 
> this should become as patch one :-)
> 
> > - add PCI quirk to avoid to bind with xhci
> > 
> > Patch 3:
> > - enable hibernation
> > 
> > Patch 4:
> > - distinguish between simulation board and soc
> > 
> > Patch 5:
> > - add quirks flag to be compatible for kinds of soc
> > 
> > Patch 6 - 16:
> > - as felipe's suggestion, break down all the special quirks of amd nl
> > 
> > 
> > Patch set already passed all the MSC testing, detailed result is below:
> > 
> > root@hr-ub:/home/ray/felipe/usb-tools# ./msc.sh -o /dev/sdb1
> > test 0e: simple 64k read/write
> > test  0: sent      62.50 MB read      22.00 MB/s write      16.33 MB/s ... success
> 
> Are you still running with VERBOSE_DEBUG on USB2 ? Here's what I get on
> USB2 connected to my PC with DWC3 running on a single-core cortex-a9
> board:
> 
> $ ./msc -t0 -o /dev/sdh -s 65536 -c 5000
> test  0: sent     312.50 MB read      31.63 MB/s write      29.10 MB/s ... success
> 
> And with RAM as backend:
> 
> $ ./msc -t0 -o /dev/sdh -s 65536 -c 5000
> test  0: sent     312.50 MB read      31.64 MB/s write      29.04 MB/s ... success
> 

Yes, I will disable DEBUG option to test again.

Thanks,
Rui

RE: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Paul Zimmerman]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 3423 bytes --]

> From: Huang Rui [mailto:ray.huang@amd.com]
> Sent: Monday, October 20, 2014 2:01 AM
> 
> On Mon, Oct 20, 2014 at 04:41:54PM +0800, Huang Rui wrote:
> > On Fri, Oct 17, 2014 at 01:48:19PM -0500, Felipe Balbi wrote:
> > > Hi,
> > >
> > > On Fri, Oct 17, 2014 at 06:41:04PM +0000, Paul Zimmerman wrote:
> > > > > From: Felipe Balbi [mailto:balbi@ti.com]
> > > > > Sent: Friday, October 17, 2014 8:00 AM
> > > > >
> > > > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > > > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> > > > > > board.
> > > > > >
> > > > > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > > > > ---
> > > > > >  drivers/usb/dwc3/core.c          | 7 ++++++-
> > > > > >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> > > > > >  drivers/usb/dwc3/platform_data.h | 1 +
> > > > > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > > index 3ccfe41..4a98696 100644
> > > > > > --- a/drivers/usb/dwc3/core.c
> > > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > > > > >  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > > > > >  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > > > > >
> > > > > > +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > > > >
> > > > > should be:
> > > > >
> > > > > 	if (!dwc->suspend_usb3_phy_quirk)
> > > > >
> > > > > > +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > > > >
> > > > > IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> > > > > that bit. Am I missing something ? Paul ?
> > > >
> > > > It looks to me that Huang's patch is enabling that bit, not disabling
> > > > it.
> > >
> > > right, but that's what's actually quirky right ? IIRC, Databook asks us
> > > to set usb2 and usb3 suspend phy bits and we're just not doing it.
> > >
> > > > Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> > > > DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> > > > series you just posted). According to the databook, both of those
> > > > bits should be set to 1 after the core initialization has completed.
> > >
> > > there you go. So unless that quirk bit flag is set, we're safe of
> > > setting SUSPHY bit for everybody.
> > >
> >
> 
> I read the databook again, below words (DWC3_GUSB3PIPECTL_SUSPHY) is
> copied from databook:
> 
> For DRD/OTG configurations, it is recommended that this bit is set to‘
> 0’ during coreConsultant configuration. If it is set to ’1’, then the
> application should clear this bit after power-on reset. Application
> needs to set it to ’1’ after the core initialization is completed.
> For all other configurations, this bit can be set to ’1’ during core
> configuration.
> 
> I see it's recommended to set '0' if on DRD/OTG configuration.

No, it's recommended to set it to '0' during coreConsultant
configuration. This is a part of the synthesis process, i.e. when
building the RTL for the SoC. This determines what the default value
of the bit will be when the core is reset. At runtime it is still
recommended to set it to '1' when in device mode, after the core
initialization is completed.

-- 
Paul

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Re: [PATCH v2 05/16] usb: dwc3: add quirks support to be compatible for kinds of SoCs

[Felipe Balbi]

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On Mon, Oct 20, 2014 at 02:02:17PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 09:41:44AM -0500, Felipe Balbi wrote:
> > HI,
> > 
> > On Fri, Oct 17, 2014 at 04:53:30PM +0800, Huang Rui wrote:
> > > This patch adds a quirks flag at dwc3 structure, and SoCs platform vendor is
> > > able to define this flag in platform data at bus glue layer. Then do some
> > > independent behaviors at dwc3 core level.
> > > 
> > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > ---
> > >  drivers/usb/dwc3/core.c          | 2 ++
> > >  drivers/usb/dwc3/core.h          | 3 +++
> > >  drivers/usb/dwc3/dwc3-pci.c      | 9 +++++++++
> > >  drivers/usb/dwc3/platform_data.h | 2 ++
> > >  4 files changed, 16 insertions(+)
> > > 
> 
> <snip>
> 
> > > diff --git a/drivers/usb/dwc3/platform_data.h b/drivers/usb/dwc3/platform_data.h
> > > index 7db34f0..1d3d65f 100644
> > > --- a/drivers/usb/dwc3/platform_data.h
> > > +++ b/drivers/usb/dwc3/platform_data.h
> > > @@ -24,4 +24,6 @@ struct dwc3_platform_data {
> > >  	enum usb_device_speed maximum_speed;
> > >  	enum usb_dr_mode dr_mode;
> > >  	bool tx_fifo_resize;
> > > +
> > > +	u32     quirks;
> > 
> > I prefer to have one-bit fields like we already have for delayed_status,
> > ep0_bounced, ep0_expect_in, and so on. That makes it easier to support
> > the same quirks through devicetree as well.
> > 
> 
> So it should define like below:
> 
> struct dwc3_platform_data {
>         ...
>         unsigned one_quirk:1;
> }
> 
> Then also defined it in dwc3 structure. And when dwc3 probed, put this
> value from glue layer to dwc3, right?

that's correct.

-- 
balbi

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Re: [PATCH v2 06/16] usb: dwc3: add disscramble quirk

[Felipe Balbi]

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On Mon, Oct 20, 2014 at 02:38:28PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 09:45:32AM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 04:53:31PM +0800, Huang Rui wrote:
> > > AMD NL fpga needs to enable disscramble quirk. And this quirk doesn't need on
> > > the true soc.
> > > 
> > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > ---
> > >  drivers/usb/dwc3/core.c          | 8 +++++++-
> > >  drivers/usb/dwc3/dwc3-pci.c      | 5 +++++
> > >  drivers/usb/dwc3/platform_data.h | 4 ++++
> > >  3 files changed, 16 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 50c0eae..819e501 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -422,7 +422,6 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > >  
> > >  	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> > >  	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> > > -	reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > >  
> > >  	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
> > >  	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
> > > @@ -461,6 +460,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > >  		dwc->is_fpga = true;
> > >  	}
> > >  
> > > +	if ((dwc->quirks & DWC3_QUIRK_AMD_NL) && dwc->is_fpga)
> > > +		dwc->quirks |= DWC3_QUIRK_DISSCRAMBLE;
> > > +
> > > +	if (dwc->quirks & DWC3_QUIRK_DISSCRAMBLE)
> > 
> > this should only be set if is_fpga, and this quirk should be a 1-bit
> > flag, so here's what you should do:
> > 
> > 	WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
> > 		"disable_scramble cannot be used on non-FPGA builds\n");
> > 
> > 	if (dwc->disable_scramble && dwc->is_fpga)
> > 		reg |= DWC3_GCTL_DISSCRAMBLE;
> > 	else
> > 		reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > 
> 
> OK, will update it in V3.
> 
> > > +		reg |= DWC3_GCTL_DISSCRAMBLE;
> > > +	else
> > > +		reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > 
> > add a blank line here, to aid readability.
> > 
> 
> OK, will add it.
> 
> > >  	/*
> > >  	 * WORKAROUND: DWC3 revisions <1.90a have a bug
> > >  	 * where the device can fail to connect at SuperSpeed
> > > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > > index 18569a4..a89db6c 100644
> > > --- a/drivers/usb/dwc3/dwc3-pci.c
> > > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > > @@ -146,6 +146,11 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> > >  	res[1].name	= "dwc_usb3";
> > >  	res[1].flags	= IORESOURCE_IRQ;
> > >  
> > > +	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> > > +			PCI_DEVICE_ID_AMD_NL) {
> > > +		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> > > +	}
> > 
> > should be part of another patch and the quirk is
> > "disable_scramble_quirk", not AMD.
> > 
> 
> Got it, you would like to keep this patch just for fpga disscramble
> quirk and do not add any 3rd platform info, right?

right. So far only FPGA-based systems need this :-)

-- 
balbi

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Re: [PATCH v2 08/16] usb: dwc3: add u2exit lfps quirk

[Felipe Balbi]

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On Mon, Oct 20, 2014 at 02:43:31PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 09:50:00AM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 04:53:33PM +0800, Huang Rui wrote:
> > > AMD NL needs to enable u2exit lfps quirk.
> > > 
> > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > ---
> > >  drivers/usb/dwc3/core.c          | 4 ++++
> > >  drivers/usb/dwc3/core.h          | 1 +
> > >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> > >  drivers/usb/dwc3/platform_data.h | 1 +
> > >  4 files changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 25db533..7322d85 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -467,6 +467,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > >  		reg |= DWC3_GCTL_DISSCRAMBLE;
> > >  	else
> > >  		reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > > +
> > > +	if (dwc->quirks & DWC3_QUIRK_U2EXIT_LFPS)
> > 
> > this should be:
> > 
> > 	if (dwc->u2_exit_lfps_quirk)
> > 
> 
> OK, will update it in V3.
> 
> > > +		reg |= DWC3_GCTL_U2EXIT_LFPS;
> > > +
> > >  	/*
> > >  	 * WORKAROUND: DWC3 revisions <1.90a have a bug
> > >  	 * where the device can fail to connect at SuperSpeed
> > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > > index d58479e..3d27f10 100644
> > > --- a/drivers/usb/dwc3/core.h
> > > +++ b/drivers/usb/dwc3/core.h
> > > @@ -166,6 +166,7 @@
> > >  #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
> > >  #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
> > >  #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)
> > > +#define DWC3_GCTL_U2EXIT_LFPS		(1 << 2)
> > >  #define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
> > >  #define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)
> > >  
> > > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > > index bbe946c..cdb9b04 100644
> > > --- a/drivers/usb/dwc3/dwc3-pci.c
> > > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > > @@ -149,7 +149,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> > >  	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> > >  			PCI_DEVICE_ID_AMD_NL) {
> > >  		dwc3_pdata.has_lpm_erratum = true;
> > > -		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> > > +		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
> > > +			| DWC3_QUIRK_U2EXIT_LFPS;
> > >  	}
> > 
> > should be combined and the last patch in the series.
> > 
> 
> You want to make all the AMD quirks enablement info and device id at
> last patch, right?

Correct, that way we avoid bisection points were AMD is "supported" but
not working.

-- 
balbi

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Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Felipe Balbi]

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Hi,

On Mon, Oct 20, 2014 at 04:41:54PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 01:48:19PM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 06:41:04PM +0000, Paul Zimmerman wrote:
> > > > From: Felipe Balbi [mailto:balbi@ti.com]
> > > > Sent: Friday, October 17, 2014 8:00 AM
> > > > 
> > > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> > > > > board.
> > > > >
> > > > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > > > ---
> > > > >  drivers/usb/dwc3/core.c          | 7 ++++++-
> > > > >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> > > > >  drivers/usb/dwc3/platform_data.h | 1 +
> > > > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > index 3ccfe41..4a98696 100644
> > > > > --- a/drivers/usb/dwc3/core.c
> > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > > > >  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > > > >  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > > > >
> > > > > +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > > > 
> > > > should be:
> > > > 
> > > > 	if (!dwc->suspend_usb3_phy_quirk)
> > > > 
> > > > > +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > > > 
> > > > IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> > > > that bit. Am I missing something ? Paul ?
> > > 
> > > It looks to me that Huang's patch is enabling that bit, not disabling
> > > it.
> > 
> > right, but that's what's actually quirky right ? IIRC, Databook asks us
> > to set usb2 and usb3 suspend phy bits and we're just not doing it.
> > 
> > > Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> > > DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> > > series you just posted). According to the databook, both of those
> > > bits should be set to 1 after the core initialization has completed.
> > 
> > there you go. So unless that quirk bit flag is set, we're safe of
> > setting SUSPHY bit for everybody.
> > 
> 
> So I can update to set these two suspend phy bits defaultly in my next
> patch set, is it OK? :)

We need to split this into two patches:

patch 1 adds missing SUSPHY bit for all cores above revision 1.94a at
the end of probe()

patch 2 adds a quirk which AMD needs so that setting USB3_SUSPHY bit is
conditional on that quirk.

-- 
balbi

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Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Felipe Balbi]

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On Mon, Oct 20, 2014 at 05:01:25PM +0800, Huang Rui wrote:
> On Mon, Oct 20, 2014 at 04:41:54PM +0800, Huang Rui wrote:
> > On Fri, Oct 17, 2014 at 01:48:19PM -0500, Felipe Balbi wrote:
> > > Hi,
> > > 
> > > On Fri, Oct 17, 2014 at 06:41:04PM +0000, Paul Zimmerman wrote:
> > > > > From: Felipe Balbi [mailto:balbi@ti.com]
> > > > > Sent: Friday, October 17, 2014 8:00 AM
> > > > > 
> > > > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > > > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> > > > > > board.
> > > > > >
> > > > > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > > > > ---
> > > > > >  drivers/usb/dwc3/core.c          | 7 ++++++-
> > > > > >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> > > > > >  drivers/usb/dwc3/platform_data.h | 1 +
> > > > > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > > index 3ccfe41..4a98696 100644
> > > > > > --- a/drivers/usb/dwc3/core.c
> > > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > > > > >  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > > > > >  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > > > > >
> > > > > > +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > > > > 
> > > > > should be:
> > > > > 
> > > > > 	if (!dwc->suspend_usb3_phy_quirk)
> > > > > 
> > > > > > +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > > > > 
> > > > > IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> > > > > that bit. Am I missing something ? Paul ?
> > > > 
> > > > It looks to me that Huang's patch is enabling that bit, not disabling
> > > > it.
> > > 
> > > right, but that's what's actually quirky right ? IIRC, Databook asks us
> > > to set usb2 and usb3 suspend phy bits and we're just not doing it.
> > > 
> > > > Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> > > > DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> > > > series you just posted). According to the databook, both of those
> > > > bits should be set to 1 after the core initialization has completed.
> > > 
> > > there you go. So unless that quirk bit flag is set, we're safe of
> > > setting SUSPHY bit for everybody.
> > > 
> > 
> 
> I read the databook again, below words (DWC3_GUSB3PIPECTL_SUSPHY) is
> copied from databook:
> 
> For DRD/OTG configurations, it is recommended that this bit is set to‘
> 0’ during coreConsultant configuration. If it is set to ’1’, then the
> application should clear this bit after power-on reset. Application
> needs to set it to ’1’ after the core initialization is completed.
> For all other configurations, this bit can be set to ’1’ during core
> configuration.
> 
> I see it's recommended to set '0' if on DRD/OTG configuration.

0 at the beginning of probe() sequence so core can communicate with its
PHYs, then set it to one at the end of probe().

-- 
balbi

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Re: [PATCH v2 00/16] usb: dwc3: add support for AMD NL SoC

[Felipe Balbi]

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Hi,

On Mon, Oct 20, 2014 at 11:38:23PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 10:10:26AM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 04:53:25PM +0800, Huang Rui wrote:
> > > The series of patches add AMD NL SoC support for DesignWare USB3 OTG
> > > IP with PCI bus glue layer. This controller supported hibernation, LPM
> > > erratum and used the 2.80a IP version and amd own phy. Current
> > > implementation support both simulation and SoC platform. And already
> > > tested with gadget zero and msc tool.  It works well on file storage
> > > gadget.
> > 
> > patches look much, much nicer there are still a few things to fix. A
> > global set of issues which I see:
> > 
> > 1) Let's get confirmation that all those quirks will be needed in
> > production as well, I have a feeling quite a few of them won't be.
> > 
> > 2) All quirks should become 1-bit fields insteads of single-bits on a
> > 32-bit variable.
> > 
> > 3) All quirks should have DeviceTree counterparts. They should all
> > become boolean properties should we can:
> > 
> > 	dwc->tx_deemphasis_quirk = of_property_read_bool(node,
> > 		"snps,tx_deemphasis_quirk");
> > 
> 
> Thanks to summarize them. Will update in V3.

hey, no problem.

> > > These patches are generated on balbi/testing/next
> > > 
> > > Changes from v1 -> v2
> > > - remove dual role function temporarily
> > > - add pci quirk to avoid to bind with xhci driver
> > > - distinguish between simulation board and soc
> > > - break down all the special quirks
> > > 
> > > 
> > > Patch 1:
> > > - add PCI device id into pci bus glue
> > 
> > this guy should be the last in the series, with all AMD quirks being
> > enabled at once. This will avoid bisection points where AMD's platforms
> > don't work.
> > 
> 
> So all the AMD special configuration and device id should be in one
> patch, right?

correct :-)

-- 
balbi

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Re: [PATCH v2 02/16] pci: quirks: add quirk to avoid AMD NL to bind with xhci

[Bjorn Helgaas]

On Fri, Oct 17, 2014 at 04:53:27PM +0800, Huang Rui wrote:
> The dwc3 controller is the PCI-E device in AMD NL platform, but the class code
> of PCI header is 0x0c0330, the same with xHC. That's because it needs to meet
> the windows enviroment. The dwc3 controller acted as only host mode to bind with
> windows xhci driver.
> But on linux, sometimes, it would auto-bind with xhci driver as well (class code
> 0x0c0330) despite it uses Pid/Vid on dwc3 driver.

This changelog really doesn't make any sense unless the reader already
knows everything.  I think you mean something like this:

  The AMD NL (please explain what "NL" is; Google has no clue) SoC contains
  a DesignWare USB3 Dual-Role Device that can be operated either as a USB
  Host or a USB Device.  In the AMD NL platform, this device ([1022:7912])
  has a class code of PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the
  xhci driver will claim it.

  But the dwc3 driver is a more specific driver for this device, and we'd
  prefer to use it instead of xhci.  To prevent xhci from claiming the
  device, change the class code to 0x0c03fe, which the PCI r3.0 spec
  defines as "USB device (not host controller)".  The dwc3 driver can then
  claim it based on its Vendor and Device ID.

Obviously, this means the device won't work at all unless dwc3 is enabled.
Previously, it probably would work as a host controller with the xhci
driver.  I assume this change is what you want.

> Heikki suggested to use the quirk to fix this issue, and the detailed discussion
> is at below thread:
> http://marc.info/?l=linux-usb&m=141197934712824&w=2

This changelog needs to be wrapped so no line is longer than 75 characters.

Please run "git log --oneline --no-merges drivers/pci/quirks.c" and make
your subject line match the rest.  In particular, "PCI" (not "pci"), drop
the "quirks:" part, and capitalize "Add".

> Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  drivers/pci/quirks.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 90acb32..3c911b7 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -378,6 +378,26 @@ static void quirk_ati_exploding_mce(struct pci_dev *dev)
>  }
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
>  
> +/* FIXME should define in <linux/pci_ids.h> */
> +#define PCI_DEVICE_ID_AMD_NL	0x7912

If you KNOW this should be in linux/pci_ids.h (and it looks like it COULD
go there, since you do use the same definition in patch [01/16]), why don't
you just do it?  Why are you wasting our time reviewing trivial stuff like
this?

> +
> +/*
> + * AMD NL SoC 7912 PCI device is dwc3 controller, but the class code of PCI
> + * header is 0x0c0330, the same with xHC. That's because it need to meet the
> + * windows enviroment. The dwc3 controller acted as only host mode to bind with
> + * windows xhci driver. But on linux, sometimes, we auto-bind with xhci driver
> + * as well (class code 0x0c0330) despite we use Pid/Vid on dwc3 driver. So this
> + * quirk used a dummy class code to avoid to bind with xhci driver at booting
> + * phase.
> + */
> +static void quirk_amd_nl_class(struct pci_dev *pdev)
> +{
> +	/* Use a dummy class value instead of PCI header provided */

When you say "dummy class value," that makes it sound like you just chose
a random invalid value.  But this value is actually defined by the spec, so
you should use the description from the spec, namely, "USB device (not host
controller)".

Bjorn

> +	pdev->class = 0x0c03fe;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL,
> +		quirk_amd_nl_class);
> +
>  /*
>   * Let's make the southbridge information explicit instead
>   * of having to worry about people probing the ACPI areas,
> -- 
> 1.9.1
> 

Re: [PATCH v2 07/16] usb: dwc3: add lpm erratum support

[Huang Rui]

On Fri, Oct 17, 2014 at 09:48:59AM -0500, Felipe Balbi wrote:
> On Fri, Oct 17, 2014 at 04:53:32PM +0800, Huang Rui wrote:
> > When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced Configuration
> > of coreConsultant, it supports of xHCI BESL Errata Dated 10/19/2011 is enabled
> > in host mode. In device mode it adds the capability to send NYET response based
> > on the BESL value received in the LPM token.
> > 
> > This patch add an entry that soc platform is able to define the lpm capacity
> > with their own device tree or bus glue layer.
> > 
> > Suggested-by: Felipe Balbi <balbi@ti.com>
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/usb/dwc3/core.c          |  2 ++
> >  drivers/usb/dwc3/core.h          | 24 +++++++++++++++---------
> >  drivers/usb/dwc3/dwc3-pci.c      |  1 +
> >  drivers/usb/dwc3/gadget.c        |  7 +++++++
> >  drivers/usb/dwc3/platform_data.h |  1 +
> >  5 files changed, 26 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 819e501..25db533 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -708,11 +708,13 @@ static int dwc3_probe(struct platform_device *pdev)
> >  
> >  	if (node) {
> >  		dwc->maximum_speed = of_usb_get_maximum_speed(node);
> > +		dwc->has_lpm_erratum = of_property_read_bool(node, "snps,has-lpm-erratum");
> >  
> >  		dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
> >  		dwc->dr_mode = of_usb_get_dr_mode(node);
> >  	} else if (pdata) {
> >  		dwc->maximum_speed = pdata->maximum_speed;
> > +		dwc->has_lpm_erratum = pdata->has_lpm_erratum;
> >  
> >  		dwc->needs_fifo_resize = pdata->tx_fifo_resize;
> >  		dwc->dr_mode = pdata->dr_mode;
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index cfe0d57..d58479e 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -246,16 +246,19 @@
> >  #define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))
> >  
> >  /* These apply for core versions 1.94a and later */
> > -#define DWC3_DCTL_KEEP_CONNECT	(1 << 19)
> > -#define DWC3_DCTL_L1_HIBER_EN	(1 << 18)
> > -#define DWC3_DCTL_CRS		(1 << 17)
> > -#define DWC3_DCTL_CSS		(1 << 16)
> > +#define DWC3_DCTL_LPM_ERRATA_MASK	DWC3_DCTL_LPM_ERRATA(0xf)
> > +#define DWC3_DCTL_LPM_ERRATA(n)		((n) << 20)
> > -#define DWC3_DCTL_INITU2ENA	(1 << 12)
> > -#define DWC3_DCTL_ACCEPTU2ENA	(1 << 11)
> > -#define DWC3_DCTL_INITU1ENA	(1 << 10)
> > -#define DWC3_DCTL_ACCEPTU1ENA	(1 << 9)
> > -#define DWC3_DCTL_TSTCTRL_MASK	(0xf << 1)
> > +#define DWC3_DCTL_KEEP_CONNECT		(1 << 19)
> > +#define DWC3_DCTL_L1_HIBER_EN		(1 << 18)
> > +#define DWC3_DCTL_CRS			(1 << 17)
> > +#define DWC3_DCTL_CSS			(1 << 16)
> > +
> > +#define DWC3_DCTL_INITU2ENA		(1 << 12)
> > +#define DWC3_DCTL_ACCEPTU2ENA		(1 << 11)
> > +#define DWC3_DCTL_INITU1ENA		(1 << 10)
> > +#define DWC3_DCTL_ACCEPTU1ENA		(1 << 9)
> > +#define DWC3_DCTL_TSTCTRL_MASK		(0xf << 1)
> >  
> >  #define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
> >  #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
> > @@ -665,6 +668,8 @@ struct dwc3_scratchpad_array {
> >   * @ep0_bounced: true when we used bounce buffer
> >   * @ep0_expect_in: true when we expect a DATA IN transfer
> >   * @has_hibernation: true when dwc3 was configured with Hibernation
> > + * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
> > + *			there's now way for software to detect this in runtime.
> >   * @is_selfpowered: true when we are selfpowered
> >   * @is_fpga: true when we are using the FPGA board
> >   * @needs_fifo_resize: not all users might want fifo resizing, flag it
> > @@ -771,6 +776,7 @@ struct dwc3 {
> >  	unsigned		ep0_bounced:1;
> >  	unsigned		ep0_expect_in:1;
> >  	unsigned		has_hibernation:1;
> > +	unsigned		has_lpm_erratum:1;
> >  	unsigned		is_selfpowered:1;
> >  	unsigned		is_fpga:1;
> >  	unsigned		needs_fifo_resize:1;
> > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > index a89db6c..bbe946c 100644
> > --- a/drivers/usb/dwc3/dwc3-pci.c
> > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > @@ -148,6 +148,7 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> >  
> >  	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> >  			PCI_DEVICE_ID_AMD_NL) {
> > +		dwc3_pdata.has_lpm_erratum = true;
> >  		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> >  	}
> >  
> 
> let's combine all AMD patches as the last patch in the series so we add
> AMD support with all quirks in one place.
> 
> > diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
> > index 1f2a719..33bfc70 100644
> > --- a/drivers/usb/dwc3/gadget.c
> > +++ b/drivers/usb/dwc3/gadget.c
> > @@ -1581,6 +1581,13 @@ static int dwc3_gadget_start(struct usb_gadget *g,
> >  	}
> >  	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
> >  
> > +	if (dwc->has_lpm_erratum) {
> > +		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
> > +		/* REVISIT should this be configurable ? */
> > +		reg |= DWC3_DCTL_LPM_ERRATA(0xf);
> 
> as Paul mentioned, this should definitely be configurable. So we need to
> discuss how to make that configurable too.
> 

Can I define a 4-bits variable (lpm_nyet_thres) to let platform vendor able to configure
the besl value at DT or glue layer?

struct dwc3_platform_data {
        ...
        unsigned has_lpm_erratum:1;
        unsigned lpm_nyet_thres:4;
}

Then put the value at probe like:

dwc->has_lpm_erratum = of_property_read_u8(node, "snps,lpm-nyet-thres");

I don't find a 4-bit "Find from a property" interface, so can I use
of_property_read_u8 instead for ARM platforms?

Then do:
if (dwc->has_lpm_erratum)
        reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_thres);

Thanks,
Rui

Re: [PATCH v2 07/16] usb: dwc3: add lpm erratum support

[Felipe Balbi]

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Hi,

On Sat, Oct 25, 2014 at 01:01:28AM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 09:48:59AM -0500, Felipe Balbi wrote:
> > On Fri, Oct 17, 2014 at 04:53:32PM +0800, Huang Rui wrote:
> > > When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced Configuration
> > > of coreConsultant, it supports of xHCI BESL Errata Dated 10/19/2011 is enabled
> > > in host mode. In device mode it adds the capability to send NYET response based
> > > on the BESL value received in the LPM token.
> > > 
> > > This patch add an entry that soc platform is able to define the lpm capacity
> > > with their own device tree or bus glue layer.
> > > 
> > > Suggested-by: Felipe Balbi <balbi@ti.com>
> > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > ---
> > >  drivers/usb/dwc3/core.c          |  2 ++
> > >  drivers/usb/dwc3/core.h          | 24 +++++++++++++++---------
> > >  drivers/usb/dwc3/dwc3-pci.c      |  1 +
> > >  drivers/usb/dwc3/gadget.c        |  7 +++++++
> > >  drivers/usb/dwc3/platform_data.h |  1 +
> > >  5 files changed, 26 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 819e501..25db533 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -708,11 +708,13 @@ static int dwc3_probe(struct platform_device *pdev)
> > >  
> > >  	if (node) {
> > >  		dwc->maximum_speed = of_usb_get_maximum_speed(node);
> > > +		dwc->has_lpm_erratum = of_property_read_bool(node, "snps,has-lpm-erratum");
> > >  
> > >  		dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
> > >  		dwc->dr_mode = of_usb_get_dr_mode(node);
> > >  	} else if (pdata) {
> > >  		dwc->maximum_speed = pdata->maximum_speed;
> > > +		dwc->has_lpm_erratum = pdata->has_lpm_erratum;
> > >  
> > >  		dwc->needs_fifo_resize = pdata->tx_fifo_resize;
> > >  		dwc->dr_mode = pdata->dr_mode;
> > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > > index cfe0d57..d58479e 100644
> > > --- a/drivers/usb/dwc3/core.h
> > > +++ b/drivers/usb/dwc3/core.h
> > > @@ -246,16 +246,19 @@
> > >  #define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))
> > >  
> > >  /* These apply for core versions 1.94a and later */
> > > -#define DWC3_DCTL_KEEP_CONNECT	(1 << 19)
> > > -#define DWC3_DCTL_L1_HIBER_EN	(1 << 18)
> > > -#define DWC3_DCTL_CRS		(1 << 17)
> > > -#define DWC3_DCTL_CSS		(1 << 16)
> > > +#define DWC3_DCTL_LPM_ERRATA_MASK	DWC3_DCTL_LPM_ERRATA(0xf)
> > > +#define DWC3_DCTL_LPM_ERRATA(n)		((n) << 20)
> > > -#define DWC3_DCTL_INITU2ENA	(1 << 12)
> > > -#define DWC3_DCTL_ACCEPTU2ENA	(1 << 11)
> > > -#define DWC3_DCTL_INITU1ENA	(1 << 10)
> > > -#define DWC3_DCTL_ACCEPTU1ENA	(1 << 9)
> > > -#define DWC3_DCTL_TSTCTRL_MASK	(0xf << 1)
> > > +#define DWC3_DCTL_KEEP_CONNECT		(1 << 19)
> > > +#define DWC3_DCTL_L1_HIBER_EN		(1 << 18)
> > > +#define DWC3_DCTL_CRS			(1 << 17)
> > > +#define DWC3_DCTL_CSS			(1 << 16)
> > > +
> > > +#define DWC3_DCTL_INITU2ENA		(1 << 12)
> > > +#define DWC3_DCTL_ACCEPTU2ENA		(1 << 11)
> > > +#define DWC3_DCTL_INITU1ENA		(1 << 10)
> > > +#define DWC3_DCTL_ACCEPTU1ENA		(1 << 9)
> > > +#define DWC3_DCTL_TSTCTRL_MASK		(0xf << 1)
> > >  
> > >  #define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
> > >  #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
> > > @@ -665,6 +668,8 @@ struct dwc3_scratchpad_array {
> > >   * @ep0_bounced: true when we used bounce buffer
> > >   * @ep0_expect_in: true when we expect a DATA IN transfer
> > >   * @has_hibernation: true when dwc3 was configured with Hibernation
> > > + * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
> > > + *			there's now way for software to detect this in runtime.
> > >   * @is_selfpowered: true when we are selfpowered
> > >   * @is_fpga: true when we are using the FPGA board
> > >   * @needs_fifo_resize: not all users might want fifo resizing, flag it
> > > @@ -771,6 +776,7 @@ struct dwc3 {
> > >  	unsigned		ep0_bounced:1;
> > >  	unsigned		ep0_expect_in:1;
> > >  	unsigned		has_hibernation:1;
> > > +	unsigned		has_lpm_erratum:1;
> > >  	unsigned		is_selfpowered:1;
> > >  	unsigned		is_fpga:1;
> > >  	unsigned		needs_fifo_resize:1;
> > > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > > index a89db6c..bbe946c 100644
> > > --- a/drivers/usb/dwc3/dwc3-pci.c
> > > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > > @@ -148,6 +148,7 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> > >  
> > >  	if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> > >  			PCI_DEVICE_ID_AMD_NL) {
> > > +		dwc3_pdata.has_lpm_erratum = true;
> > >  		dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> > >  	}
> > >  
> > 
> > let's combine all AMD patches as the last patch in the series so we add
> > AMD support with all quirks in one place.
> > 
> > > diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
> > > index 1f2a719..33bfc70 100644
> > > --- a/drivers/usb/dwc3/gadget.c
> > > +++ b/drivers/usb/dwc3/gadget.c
> > > @@ -1581,6 +1581,13 @@ static int dwc3_gadget_start(struct usb_gadget *g,
> > >  	}
> > >  	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
> > >  
> > > +	if (dwc->has_lpm_erratum) {
> > > +		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
> > > +		/* REVISIT should this be configurable ? */
> > > +		reg |= DWC3_DCTL_LPM_ERRATA(0xf);
> > 
> > as Paul mentioned, this should definitely be configurable. So we need to
> > discuss how to make that configurable too.
> > 
> 
> Can I define a 4-bits variable (lpm_nyet_thres) to let platform vendor able to configure
> the besl value at DT or glue layer?
> 
> struct dwc3_platform_data {
>         ...
>         unsigned has_lpm_erratum:1;
>         unsigned lpm_nyet_thres:4;

this threshold can be a u8, no problem :-) (also, please spell out
threshold completely :-)

> Then put the value at probe like:
> 
> dwc->has_lpm_erratum = of_property_read_u8(node, "snps,lpm-nyet-thres");

yup, that's fine :-)

> I don't find a 4-bit "Find from a property" interface, so can I use
> of_property_read_u8 instead for ARM platforms?
> 
> Then do:
> if (dwc->has_lpm_erratum)
>         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_thres);

perfect :-) But then default to highest possible threshold, perhaps ?

lpm_nyet_threshold = 0xff;

if (pdata->lpm_nyet_threshold)
	lpm_nyet_threshold = pdata->lpm_nyet_threshold;

and likewise for DT.

-- 
balbi

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Re: [PATCH v2 02/16] pci: quirks: add quirk to avoid AMD NL to bind with xhci

[Huang Rui]

On Fri, Oct 24, 2014 at 10:35:29AM -0600, Bjorn Helgaas wrote:
> On Fri, Oct 17, 2014 at 04:53:27PM +0800, Huang Rui wrote:
> > The dwc3 controller is the PCI-E device in AMD NL platform, but the class code
> > of PCI header is 0x0c0330, the same with xHC. That's because it needs to meet
> > the windows enviroment. The dwc3 controller acted as only host mode to bind with
> > windows xhci driver.
> > But on linux, sometimes, it would auto-bind with xhci driver as well (class code
> > 0x0c0330) despite it uses Pid/Vid on dwc3 driver.
> 
> This changelog really doesn't make any sense unless the reader already
> knows everything.  I think you mean something like this:
> 
>   The AMD NL (please explain what "NL" is; Google has no clue) SoC contains
>   a DesignWare USB3 Dual-Role Device that can be operated either as a USB
>   Host or a USB Device.  In the AMD NL platform, this device ([1022:7912])
>   has a class code of PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the
>   xhci driver will claim it.
> 
>   But the dwc3 driver is a more specific driver for this device, and we'd
>   prefer to use it instead of xhci.  To prevent xhci from claiming the
>   device, change the class code to 0x0c03fe, which the PCI r3.0 spec
>   defines as "USB device (not host controller)".  The dwc3 driver can then
>   claim it based on its Vendor and Device ID.
> 
> Obviously, this means the device won't work at all unless dwc3 is enabled.
> Previously, it probably would work as a host controller with the xhci
> driver.  I assume this change is what you want.
> 

OK, I will update to this changelog in V3.

> > Heikki suggested to use the quirk to fix this issue, and the detailed discussion
> > is at below thread:
> > http://marc.info/?l=linux-usb&m=141197934712824&w=2
> 
> This changelog needs to be wrapped so no line is longer than 75 characters.
> 
> Please run "git log --oneline --no-merges drivers/pci/quirks.c" and make
> your subject line match the rest.  In particular, "PCI" (not "pci"), drop
> the "quirks:" part, and capitalize "Add".
> 

I got it, will update subject.

> > Suggested-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/pci/quirks.c | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> > 
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 90acb32..3c911b7 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -378,6 +378,26 @@ static void quirk_ati_exploding_mce(struct pci_dev *dev)
> >  }
> >  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
> >  
> > +/* FIXME should define in <linux/pci_ids.h> */
> > +#define PCI_DEVICE_ID_AMD_NL	0x7912
> 
> If you KNOW this should be in linux/pci_ids.h (and it looks like it COULD
> go there, since you do use the same definition in patch [01/16]), why don't
> you just do it?  Why are you wasting our time reviewing trivial stuff like
> this?
> 

Apology, I was told that it could not add device id into pci_ids.h
from my buddy with below thread discussion last year, but I don't
confirm at current. I check the git log at pci_ids.h, it looks like
it's able to add device id marco again, is that right?

http://marc.info/?l=linux-pci&m=137028614924258&w=2

If I misunderstand your meaning, please correct me.

> > +
> > +/*
> > + * AMD NL SoC 7912 PCI device is dwc3 controller, but the class code of PCI
> > + * header is 0x0c0330, the same with xHC. That's because it need to meet the
> > + * windows enviroment. The dwc3 controller acted as only host mode to bind with
> > + * windows xhci driver. But on linux, sometimes, we auto-bind with xhci driver
> > + * as well (class code 0x0c0330) despite we use Pid/Vid on dwc3 driver. So this
> > + * quirk used a dummy class code to avoid to bind with xhci driver at booting
> > + * phase.
> > + */
> > +static void quirk_amd_nl_class(struct pci_dev *pdev)
> > +{
> > +	/* Use a dummy class value instead of PCI header provided */
> 
> When you say "dummy class value," that makes it sound like you just chose
> a random invalid value.  But this value is actually defined by the spec, so
> you should use the description from the spec, namely, "USB device (not host
> controller)".
> 

Yes, you're right. Will change this description.

Thanks,
Rui

Re: [PATCH v2 02/16] pci: quirks: add quirk to avoid AMD NL to bind with xhci

[Bjorn Helgaas]

On Sun, Oct 26, 2014 at 8:55 PM, Huang Rui <ray.huang@amd.com> wrote:
> On Fri, Oct 24, 2014 at 10:35:29AM -0600, Bjorn Helgaas wrote:
>> On Fri, Oct 17, 2014 at 04:53:27PM +0800, Huang Rui wrote:

>> > +/* FIXME should define in <linux/pci_ids.h> */
>> > +#define PCI_DEVICE_ID_AMD_NL       0x7912
>>
>> If you KNOW this should be in linux/pci_ids.h (and it looks like it COULD
>> go there, since you do use the same definition in patch [01/16]), why don't
>> you just do it?  Why are you wasting our time reviewing trivial stuff like
>> this?
>>
>
> Apology, I was told that it could not add device id into pci_ids.h
> from my buddy with below thread discussion last year, but I don't
> confirm at current. I check the git log at pci_ids.h, it looks like
> it's able to add device id marco again, is that right?
>
> http://marc.info/?l=linux-pci&m=137028614924258&w=2
>
> If I misunderstand your meaning, please correct me.

Just read the text at the beginning of pci_ids.h.

If you have to use the same ID in two different files, you should add
it to pci_ids.h.