* [PATCH v2 0/6] clk: samsung: Fix bug of Exynos5433 clocks @ 2015-04-03 0:29 Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 1/6] clk: samsung: Use CONFIG_ARCH_EXYNOS instead of CONFIG_ARCH_EXYNOS5433 Chanwoo Choi ` (5 more replies) 0 siblings, 6 replies; 7+ messages in thread From: Chanwoo Choi @ 2015-04-03 0:29 UTC (permalink / raw) To: s.nawrocki, tomasz.figa, mturquette Cc: kgene, inki.dae, chanho61.park, cw00.choi, jonghwa3.lee, linux-samsung-soc, linux-kernel, devicetree This patchset remove the CONFIG_ARCH_EXYNOS5433 insteadf use the CONFIG_ARCH_EXYNOS because Arnd Bergmann gave me a comment[1] that don't add specific CONFIG_ARCH_EXYNOS5433 for ARM-64bit SoC. And this patchset fix following bugs: - Fix wrong offset of PCLK_MSCL_SECURE_SMMU_JPEG in CMU_MSCL. - Fix wrong PMS value for 700MHz. - Fix wrong parent clock of 'sclk_apollo' clock. - Fix wrong register for ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT - Add CLK_SET_RATE_PARENT flags to propagate parent clock when changing the clock for DVFS feature. [1] https://lkml.org/lkml/2015/2/26/102 Changelog: Change from v1: (https://lkml.org/lkml/2015/3/17/855) - Add new patches (patch3 ~ patch6) Chanwoo Choi (4): clk: samsung: Use CONFIG_ARCH_EXYNOS instead of CONFIG_ARCH_EXYNOS5433 clk: samsung: exynos5433: Fix wrong parent clock of sclk_apollo clock clk: samsung: exynos5433: Fix wrong PMS value of exynos5433_pll_rates clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE core Jonghwa Lee (2): clk: samsung: exynos5433: Fix wrong offset of PCLK_MSCL_SECURE_SMMU_JPEG clk: samsung: exynos5433: Fix CLK_PCLK_MONOTONIC_CNT's register correctly drivers/clk/samsung/Makefile | 2 +- drivers/clk/samsung/clk-exynos5433.c | 34 ++++++++++++++++------------------ 2 files changed, 17 insertions(+), 19 deletions(-) -- 1.8.5.5 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/6] clk: samsung: Use CONFIG_ARCH_EXYNOS instead of CONFIG_ARCH_EXYNOS5433 2015-04-03 0:29 [PATCH v2 0/6] clk: samsung: Fix bug of Exynos5433 clocks Chanwoo Choi @ 2015-04-03 0:29 ` Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 2/6] clk: samsung: exynos5433: Fix wrong offset of PCLK_MSCL_SECURE_SMMU_JPEG Chanwoo Choi ` (4 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Chanwoo Choi @ 2015-04-03 0:29 UTC (permalink / raw) To: s.nawrocki, tomasz.figa, mturquette Cc: kgene, inki.dae, chanho61.park, cw00.choi, jonghwa3.lee, linux-samsung-soc, linux-kernel, devicetree, Arnd Bergmann This patch removes the CONFIG_ARCH_EXYNOS5433 and then use only the CONFIG_ARCH_EXYNOS for ARM-64bit Exynos5433 SoC. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- drivers/clk/samsung/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 17e9af7..a17683b 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -10,7 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o -obj-$(CONFIG_ARCH_EXYNOS5433) += clk-exynos5433.o +obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/6] clk: samsung: exynos5433: Fix wrong offset of PCLK_MSCL_SECURE_SMMU_JPEG 2015-04-03 0:29 [PATCH v2 0/6] clk: samsung: Fix bug of Exynos5433 clocks Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 1/6] clk: samsung: Use CONFIG_ARCH_EXYNOS instead of CONFIG_ARCH_EXYNOS5433 Chanwoo Choi @ 2015-04-03 0:29 ` Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 3/6] clk: samsung: exynos5433: Fix CLK_PCLK_MONOTONIC_CNT's register correctly Chanwoo Choi ` (3 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Chanwoo Choi @ 2015-04-03 0:29 UTC (permalink / raw) To: s.nawrocki, tomasz.figa, mturquette Cc: kgene, inki.dae, chanho61.park, cw00.choi, jonghwa3.lee, linux-samsung-soc, linux-kernel, devicetree From: Jonghwa Lee <jonghwa3.lee@samsung.com> This patch fixes the wrong offoset of PCLK_MSCL_SECURE_SMMU_JPEG in CMU_MSCL domain. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- drivers/clk/samsung/clk-exynos5433.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 387e3e3..543f9c7 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -3927,7 +3927,7 @@ CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", #define ENABLE_PCLK_MSCL 0x0900 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 -#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x000c +#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c #define ENABLE_SCLK_MSCL 0x0a00 #define ENABLE_IP_MSCL0 0x0b00 #define ENABLE_IP_MSCL1 0x0b04 -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 3/6] clk: samsung: exynos5433: Fix CLK_PCLK_MONOTONIC_CNT's register correctly 2015-04-03 0:29 [PATCH v2 0/6] clk: samsung: Fix bug of Exynos5433 clocks Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 1/6] clk: samsung: Use CONFIG_ARCH_EXYNOS instead of CONFIG_ARCH_EXYNOS5433 Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 2/6] clk: samsung: exynos5433: Fix wrong offset of PCLK_MSCL_SECURE_SMMU_JPEG Chanwoo Choi @ 2015-04-03 0:29 ` Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 4/6] clk: samsung: exynos5433: Fix wrong parent clock of sclk_apollo clock Chanwoo Choi ` (2 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Chanwoo Choi @ 2015-04-03 0:29 UTC (permalink / raw) To: s.nawrocki, tomasz.figa, mturquette Cc: kgene, inki.dae, chanho61.park, cw00.choi, jonghwa3.lee, linux-samsung-soc, linux-kernel, devicetree From: Jonghwa Lee <jonghwa3.lee@samsung.com> CLK_PCLK_MONOTONIC_CNT's register is now assigned with wrong one. Its correct register is ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- drivers/clk/samsung/clk-exynos5433.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 543f9c7..b1a546e 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -1490,7 +1490,7 @@ static struct samsung_gate_clock mif_gate_clks[] __initdata = { /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", - ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), + ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0), /* ENABLE_PCLK_MIF_SECURE_RTC */ GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 4/6] clk: samsung: exynos5433: Fix wrong parent clock of sclk_apollo clock 2015-04-03 0:29 [PATCH v2 0/6] clk: samsung: Fix bug of Exynos5433 clocks Chanwoo Choi ` (2 preceding siblings ...) 2015-04-03 0:29 ` [PATCH v2 3/6] clk: samsung: exynos5433: Fix CLK_PCLK_MONOTONIC_CNT's register correctly Chanwoo Choi @ 2015-04-03 0:29 ` Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 5/6] clk: samsung: exynos5433: Fix wrong PMS value of exynos5433_pll_rates Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 6/6] clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE core Chanwoo Choi 5 siblings, 0 replies; 7+ messages in thread From: Chanwoo Choi @ 2015-04-03 0:29 UTC (permalink / raw) To: s.nawrocki, tomasz.figa, mturquette Cc: kgene, inki.dae, chanho61.park, cw00.choi, jonghwa3.lee, linux-samsung-soc, linux-kernel, devicetree This patch fixes the wrong parent clock of sclk_apollo clock from 'div_apollo_pll' to 'div_apollo2'. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- drivers/clk/samsung/clk-exynos5433.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index b1a546e..ec29426 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -3665,7 +3665,7 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = { ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), - GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll", + GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2", ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0), }; -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 5/6] clk: samsung: exynos5433: Fix wrong PMS value of exynos5433_pll_rates 2015-04-03 0:29 [PATCH v2 0/6] clk: samsung: Fix bug of Exynos5433 clocks Chanwoo Choi ` (3 preceding siblings ...) 2015-04-03 0:29 ` [PATCH v2 4/6] clk: samsung: exynos5433: Fix wrong parent clock of sclk_apollo clock Chanwoo Choi @ 2015-04-03 0:29 ` Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 6/6] clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE core Chanwoo Choi 5 siblings, 0 replies; 7+ messages in thread From: Chanwoo Choi @ 2015-04-03 0:29 UTC (permalink / raw) To: s.nawrocki, tomasz.figa, mturquette Cc: kgene, inki.dae, chanho61.park, cw00.choi, jonghwa3.lee, linux-samsung-soc, linux-kernel, devicetree This patch fixes the wrong PMS value of exynos5433_pll_rates table for {ATLAS|APOLLO|MEM0|MEM1|BUS|MFC|MPHY|G3D|DISP|ISP|_PLL. - before : rate=720000000 (mdiv=360, pdiv=6, sdiv=1) - after : rate=700000000 (mdiv=175, pdiv=3, sdiv=1) Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- drivers/clk/samsung/clk-exynos5433.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index ec29426..44f3dd5 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -748,7 +748,7 @@ static struct samsung_pll_rate_table exynos5443_pll_rates[] = { PLL_35XX_RATE(825000000U, 275, 4, 1), PLL_35XX_RATE(800000000U, 400, 6, 1), PLL_35XX_RATE(733000000U, 733, 12, 1), - PLL_35XX_RATE(700000000U, 360, 6, 1), + PLL_35XX_RATE(700000000U, 175, 3, 1), PLL_35XX_RATE(667000000U, 222, 4, 1), PLL_35XX_RATE(633000000U, 211, 4, 1), PLL_35XX_RATE(600000000U, 500, 5, 2), -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 6/6] clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE core 2015-04-03 0:29 [PATCH v2 0/6] clk: samsung: Fix bug of Exynos5433 clocks Chanwoo Choi ` (4 preceding siblings ...) 2015-04-03 0:29 ` [PATCH v2 5/6] clk: samsung: exynos5433: Fix wrong PMS value of exynos5433_pll_rates Chanwoo Choi @ 2015-04-03 0:29 ` Chanwoo Choi 5 siblings, 0 replies; 7+ messages in thread From: Chanwoo Choi @ 2015-04-03 0:29 UTC (permalink / raw) To: s.nawrocki, tomasz.figa, mturquette Cc: kgene, inki.dae, chanho61.park, cw00.choi, jonghwa3.lee, linux-samsung-soc, linux-kernel, devicetree This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57} core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver. - 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM. - 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- drivers/clk/samsung/clk-exynos5433.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 44f3dd5..0e6dce8 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -3582,7 +3582,7 @@ static struct samsung_pll_clock apollo_pll_clks[] __initdata = { static struct samsung_mux_clock apollo_mux_clks[] __initdata = { /* MUX_SEL_APOLLO0 */ MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, - MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY), + MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0), /* MUX_SEL_APOLLO1 */ MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", @@ -3590,7 +3590,7 @@ static struct samsung_mux_clock apollo_mux_clks[] __initdata = { /* MUX_SEL_APOLLO2 */ MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, - 0, 1, 0, CLK_MUX_READ_ONLY), + 0, 1, CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock apollo_div_clks[] __initdata = { @@ -3611,11 +3611,9 @@ static struct samsung_div_clock apollo_div_clks[] __initdata = { DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", - DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0), DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", - DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0), /* DIV_APOLLO1 */ DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", @@ -3666,7 +3664,8 @@ static struct samsung_gate_clock apollo_gate_clks[] __initdata = { GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2", - ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0), + ENABLE_SCLK_APOLLO, 0, + CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; static struct samsung_cmu_info apollo_cmu_info __initdata = { @@ -3775,7 +3774,7 @@ static struct samsung_pll_clock atlas_pll_clks[] __initdata = { static struct samsung_mux_clock atlas_mux_clks[] __initdata = { /* MUX_SEL_ATLAS0 */ MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, - MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY), + MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0), /* MUX_SEL_ATLAS1 */ MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", @@ -3783,7 +3782,7 @@ static struct samsung_mux_clock atlas_mux_clks[] __initdata = { /* MUX_SEL_ATLAS2 */ MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, - 0, 1, 0, CLK_MUX_READ_ONLY), + 0, 1, CLK_SET_RATE_PARENT, 0), }; static struct samsung_div_clock atlas_div_clks[] __initdata = { @@ -3804,11 +3803,9 @@ static struct samsung_div_clock atlas_div_clks[] __initdata = { DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY), DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", - DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0), DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", - DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE, - CLK_DIVIDER_READ_ONLY), + DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0), /* DIV_ATLAS1 */ DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", @@ -3885,7 +3882,8 @@ static struct samsung_gate_clock atlas_gate_clks[] __initdata = { GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2", - ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), + ENABLE_SCLK_ATLAS, 0, + CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), }; static struct samsung_cmu_info atlas_cmu_info __initdata = { -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-04-03 0:30 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-04-03 0:29 [PATCH v2 0/6] clk: samsung: Fix bug of Exynos5433 clocks Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 1/6] clk: samsung: Use CONFIG_ARCH_EXYNOS instead of CONFIG_ARCH_EXYNOS5433 Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 2/6] clk: samsung: exynos5433: Fix wrong offset of PCLK_MSCL_SECURE_SMMU_JPEG Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 3/6] clk: samsung: exynos5433: Fix CLK_PCLK_MONOTONIC_CNT's register correctly Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 4/6] clk: samsung: exynos5433: Fix wrong parent clock of sclk_apollo clock Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 5/6] clk: samsung: exynos5433: Fix wrong PMS value of exynos5433_pll_rates Chanwoo Choi 2015-04-03 0:29 ` [PATCH v2 6/6] clk: samsung: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE core Chanwoo Choi
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