[PATCH 0/3] mailbox: rockchip: Add mailbox driver for Rockchip platform

[PATCH 0/3] mailbox: rockchip: Add mailbox driver for Rockchip platform

[Caesar Wang]

Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processorm.

This driver is found on RK3368 SoCs.

The Mailbox module is a simple APB peripheral that allows both
the Cortex-A53 MCU system to communicate by writing operation to
generate interrupt.
The registers are accessible by both CPU via APB interface.

Tested on RK3368 SDK board.



Caesar Wang (3):
  dt-bindings: Add document of Rockchip mailbox
  mailbox: rockchip: Add Rockchip mailbox driver
  ARM64: dts: rk3368: Add mailbox device nodes

 .../bindings/mailbox/rockchip-mailbox.txt          |  33 +++
 arch/arm64/boot/dts/rockchip/rk3368.dtsi           |  13 +
 drivers/mailbox/Kconfig                            |   9 +
 drivers/mailbox/Makefile                           |   2 +
 drivers/mailbox/rockchip-mailbox.c                 | 317 +++++++++++++++++++++
 5 files changed, 374 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
 create mode 100644 drivers/mailbox/rockchip-mailbox.c

-- 
1.9.1

[PATCH 1/3] dt-bindings: Add document of Rockchip mailbox

[Caesar Wang]

This add the necessary binding documentation for mailbox
found on RK3368 SoC.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 .../bindings/mailbox/rockchip-mailbox.txt          | 33 ++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt

diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
new file mode 100644
index 0000000..b9b4768
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
@@ -0,0 +1,33 @@
+Rockchip mailbox
+
+The Rockchip mailbox is used by the Rockchip CPU cores to communicate
+requests to MCU processor.
+
+Refer to ./mailbox.txt for generic information about mailbox device-tree
+bindings.
+
+Required properties:
+
+ - compatible: should be one of the following.
+   - "rockchip,rk3368-mbox" for rk3368
+ - reg: physical base address of the controller and length of memory mapped
+	region.
+	physical base address of the share buffer and length of memory mapped
+	region.
+ - interrupts: The interrupt number to the cpu. The interrupt specifier format
+	depends on the interrupt controller.
+
+Example:
+--------
+
+/* RK3368 */
+mbox: mbox@ff6b0000 {
+	compatible = "rockchip,rk3368-mailbox";
+	reg = <0x0 0xff6b0000 0x0 0x1000>,
+	      <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
+	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+	#mbox-cells = <1>;
+};
-- 
1.9.1

[PATCH 2/3] mailbox: rockchip: Add Rockchip mailbox driver

[Caesar Wang]

This driver is found on RK3368 SoCs.

The Mailbox module is a simple APB peripheral that allows both
the Cortex-A53 MCU system to communicate by writing operation to
generate interrupt.
The registers are accessible by both CPU via APB interface.

The Mailbox has the following main features:

@ Support dual-core system: Cortex-A53 and MCU.
@ Support APB interface.
@ Support four mailbox elements, each element includes one data word, one
  command word register and one flag bit that can represent one interrupt.
@ Four interrupts to Cortex-A53.
@ Four interrupts to MCU.
@ Provide 32 lock registers for software to use to indicate whether mailbox
  is occupied.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/mailbox/Kconfig            |   9 ++
 drivers/mailbox/Makefile           |   2 +
 drivers/mailbox/rockchip-mailbox.c | 317 +++++++++++++++++++++++++++++++++++++
 3 files changed, 328 insertions(+)
 create mode 100644 drivers/mailbox/rockchip-mailbox.c

diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index bbec500..a548d700 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -43,6 +43,15 @@ config OMAP_MBOX_KFIFO_SIZE
 	  This can also be changed at runtime (via the mbox_kfifo_size
 	  module parameter).
 
+config ROCKCHIP_MBOX
+	bool "Rockchip Soc Intergrated Mailbox Support"
+	depends on ARCH_ROCKCHIP
+	help
+	  This driver provides support for inter-processor communication
+	  between CPU cores and MCU processor on Some Rockchip SOCs.
+	  Please check it that the Soc you use have Mailbox hardware.
+	  Say Y here if you want to use the Rockchip Mailbox support.
+
 config PCC
 	bool "Platform Communication Channel Driver"
 	depends on ACPI
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 8e6d822..730cb5d 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -8,6 +8,8 @@ obj-$(CONFIG_PL320_MBOX)	+= pl320-ipc.o
 
 obj-$(CONFIG_OMAP2PLUS_MBOX)	+= omap-mailbox.o
 
+obj-$(CONFIG_ROCKCHIP_MBOX)	+= rockchip-mailbox.o
+
 obj-$(CONFIG_PCC)		+= pcc.o
 
 obj-$(CONFIG_ALTERA_MBOX)	+= mailbox-altera.o
diff --git a/drivers/mailbox/rockchip-mailbox.c b/drivers/mailbox/rockchip-mailbox.c
new file mode 100644
index 0000000..715ab96
--- /dev/null
+++ b/drivers/mailbox/rockchip-mailbox.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Authors:	Addy Ke <addy.ke@rock-chips.com>
+ *		Caesar Wang <wxt@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#define MAILBOX_A2B_INTEN		0x00
+#define MAILBOX_A2B_STATUS		0x04
+#define MAILBOX_A2B_CMD(x)		(0x08 + (x) * 8)
+#define MAILBOX_A2B_DAT(x)		(0x0c + (x) * 8)
+
+#define MAILBOX_B2A_INTEN		0x28
+#define MAILBOX_B2A_STATUS		0x2C
+#define MAILBOX_B2A_CMD(x)		(0x30 + (x) * 8)
+#define MAILBOX_B2A_DAT(x)		(0x34 + (x) * 8)
+
+#define MAILBOX_ATOMIC_LOCK(x)		(0x100 + (x) * 8)
+
+/* A2B: 0 - 2k */
+#define A2B_BUF(size, idx)		((idx) * (size))
+
+/* B2A: 2k - 4k */
+#define B2A_BUF(size, idx)		(((idx) + 4) * (size))
+
+struct rockchip_mbox_msg {
+	u32 cmd;
+	int tx_size;
+	void *tx_buf;
+	int rx_size;
+	void *rx_buf;
+	void *cl_data;
+};
+
+struct rockchip_mbox_data {
+	int num_chans;
+};
+
+struct rockchip_mbox_chan {
+	int idx;
+	int irq;
+	struct rockchip_mbox_msg *msg;
+	struct rockchip_mbox *mb;
+};
+
+struct rockchip_mbox {
+	struct mbox_controller mbox;
+	struct clk *pclk;
+	void __iomem *mbox_base;
+
+	/* The base address of share memory to transfer data */
+	void __iomem *buf_base;
+
+	/* The maximum size of buf for each channel */
+	u32 buf_size;
+
+	struct rockchip_mbox_chan *chans;
+};
+
+static inline int chan_to_idx(struct rockchip_mbox *mb,
+			      struct mbox_chan *chan)
+{
+	return (chan - mb->mbox.chans);
+}
+
+static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
+	struct rockchip_mbox_msg *msg = data;
+	int idx = chan_to_idx(mb, chan);
+
+	if (!msg)
+		return -EINVAL;
+
+	if ((msg->tx_size > mb->buf_size) ||
+	    (msg->rx_size > mb->buf_size)) {
+		dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
+			mb->buf_size);
+		return -EINVAL;
+	}
+
+	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
+		idx, msg->cmd);
+
+	mb->chans[idx].msg = msg;
+
+	if (msg->tx_buf)
+		memcpy(mb->buf_base + A2B_BUF(mb->buf_size, idx),
+		       msg->tx_buf, msg->tx_size);
+
+	writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(idx));
+	writel_relaxed(msg->rx_size, mb->mbox_base + MAILBOX_A2B_DAT(idx));
+
+	return 0;
+}
+
+static int rockchip_mbox_startup(struct mbox_chan *chan)
+{
+	return 0;
+}
+
+static void rockchip_mbox_shutdown(struct mbox_chan *chan)
+{
+	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
+	int idx = chan_to_idx(mb, chan);
+
+	mb->chans[idx].msg = NULL;
+}
+
+static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
+	.send_data	= rockchip_mbox_send_data,
+	.startup	= rockchip_mbox_startup,
+	.shutdown	= rockchip_mbox_shutdown,
+};
+
+static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
+{
+	int idx;
+	struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
+	u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
+
+	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
+		if ((status & (1 << idx)) && (irq == mb->chans[idx].irq)) {
+			/* Clear mbox interrupt */
+			writel_relaxed(1 << idx,
+				       mb->mbox_base + MAILBOX_B2A_STATUS);
+			return IRQ_WAKE_THREAD;
+		}
+	}
+
+	return IRQ_NONE;
+}
+
+static irqreturn_t rockchip_mbox_isr(int irq, void *dev_id)
+{
+	int idx;
+	struct rockchip_mbox_msg *msg = NULL;
+	struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
+
+	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
+		if (irq != mb->chans[idx].irq)
+			continue;
+
+		msg = mb->chans[idx].msg;
+		if (!msg) {
+			dev_err(mb->mbox.dev,
+				"Chan[%d]: B2A message is NULL\n", idx);
+			break; /* spurious */
+		}
+
+		if (msg->rx_buf)
+			memcpy(msg->rx_buf,
+			       mb->buf_base + B2A_BUF(mb->buf_size, idx),
+			       msg->rx_size);
+
+		mbox_chan_received_data(&mb->mbox.chans[idx], msg);
+		mb->chans[idx].msg = NULL;
+
+		dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n",
+			idx, msg->cmd);
+
+		break;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static const struct rockchip_mbox_data rk3368_drv_data = {
+	.num_chans = 4,
+};
+
+static const struct of_device_id rockchip_mbox_of_match[] = {
+	{ .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, rockchp_mbox_of_match);
+
+static int rockchip_mbox_probe(struct platform_device *pdev)
+{
+	struct rockchip_mbox *mb;
+	const struct of_device_id *match;
+	const struct rockchip_mbox_data *drv_data;
+	struct resource *res;
+	int ret, irq, i;
+
+	if (!pdev->dev.of_node)
+		return -ENODEV;
+
+	match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
+	drv_data = (const struct rockchip_mbox_data *)match->data;
+
+	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
+	if (!mb)
+		return -ENOMEM;
+
+	mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
+				 sizeof(*mb->chans), GFP_KERNEL);
+	if (!mb->chans)
+		return -ENOMEM;
+
+	mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
+				      sizeof(*mb->mbox.chans), GFP_KERNEL);
+	if (!mb->mbox.chans)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, mb);
+
+	mb->mbox.dev = &pdev->dev;
+	mb->mbox.num_chans = drv_data->num_chans;
+	mb->mbox.ops = &rockchip_mbox_chan_ops;
+	mb->mbox.txdone_irq = true;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(mb->mbox_base))
+		return PTR_ERR(mb->mbox_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (!res)
+		return -ENODEV;
+
+	/* Each channel has two buffers for A2B and B2A */
+	mb->buf_size = resource_size(res) / (drv_data->num_chans * 2);
+	mb->buf_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(mb->buf_base))
+		return PTR_ERR(mb->buf_base);
+
+	mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
+	if (IS_ERR(mb->pclk)) {
+		ret = PTR_ERR(mb->pclk);
+		dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
+			ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(mb->pclk);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
+		return ret;
+	}
+
+	for (i = 0; i < mb->mbox.num_chans; i++) {
+		irq = platform_get_irq(pdev, i);
+		if (irq < 0)
+			return irq;
+
+		ret = devm_request_threaded_irq(&pdev->dev, irq,
+						rockchip_mbox_irq,
+						rockchip_mbox_isr, IRQF_ONESHOT,
+						dev_name(&pdev->dev), mb);
+		if (ret < 0)
+			return ret;
+
+		mb->chans[i].idx = i;
+		mb->chans[i].mb = mb;
+		mb->chans[i].msg = NULL;
+		mb->chans[i].irq = irq;
+	}
+
+	/* Enable all B2A interrupts */
+	writel_relaxed((1 << mb->mbox.num_chans) - 1,
+		       mb->mbox_base + MAILBOX_B2A_INTEN);
+
+	ret = mbox_controller_register(&mb->mbox);
+	if (ret < 0)
+		dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
+
+	return ret;
+}
+
+static int rockchip_mbox_remove(struct platform_device *pdev)
+{
+	struct rockchip_mbox *mb = platform_get_drvdata(pdev);
+
+	if (!mb)
+		return -EINVAL;
+
+	mbox_controller_unregister(&mb->mbox);
+
+	return 0;
+}
+
+static struct platform_driver rockchip_mbox_driver = {
+	.probe	= rockchip_mbox_probe,
+	.remove	= rockchip_mbox_remove,
+	.driver = {
+		.name = "rockchip-mailbox",
+		.of_match_table = of_match_ptr(rockchip_mbox_of_match),
+	},
+};
+
+static int __init rockchip_mbox_init(void)
+{
+	return platform_driver_register(&rockchip_mbox_driver);
+}
+subsys_initcall(rockchip_mbox_init);
-- 
1.9.1

[PATCH 3/3] ARM64: dts: rk3368: Add mailbox device nodes

[Caesar Wang]

This adds mailbox device nodes in dts.

mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processormZ

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index a712bea..9ac5cca 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -484,6 +484,19 @@
 		status = "disabled";
 	};
 
+	mbox: mbox@ff6b0000 {
+		compatible = "rockchip,rk3368-mailbox";
+		reg = <0x0 0xff6b0000 0x0 0x1000>,
+		      <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
+		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_MAILBOX>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <1>;
+	};
+
 	pmugrf: syscon@ff738000 {
 		compatible = "rockchip,rk3368-pmugrf", "syscon";
 		reg = <0x0 0xff738000 0x0 0x1000>;
-- 
1.9.1

Re: [PATCH 0/3] mailbox: rockchip: Add mailbox driver for Rockchip platform

[Caesar Wang]

Hello Jassi,

Friendly Ping!

Could you review this series patchs if you have free time?


在 2015年09月14日 19:06, Caesar Wang 写道:
> Mailbox is used by the Rockchip CPU cores to communicate
> requests to MCU processorm.
>
> This driver is found on RK3368 SoCs.
>
> The Mailbox module is a simple APB peripheral that allows both
> the Cortex-A53 MCU system to communicate by writing operation to
> generate interrupt.
> The registers are accessible by both CPU via APB interface.
>
> Tested on RK3368 SDK board.
>
>
>
> Caesar Wang (3):
>    dt-bindings: Add document of Rockchip mailbox
>    mailbox: rockchip: Add Rockchip mailbox driver
>    ARM64: dts: rk3368: Add mailbox device nodes
>
>   .../bindings/mailbox/rockchip-mailbox.txt          |  33 +++
>   arch/arm64/boot/dts/rockchip/rk3368.dtsi           |  13 +
>   drivers/mailbox/Kconfig                            |   9 +
>   drivers/mailbox/Makefile                           |   2 +
>   drivers/mailbox/rockchip-mailbox.c                 | 317 +++++++++++++++++++++
>   5 files changed, 374 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>   create mode 100644 drivers/mailbox/rockchip-mailbox.c
>

-- 
Thanks,
Caesar

Re: [PATCH 0/3] mailbox: rockchip: Add mailbox driver for Rockchip platform

[Jassi Brar]

On Sun, Sep 27, 2015 at 7:09 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
> Hello Jassi,
>
> Friendly Ping!
>
> Could you review this series patchs if you have free time?
>
It's been only 2 weeks since you posted the driver and I have been
busy with stuff that missed the last release. I did not miss your
patchset.

-Jassi

Re: [PATCH 1/3] dt-bindings: Add document of Rockchip mailbox

[Jassi Brar]

On Mon, Sep 14, 2015 at 4:36 PM, Caesar Wang <wxt@rock-chips.com> wrote:
> This add the necessary binding documentation for mailbox
> found on RK3368 SoC.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
>  .../bindings/mailbox/rockchip-mailbox.txt          | 33 ++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>
> diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
> new file mode 100644
> index 0000000..b9b4768
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
> @@ -0,0 +1,33 @@
> +Rockchip mailbox
> +
> +The Rockchip mailbox is used by the Rockchip CPU cores to communicate
> +requests to MCU processor.
> +
> +Refer to ./mailbox.txt for generic information about mailbox device-tree
> +bindings.
> +
> +Required properties:
> +
> + - compatible: should be one of the following.
> +   - "rockchip,rk3368-mbox" for rk3368
> + - reg: physical base address of the controller and length of memory mapped
> +       region.
> +       physical base address of the share buffer and length of memory mapped
> +       region.
Please make shared-sram a property of user drivers.

Location and size of shared-memory is a platform property, mailbox
controller doesn't need sram to function.
  For example, protocol on some platform, with this controller, may be
trivial enough to not need a shared sram... say only 32-bits wide
requests and responses which can be passed via mailbox registers
directly.   mbox_client.tx_prepare() is where the user driver sets up
the shared-memory.

Re: [PATCH 2/3] mailbox: rockchip: Add Rockchip mailbox driver

[Jassi Brar]

On Mon, Sep 14, 2015 at 4:36 PM, Caesar Wang <wxt@rock-chips.com> wrote:
> This driver is found on RK3368 SoCs.
>
> The Mailbox module is a simple APB peripheral that allows both
> the Cortex-A53 MCU system to communicate by writing operation to
> generate interrupt.
> The registers are accessible by both CPU via APB interface.
>
> The Mailbox has the following main features:
>
> @ Support dual-core system: Cortex-A53 and MCU.
> @ Support APB interface.
> @ Support four mailbox elements, each element includes one data word, one
>   command word register and one flag bit that can represent one interrupt.
> @ Four interrupts to Cortex-A53.
> @ Four interrupts to MCU.
> @ Provide 32 lock registers for software to use to indicate whether mailbox
>   is occupied.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
>  drivers/mailbox/Kconfig            |   9 ++
>  drivers/mailbox/Makefile           |   2 +
>  drivers/mailbox/rockchip-mailbox.c | 317 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 328 insertions(+)
>  create mode 100644 drivers/mailbox/rockchip-mailbox.c
>
> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
> index bbec500..a548d700 100644
> --- a/drivers/mailbox/Kconfig
> +++ b/drivers/mailbox/Kconfig
> @@ -43,6 +43,15 @@ config OMAP_MBOX_KFIFO_SIZE
>           This can also be changed at runtime (via the mbox_kfifo_size
>           module parameter).
>
> +config ROCKCHIP_MBOX
> +       bool "Rockchip Soc Intergrated Mailbox Support"
> +       depends on ARCH_ROCKCHIP
> +       help
> +         This driver provides support for inter-processor communication
> +         between CPU cores and MCU processor on Some Rockchip SOCs.
> +         Please check it that the Soc you use have Mailbox hardware.
> +         Say Y here if you want to use the Rockchip Mailbox support.
> +
>  config PCC
>         bool "Platform Communication Channel Driver"
>         depends on ACPI
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
> index 8e6d822..730cb5d 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -8,6 +8,8 @@ obj-$(CONFIG_PL320_MBOX)        += pl320-ipc.o
>
>  obj-$(CONFIG_OMAP2PLUS_MBOX)   += omap-mailbox.o
>
> +obj-$(CONFIG_ROCKCHIP_MBOX)    += rockchip-mailbox.o
> +
>  obj-$(CONFIG_PCC)              += pcc.o
>
>  obj-$(CONFIG_ALTERA_MBOX)      += mailbox-altera.o
> diff --git a/drivers/mailbox/rockchip-mailbox.c b/drivers/mailbox/rockchip-mailbox.c
> new file mode 100644
> index 0000000..715ab96
> --- /dev/null
> +++ b/drivers/mailbox/rockchip-mailbox.c
> @@ -0,0 +1,317 @@
> +/*
> + * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * Authors:    Addy Ke <addy.ke@rock-chips.com>
> + *             Caesar Wang <wxt@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mailbox_controller.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#define MAILBOX_A2B_INTEN              0x00
> +#define MAILBOX_A2B_STATUS             0x04
> +#define MAILBOX_A2B_CMD(x)             (0x08 + (x) * 8)
> +#define MAILBOX_A2B_DAT(x)             (0x0c + (x) * 8)
> +
> +#define MAILBOX_B2A_INTEN              0x28
> +#define MAILBOX_B2A_STATUS             0x2C
> +#define MAILBOX_B2A_CMD(x)             (0x30 + (x) * 8)
> +#define MAILBOX_B2A_DAT(x)             (0x34 + (x) * 8)
> +
> +#define MAILBOX_ATOMIC_LOCK(x)         (0x100 + (x) * 8)
> +
> +/* A2B: 0 - 2k */
> +#define A2B_BUF(size, idx)             ((idx) * (size))
> +
> +/* B2A: 2k - 4k */
> +#define B2A_BUF(size, idx)             (((idx) + 4) * (size))
> +
> +struct rockchip_mbox_msg {
> +       u32 cmd;
> +       int tx_size;
> +       void *tx_buf;
> +       int rx_size;
> +       void *rx_buf;
> +       void *cl_data;
> +};
> +
> +struct rockchip_mbox_data {
> +       int num_chans;
> +};
> +
> +struct rockchip_mbox_chan {
> +       int idx;
> +       int irq;
> +       struct rockchip_mbox_msg *msg;
> +       struct rockchip_mbox *mb;
> +};
> +
> +struct rockchip_mbox {
> +       struct mbox_controller mbox;
> +       struct clk *pclk;
> +       void __iomem *mbox_base;
> +
> +       /* The base address of share memory to transfer data */
> +       void __iomem *buf_base;
> +
> +       /* The maximum size of buf for each channel */
> +       u32 buf_size;
> +
> +       struct rockchip_mbox_chan *chans;
> +};
> +
> +static inline int chan_to_idx(struct rockchip_mbox *mb,
> +                             struct mbox_chan *chan)
> +{
> +       return (chan - mb->mbox.chans);
> +}
perhaps you intended rockchip_mbox_chan.idx for this purpose?


> +static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
> +{
> +       struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
> +       struct rockchip_mbox_msg *msg = data;
> +       int idx = chan_to_idx(mb, chan);
> +
> +       if (!msg)
> +               return -EINVAL;
> +
> +       if ((msg->tx_size > mb->buf_size) ||
> +           (msg->rx_size > mb->buf_size)) {
> +               dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
> +                       mb->buf_size);
> +               return -EINVAL;
> +       }
> +
> +       dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
> +               idx, msg->cmd);
> +
> +       mb->chans[idx].msg = msg;
> +
> +       if (msg->tx_buf)
> +               memcpy(mb->buf_base + A2B_BUF(mb->buf_size, idx),
> +                      msg->tx_buf, msg->tx_size);
> +
as I said on the bindings patch, this should be done by client driver
in tx_prepare() callback.

> +       writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(idx));
> +       writel_relaxed(msg->rx_size, mb->mbox_base + MAILBOX_A2B_DAT(idx));
> +
Usually length of payload is not specified via mailbox registers but
we have to live with what your protocol does... so maybe keep rx_size
in rockchip_mbox_msg but remove  tx_size, tx_buf, void *rx_buf, and
cl_data


> +       return 0;
> +}
> +
> +static int rockchip_mbox_startup(struct mbox_chan *chan)
> +{
> +       return 0;
> +}
maybe request the channel irq in startup and release in shutdown ?

Re: [PATCH 1/3] dt-bindings: Add document of Rockchip mailbox

[Rob Herring]

On Mon, Sep 14, 2015 at 6:06 AM, Caesar Wang <wxt@rock-chips.com> wrote:
> This add the necessary binding documentation for mailbox
> found on RK3368 SoC.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
>  .../bindings/mailbox/rockchip-mailbox.txt          | 33 ++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>
> diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
> new file mode 100644
> index 0000000..b9b4768
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
> @@ -0,0 +1,33 @@
> +Rockchip mailbox
> +
> +The Rockchip mailbox is used by the Rockchip CPU cores to communicate
> +requests to MCU processor.
> +
> +Refer to ./mailbox.txt for generic information about mailbox device-tree
> +bindings.
> +
> +Required properties:
> +
> + - compatible: should be one of the following.
> +   - "rockchip,rk3368-mbox" for rk3368
> + - reg: physical base address of the controller and length of memory mapped
> +       region.
> +       physical base address of the share buffer and length of memory mapped

s/share/shared/

> +       region.
> + - interrupts: The interrupt number to the cpu. The interrupt specifier format
> +       depends on the interrupt controller.

Need to specify the value of #mbox-cells.

> +
> +Example:
> +--------
> +
> +/* RK3368 */
> +mbox: mbox@ff6b0000 {
> +       compatible = "rockchip,rk3368-mailbox";
> +       reg = <0x0 0xff6b0000 0x0 0x1000>,
> +             <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */

If this is just onchip SRAM usable for anything, then use the SRAM
binding (misc/sram.txt). It has provisions for defining the use.

> +       interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +       #mbox-cells = <1>;
> +};
> --
> 1.9.1
>

Re: [PATCH 1/3] dt-bindings: Add document of Rockchip mailbox

[Caesar Wang]

I'm missing this patch for long time.

在 2015年10月06日 22:50, Rob Herring 写道:
> On Mon, Sep 14, 2015 at 6:06 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>> This add the necessary binding documentation for mailbox
>> found on RK3368 SoC.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> ---
>>
>>   .../bindings/mailbox/rockchip-mailbox.txt          | 33 ++++++++++++++++++++++
>>   1 file changed, 33 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>> new file mode 100644
>> index 0000000..b9b4768
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>> @@ -0,0 +1,33 @@
>> +Rockchip mailbox
>> +
>> +The Rockchip mailbox is used by the Rockchip CPU cores to communicate
>> +requests to MCU processor.
>> +
>> +Refer to ./mailbox.txt for generic information about mailbox device-tree
>> +bindings.
>> +
>> +Required properties:
>> +
>> + - compatible: should be one of the following.
>> +   - "rockchip,rk3368-mbox" for rk3368
>> + - reg: physical base address of the controller and length of memory mapped
>> +       region.
>> +       physical base address of the share buffer and length of memory mapped
> s/share/shared/

Done.

>
>> +       region.
>> + - interrupts: The interrupt number to the cpu. The interrupt specifier format
>> +       depends on the interrupt controller.
> Need to specify the value of #mbox-cells.

Done.
>> +
>> +Example:
>> +--------
>> +
>> +/* RK3368 */
>> +mbox: mbox@ff6b0000 {
>> +       compatible = "rockchip,rk3368-mailbox";
>> +       reg = <0x0 0xff6b0000 0x0 0x1000>,
>> +             <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
> If this is just onchip SRAM usable for anything, then use the SRAM
> binding (misc/sram.txt). It has provisions for defining the use.

Okay,  we don't need define the shared-sram in this document.

>> +       interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
>> +                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
>> +                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
>> +                    <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
>> +       #mbox-cells = <1>;
>> +};
>> --
>> 1.9.1
>>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
Thanks,
Caesar

Re: [PATCH 1/3] dt-bindings: Add document of Rockchip mailbox

[Caesar Wang]

Hello Jassi,

Sorry for delay reply.
在 2015年10月06日 18:34, Jassi Brar 写道:
> On Mon, Sep 14, 2015 at 4:36 PM, Caesar Wang <wxt@rock-chips.com> wrote:
>> This add the necessary binding documentation for mailbox
>> found on RK3368 SoC.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> ---
>>
>>   .../bindings/mailbox/rockchip-mailbox.txt          | 33 ++++++++++++++++++++++
>>   1 file changed, 33 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>> new file mode 100644
>> index 0000000..b9b4768
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
>> @@ -0,0 +1,33 @@
>> +Rockchip mailbox
>> +
>> +The Rockchip mailbox is used by the Rockchip CPU cores to communicate
>> +requests to MCU processor.
>> +
>> +Refer to ./mailbox.txt for generic information about mailbox device-tree
>> +bindings.
>> +
>> +Required properties:
>> +
>> + - compatible: should be one of the following.
>> +   - "rockchip,rk3368-mbox" for rk3368
>> + - reg: physical base address of the controller and length of memory mapped
>> +       region.
>> +       physical base address of the share buffer and length of memory mapped
>> +       region.
> Please make shared-sram a property of user drivers.

As Rob points out,
maybe, don't we need also define it in user drivers.
As the SRAM binding (misc/sram.txt) had defined.

I just make the SCPI protocol client driver to work for mailbox.
>
> Location and size of shared-memory is a platform property, mailbox
> controller doesn't need sram to function.
>    For example, protocol on some platform, with this controller, may be
> trivial enough to not need a shared sram... say only 32-bits wide
> requests and responses which can be passed via mailbox registers
> directly.   mbox_client.tx_prepare() is where the user driver sets up
> the shared-memory.
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
Thanks,
Caesar