From: "Suzuki K. Poulose" <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: marc.zyngier@arm.com, will.deacon@arm.com, mark.rutland@arm.com,
catalin.marinas@arm.com, steve.capper@linaro.org,
linux-kernel@vger.kernel.org, andre.przywara@arm.com,
dave.martin@arm.com, Vladimir.Murzin@arm.com,
james.morse@arm.com, ard.biesheuvel@linaro.org,
edward.nevill@linaro.org, aph@redhat.com,
"Suzuki K. Poulose" <suzuki.poulose@arm.com>
Subject: [PATCH v2 20/22] arm64: Expose feature registers by emulating MRS
Date: Mon, 5 Oct 2015 18:02:09 +0100 [thread overview]
Message-ID: <1444064531-25607-21-git-send-email-suzuki.poulose@arm.com> (raw)
In-Reply-To: <1444064531-25607-1-git-send-email-suzuki.poulose@arm.com>
This patch adds the hook for emulating MRS instruction to
export the 'user visible' value of supported system registers.
We emulate only the following id space for system registers:
Op0=0, Op1=0, CRn=0.
The rest will fall back to SIGILL.
This capability is also advertised via a new HWCAP_CPUID.
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/sysreg.h | 3 ++
arch/arm64/include/uapi/asm/hwcap.h | 1 +
arch/arm64/kernel/cpufeature.c | 95 +++++++++++++++++++++++++++++++++++
arch/arm64/kernel/cpuinfo.c | 1 +
4 files changed, 100 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index dc72fc6..b44ad93 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -192,6 +192,9 @@
#define MVFR1_FPFTZ_SHIFT 0
+/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:1 */
+#define SYS_MPIDR_SAFE_VAL ((1UL<<31)|(1UL<<24))
+
#ifdef __ASSEMBLY__
.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index 361c8a8..3386e64 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -28,5 +28,6 @@
#define HWCAP_SHA2 (1 << 6)
#define HWCAP_CRC32 (1 << 7)
#define HWCAP_ATOMICS (1 << 8)
+#define HWCAP_CPUID (1 << 9)
#endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f8fee51..54a8f2e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -24,6 +24,7 @@
#include <asm/cpufeature.h>
#include <asm/processor.h>
#include <asm/sysreg.h>
+#include <asm/traps.h>
unsigned long elf_hwcap __read_mostly;
EXPORT_SYMBOL_GPL(elf_hwcap);
@@ -710,6 +711,8 @@ void check_cpu_hwcaps(void)
{
int i;
const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
+
+ elf_hwcap |= HWCAP_CPUID;
for(i = 0; i < ARRAY_SIZE(arm64_hwcaps); i ++)
if (hwcaps[i].matches(&hwcaps[i]))
cap_set_hwcap(&hwcaps[i]);
@@ -880,3 +883,95 @@ void __init setup_cpu_features(void)
pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
L1_CACHE_BYTES, cls);
}
+
+/*
+ * We emulate only the following system register space.
+ * Op0 = 0x3, CRn = 0x0, Op1 = 0x0
+ * See Table C5-6 System instruction encodings for System register accesses,
+ * ARMv8 ARM(ARM DDI 0487A.f) for more details.
+ */
+static int __attribute_const__ is_emulated(u32 id)
+{
+ if (sys_reg_Op0(id) != 0x3 ||
+ sys_reg_CRn(id) != 0x0 ||
+ sys_reg_Op1(id) != 0x0)
+ return 0;
+ return 1;
+}
+
+/*
+ * With CRm = 0, id should be one of :
+ * MIDR_EL1
+ * MPIDR_EL1
+ * REVIDR_EL1
+ */
+static int emulate_id_reg(u32 id, u64 *valp)
+{
+ switch(id) {
+ case SYS_MIDR_EL1:
+ *valp = read_cpuid_id();
+ return 0;
+ case SYS_MPIDR_EL1:
+ *valp = SYS_MPIDR_SAFE_VAL;
+ return 0;
+ case SYS_REVIDR_EL1:
+ *valp = 0;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int emulate_sys_reg(u32 id, u64 *valp)
+{
+ struct arm64_ftr_reg *regp;
+
+ if (!is_emulated(id))
+ return -EINVAL;
+
+ if (sys_reg_CRm(id) == 0)
+ return emulate_id_reg(id, valp);
+
+ regp = get_arm64_sys_reg(id);
+ if (regp)
+ *valp = regp->user_val | (regp->sys_val & regp->user_mask);
+ else
+ /*
+ * Registers we don't track are either IMPLEMENTAION DEFINED
+ * (e.g, ID_AFR0_EL1) or reserved RAZ.
+ */
+ *valp = 0;
+ return 0;
+}
+
+static int emulate_mrs(struct pt_regs *regs, u32 insn)
+{
+ int rc = 0;
+ u32 sys_reg, dst;
+ u64 val = 0;
+
+ sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn);
+ rc = emulate_sys_reg(sys_reg, &val);
+ if (rc)
+ return rc;
+ dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT ,insn);
+ regs->user_regs.regs[dst] = val;
+ regs->pc += 4;
+ return 0;
+}
+
+static struct undef_hook mrs_hook = {
+ .instr_mask = 0xfff00000,
+ .instr_val = 0xd5300000,
+ .pstate_mask = COMPAT_PSR_MODE_MASK,
+ .pstate_val = PSR_MODE_EL0t,
+ .fn = emulate_mrs,
+};
+
+int __init arm64_cpufeature_init(void)
+{
+ register_undef_hook(&mrs_hook);
+ return 0;
+}
+
+late_initcall(arm64_cpufeature_init);
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 789fbea..52331ff 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -58,6 +58,7 @@ static const char *hwcap_str[] = {
"sha2",
"crc32",
"atomics",
+ "cpuid",
NULL
};
--
1.7.9.5
next prev parent reply other threads:[~2015-10-05 17:04 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-05 17:01 [PATCH v2 00/22] arm64: Consolidate CPU feature handling Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 01/22] arm64: Make the CPU information more clear Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 02/22] arm64: Delay ELF HWCAP initialisation until all CPUs are up Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 03/22] arm64: Move cpu feature detection code Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 04/22] arm64: Move mixed endian support detection Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 05/22] arm64: Move /proc/cpuinfo handling code Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 06/22] arm64: sys_reg: Define System register encoding Suzuki K. Poulose
2015-10-07 16:36 ` Catalin Marinas
2015-10-07 17:03 ` Suzuki K. Poulose
2015-10-08 14:43 ` Catalin Marinas
2015-10-08 16:13 ` Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 07/22] arm64: Keep track of CPU feature registers Suzuki K. Poulose
2015-10-07 17:16 ` Catalin Marinas
2015-10-08 9:55 ` Suzuki K. Poulose
2015-10-08 15:03 ` Catalin Marinas
2015-10-09 13:00 ` Suzuki K. Poulose
2015-10-12 17:01 ` Suzuki K. Poulose
2015-10-12 17:21 ` Mark Rutland
2015-10-13 9:40 ` Catalin Marinas
2015-10-09 10:56 ` Suzuki K. Poulose
2015-10-09 14:16 ` Catalin Marinas
2015-10-05 17:01 ` [PATCH v2 08/22] arm64: Consolidate CPU Sanity check to CPU Feature infrastructure Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 09/22] arm64: Read system wide CPUID value Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 10/22] arm64: Cleanup mixed endian support detection Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 11/22] arm64: Populate cpuinfo after notify_cpu_starting Suzuki K. Poulose
2015-10-08 10:15 ` Catalin Marinas
2015-10-08 10:46 ` Suzuki K. Poulose
2015-10-09 15:01 ` Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 12/22] arm64: Delay cpu feature checks Suzuki K. Poulose
2015-10-06 4:41 ` kbuild test robot
2015-10-06 11:09 ` Suzuki K. Poulose
2015-10-08 11:08 ` Catalin Marinas
2015-10-13 10:12 ` Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 13/22] arm64: Make use of system wide capability checks Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 14/22] arm64: Cleanup HWCAP handling Suzuki K. Poulose
2015-10-08 11:10 ` Catalin Marinas
2015-10-08 11:17 ` Russell King - ARM Linux
2015-10-08 13:00 ` Catalin Marinas
2015-10-08 14:54 ` Edward Nevill
2015-10-05 17:02 ` [PATCH v2 15/22] arm64: Move FP/ASIMD hwcap handling to common code Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 16/22] arm64/debug: Make use of the system wide safe value Suzuki K. Poulose
2015-10-08 11:11 ` Catalin Marinas
2015-10-08 11:56 ` Suzuki K. Poulose
2015-10-08 15:08 ` Catalin Marinas
2015-10-08 15:57 ` Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 17/22] arm64/kvm: Make use of the system wide safe values Suzuki K. Poulose
2015-10-10 15:17 ` Christoffer Dall
2015-10-05 17:02 ` [PATCH v2 18/22] arm64: Add helper to decode register from instruction Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 19/22] arm64: cpufeature: Track the user visible fields Suzuki K. Poulose
2015-10-05 17:02 ` Suzuki K. Poulose [this message]
2015-10-05 17:02 ` [PATCH v2 21/22] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Suzuki K. Poulose
2015-10-06 9:09 ` Russell King - ARM Linux
2015-10-06 10:18 ` Steve Capper
2015-10-06 10:25 ` Mark Rutland
2015-10-06 10:29 ` Steve Capper
2015-10-06 19:16 ` Russell King - ARM Linux
2015-10-05 17:02 ` [PATCH v2 22/22] arm64: feature registers: Documentation Suzuki K. Poulose
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1444064531-25607-21-git-send-email-suzuki.poulose@arm.com \
--to=suzuki.poulose@arm.com \
--cc=Vladimir.Murzin@arm.com \
--cc=andre.przywara@arm.com \
--cc=aph@redhat.com \
--cc=ard.biesheuvel@linaro.org \
--cc=catalin.marinas@arm.com \
--cc=dave.martin@arm.com \
--cc=edward.nevill@linaro.org \
--cc=james.morse@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=steve.capper@linaro.org \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).