From: "Suzuki K. Poulose" <Suzuki.Poulose@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: mark.rutland@arm.com, Vladimir.Murzin@arm.com,
steve.capper@linaro.org, ard.biesheuvel@linaro.org,
marc.zyngier@arm.com, andre.przywara@arm.com,
will.deacon@arm.com, linux-kernel@vger.kernel.org,
edward.nevill@linaro.org, aph@redhat.com, james.morse@arm.com,
dave.martin@arm.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 06/22] arm64: sys_reg: Define System register encoding
Date: Thu, 8 Oct 2015 17:13:27 +0100 [thread overview]
Message-ID: <56169627.9090307@arm.com> (raw)
In-Reply-To: <20151008144348.GJ17192@e104818-lin.cambridge.arm.com>
On 08/10/15 15:43, Catalin Marinas wrote:
> On Wed, Oct 07, 2015 at 06:03:34PM +0100, Suzuki K. Poulose wrote:
>> On 07/10/15 17:36, Catalin Marinas wrote:
>>> On Mon, Oct 05, 2015 at 06:01:55PM +0100, Suzuki K. Poulose wrote:
>>>> * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
>>>> * C5.2, version:ARM DDI 0487A.f)
>>>> * [20-19] : Op0
>>>> @@ -34,15 +34,40 @@
>>>> * [15-12] : CRn
>>>> * [11-8] : CRm
>>>> * [7-5] : Op2
>>>> + * Hence we use [ sys_reg() << 5 ] in the mrs/msr instructions.
>>>
>>> Do we really need to have all the ids shifted right by 5? I can't see
>>> where it helps. OTOH, it makes the code more complicated by having to
>>> remember to shift the id left by 5.
>>
>> This is a cosmetic change, to reuse the sys_reg() definitions for both
>> mrs_s/msr_s macros and the CPU ID. The (existing)left shift is only needed
>> for the mrs_s/msr_s, so the existing users don't have to worry about the shift
>> unless they have hard-open-coded values for the register. On the plus
>> side it becomes slightly easier to use the same encoding for CPU id
>> tracking (and manual decoding). If you think this is superfluous, I could
>> change the CPU-id to use right shifted values from sys_reg.
>
> You may be right but I still fail to see whether the shifted values are
> useful to the CPUID code. Are you referring to the 'switch' statements?
>
Yes. Again we can adjust the macros to get the right fields for switch().
Its also about the meaning of sys_reg(). The name kind of implies the system
register encoding defined by ARM ARM. However the current version
defines the encoding as it appears in the mrs/msr instructions, which can
be confusing if we start using the same encoding for representing the sys_reg
elsewhere(in this case CPUID infrastructure). Again, I am not too particular
about this change.
Suzuki
next prev parent reply other threads:[~2015-10-08 16:13 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-05 17:01 [PATCH v2 00/22] arm64: Consolidate CPU feature handling Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 01/22] arm64: Make the CPU information more clear Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 02/22] arm64: Delay ELF HWCAP initialisation until all CPUs are up Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 03/22] arm64: Move cpu feature detection code Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 04/22] arm64: Move mixed endian support detection Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 05/22] arm64: Move /proc/cpuinfo handling code Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 06/22] arm64: sys_reg: Define System register encoding Suzuki K. Poulose
2015-10-07 16:36 ` Catalin Marinas
2015-10-07 17:03 ` Suzuki K. Poulose
2015-10-08 14:43 ` Catalin Marinas
2015-10-08 16:13 ` Suzuki K. Poulose [this message]
2015-10-05 17:01 ` [PATCH v2 07/22] arm64: Keep track of CPU feature registers Suzuki K. Poulose
2015-10-07 17:16 ` Catalin Marinas
2015-10-08 9:55 ` Suzuki K. Poulose
2015-10-08 15:03 ` Catalin Marinas
2015-10-09 13:00 ` Suzuki K. Poulose
2015-10-12 17:01 ` Suzuki K. Poulose
2015-10-12 17:21 ` Mark Rutland
2015-10-13 9:40 ` Catalin Marinas
2015-10-09 10:56 ` Suzuki K. Poulose
2015-10-09 14:16 ` Catalin Marinas
2015-10-05 17:01 ` [PATCH v2 08/22] arm64: Consolidate CPU Sanity check to CPU Feature infrastructure Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 09/22] arm64: Read system wide CPUID value Suzuki K. Poulose
2015-10-05 17:01 ` [PATCH v2 10/22] arm64: Cleanup mixed endian support detection Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 11/22] arm64: Populate cpuinfo after notify_cpu_starting Suzuki K. Poulose
2015-10-08 10:15 ` Catalin Marinas
2015-10-08 10:46 ` Suzuki K. Poulose
2015-10-09 15:01 ` Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 12/22] arm64: Delay cpu feature checks Suzuki K. Poulose
2015-10-06 4:41 ` kbuild test robot
2015-10-06 11:09 ` Suzuki K. Poulose
2015-10-08 11:08 ` Catalin Marinas
2015-10-13 10:12 ` Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 13/22] arm64: Make use of system wide capability checks Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 14/22] arm64: Cleanup HWCAP handling Suzuki K. Poulose
2015-10-08 11:10 ` Catalin Marinas
2015-10-08 11:17 ` Russell King - ARM Linux
2015-10-08 13:00 ` Catalin Marinas
2015-10-08 14:54 ` Edward Nevill
2015-10-05 17:02 ` [PATCH v2 15/22] arm64: Move FP/ASIMD hwcap handling to common code Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 16/22] arm64/debug: Make use of the system wide safe value Suzuki K. Poulose
2015-10-08 11:11 ` Catalin Marinas
2015-10-08 11:56 ` Suzuki K. Poulose
2015-10-08 15:08 ` Catalin Marinas
2015-10-08 15:57 ` Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 17/22] arm64/kvm: Make use of the system wide safe values Suzuki K. Poulose
2015-10-10 15:17 ` Christoffer Dall
2015-10-05 17:02 ` [PATCH v2 18/22] arm64: Add helper to decode register from instruction Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 19/22] arm64: cpufeature: Track the user visible fields Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 20/22] arm64: Expose feature registers by emulating MRS Suzuki K. Poulose
2015-10-05 17:02 ` [PATCH v2 21/22] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Suzuki K. Poulose
2015-10-06 9:09 ` Russell King - ARM Linux
2015-10-06 10:18 ` Steve Capper
2015-10-06 10:25 ` Mark Rutland
2015-10-06 10:29 ` Steve Capper
2015-10-06 19:16 ` Russell King - ARM Linux
2015-10-05 17:02 ` [PATCH v2 22/22] arm64: feature registers: Documentation Suzuki K. Poulose
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