From: Jisheng Zhang <jszhang@marvell.com>
To: <bhelgaas@google.com>, <thierry.reding@gmail.com>,
<swarren@wwwdotorg.org>, <gnurou@gmail.com>, <tinamdar@apm.com>,
<rjui@broadcom.com>, <sbranden@broadcom.com>,
<linux@arm.linux.org.uk>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<bcm-kernel-feedback-list@broadcom.com>,
Jisheng Zhang <jszhang@marvell.com>
Subject: [RFC PATCH 0/3] PCI: generate proper configuration access cycles
Date: Mon, 26 Oct 2015 19:02:11 +0800 [thread overview]
Message-ID: <1445857334-6936-1-git-send-email-jszhang@marvell.com> (raw)
Inspired by Russell King's patch[1], I found some pci hosts also have the
same issue of "reading 32-bits from the command register, modifying the
command register, and then writing it back has the effect of clearing
any status bits that were indicating at that time" as pointed out by
Russell. Fix them by using the pci_generic_config_write.
Another problem is do we need to use proper readb/readw for config read?
Jisheng Zhang (3):
PCI: iproc: generate proper configuration access cycles
PCI: tegra: generate proper configuration access cycles
PCI: xgene: generate proper configuration access cycles
drivers/pci/host/pci-tegra.c | 2 +-
drivers/pci/host/pci-xgene.c | 2 +-
drivers/pci/host/pcie-iproc.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
--
2.6.2
next reply other threads:[~2015-10-26 11:06 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-26 11:02 Jisheng Zhang [this message]
2015-10-26 11:02 ` [RFC PATCH 1/3] PCI: iproc: generate proper configuration access cycles Jisheng Zhang
2015-10-26 17:18 ` Ray Jui
2015-10-27 2:18 ` Jisheng Zhang
2015-10-30 23:21 ` Arnd Bergmann
2015-10-26 11:02 ` [RFC PATCH 2/3] PCI: tegra: " Jisheng Zhang
2015-10-26 11:02 ` [RFC PATCH 3/3] PCI: xgene: " Jisheng Zhang
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