* [PATCH V2 01/12] net-next: mediatek: Document ralink/mediatek SoC ethernet binding
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-03-02 18:46 ` Rob Herring
2016-02-26 14:21 ` [PATCH V2 02/12] net-next: mediatek: add the drivers core files John Crispin
` (10 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee, devicetree
Add three files. One describes the actual frame engine, the other two
describe fast ethernet and gigabit switches bindings.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
Cc: devicetree@vger.kernel.org
---
.../devicetree/bindings/net/mediatek-net-esw.txt | 25 +++++
.../devicetree/bindings/net/mediatek-net-gsw.txt | 48 +++++++++
.../devicetree/bindings/net/mediatek-net.txt | 113 ++++++++++++++++++++
3 files changed, 186 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/mediatek-net-esw.txt
create mode 100644 Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
diff --git a/Documentation/devicetree/bindings/net/mediatek-net-esw.txt b/Documentation/devicetree/bindings/net/mediatek-net-esw.txt
new file mode 100644
index 0000000..84c51a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mediatek-net-esw.txt
@@ -0,0 +1,25 @@
+Ralink Fast Ethernet Embedded Switch
+====================================
+
+The ralink fast ethernet embedded switch can be found on Ralink and Mediatek
+SoCs (RT3x5x, RT5350, MT76x8).
+
+Required properties:
+- compatible: Should be "ralink,rt3050-esw"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the embedded switches interrupt
+
+Optional properties:
+- mediatek,led_polarity: override the active high/low settings of the leds
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device
+
+Example:
+
+esw@10110000 {
+ compatible = "ralink,rt3050-esw";
+ reg = <0x10110000 8000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+};
diff --git a/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt b/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
new file mode 100644
index 0000000..596b385
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
@@ -0,0 +1,48 @@
+Mediatek Gigabit Switch
+=======================
+
+The mediatek gigabit switch can be found on Mediatek SoCs.
+
+Required properties:
+- compatible: Should be "mediatek,mt7620-gsw", "mediatek,mt7621-gsw",
+ "mediatek,mt7623-gsw"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the gigabit switches interrupt
+
+
+Additional required properties for ARM based SoCs:
+- mediatek,reset-pin: phandle describing the reset GPIO
+- clocks: the clocks used by the switch
+- clock-names: the names of the clocks listed in the clocks property
+ these should be "trgpll", "esw", "gp2", "gp1"
+- mt7530-supply: the phandle of the regulator used to power the switch
+- mediatek,pctl-regmap: phandle to the port control regmap. this is used to
+ setup the drive current
+
+
+Optional properties:
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device
+
+Example:
+
+gsw: switch@1b100000 {
+ compatible = "mediatek,mt7623-gsw";
+ reg = <0 0x1b110000 0 0x300000>;
+
+ interrupt-parent = <&pio>;
+ interrupts = <168 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
+ <ðsys CLK_ETHSYS_ESW>,
+ <ðsys CLK_ETHSYS_GP2>,
+ <ðsys CLK_ETHSYS_GP1>;
+ clock-names = "trgpll", "esw", "gp2", "gp1";
+
+ mt7530-supply = <&mt6323_vpa_reg>;
+
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
+ mediatek,reset-pin = <&pio 15 0>;
+
+ status = "okay";
+};
diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
new file mode 100644
index 0000000..f8c5747
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
@@ -0,0 +1,113 @@
+iMEdiatek Frame Engine Ethernet controller
+=======================================
+
+The frame engine ethernet controller can be found on Ralink and Mediatek SoCs
+(RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).
+
+Depending on the SoC, there is a number of ports connected to the CPU port
+directly and/or via a (gigabit-)switch. Newer gigabit SoCs can support
+a dual MAC setup.
+
+* Ethernet controller node
+
+Required properties:
+- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
+ "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
+ "mediatek,mt7620-eth", "mediatek,mt7621-eth", "mediatek,mt7623-eth"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the frame engines interrupt
+- mediatek,ethsys: phandle to the syscon node that handles the port setup
+
+Required properties for ARM based SoCs:
+- clocks: the clock used by the core
+- clock-names: the names of the clock listed in the clocks property
+- power-domains: phandle the to power domain that the ethernet is part of
+
+Optional properties:
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device
+- mediatek,switch : phandle pointing at the device node of the switch device
+
+
+* Ethernet port node for MT7620
+
+We need to define which physical port is wired and how it should be setup.
+
+Required properties:
+- compatible: Should be "mediatek,eth-port"
+- reg: The number of the physical port
+- phy-handle: reference to the node describing the phy
+
+
+* Ethernet MAC node - dual MAC SoCs only
+
+Required properties:
+- compatible: Should be "mediatek,eth-mac"
+- reg: The number of the MAC
+
+
+Example for singel MAC SoC:
+
+mdio-bus {
+ status = "okay";
+
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ phy-mode = "rgmii";
+ };
+};
+
+eth: ethernet@10100000 {
+ compatible = "mediatek,mt7620-eth";
+ reg = <0x10100000 10000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <5>;
+
+ mediatek,switch = <&gsw>;
+
+ port@4 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&phy4>;
+ };
+};
+
+
+Example for dual MAC SoC:
+
+eth: ethernet@1b100000 {
+ compatible = "mediatek,mt7623-eth";
+ reg = <0 0x1b100000 0 0x10000>;
+
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "ethif";
+
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+
+ mediatek,ethsys = <ðsys>;
+ mediatek,switch = <&gsw>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ gmac1: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+
+ status = "okay";
+ };
+
+ gmac2: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+
+ status = "okay";
+ };
+};
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH V2 01/12] net-next: mediatek: Document ralink/mediatek SoC ethernet binding
2016-02-26 14:21 ` [PATCH V2 01/12] net-next: mediatek: Document ralink/mediatek SoC ethernet binding John Crispin
@ 2016-03-02 18:46 ` Rob Herring
2016-03-02 18:49 ` John Crispin
0 siblings, 1 reply; 26+ messages in thread
From: Rob Herring @ 2016-03-02 18:46 UTC (permalink / raw)
To: John Crispin
Cc: David S. Miller, Fred Chang (張嘉宏),
devicetree, Felix Fietkau, Steven Liu (劉人豪),
netdev, Carlos Huang (黃士彰),
linux-kernel, linux-mediatek, Matthias Brugger, Michael Lee,
linux-arm-kernel
On Fri, Feb 26, 2016 at 03:21:33PM +0100, John Crispin wrote:
> Add three files. One describes the actual frame engine, the other two
> describe fast ethernet and gigabit switches bindings.
>
> Signed-off-by: John Crispin <blogic@openwrt.org>
> Signed-off-by: Felix Fietkau <nbd@openwrt.org>
> Signed-off-by: Michael Lee <igvtee@gmail.com>
Does this reflect the order people worked on this? Your SoB typically
would be last.
> Cc: devicetree@vger.kernel.org
> ---
> .../devicetree/bindings/net/mediatek-net-esw.txt | 25 +++++
> .../devicetree/bindings/net/mediatek-net-gsw.txt | 48 +++++++++
> .../devicetree/bindings/net/mediatek-net.txt | 113 ++++++++++++++++++++
> 3 files changed, 186 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/mediatek-net-esw.txt
> create mode 100644 Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
> create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
>
> diff --git a/Documentation/devicetree/bindings/net/mediatek-net-esw.txt b/Documentation/devicetree/bindings/net/mediatek-net-esw.txt
> new file mode 100644
> index 0000000..84c51a0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/mediatek-net-esw.txt
> @@ -0,0 +1,25 @@
> +Ralink Fast Ethernet Embedded Switch
> +====================================
> +
> +The ralink fast ethernet embedded switch can be found on Ralink and Mediatek
> +SoCs (RT3x5x, RT5350, MT76x8).
> +
> +Required properties:
> +- compatible: Should be "ralink,rt3050-esw"
> +- reg: Address and length of the register set for the device
> +- interrupts: Should contain the embedded switches interrupt
> +
> +Optional properties:
> +- mediatek,led_polarity: override the active high/low settings of the leds
Don't use '_'.
This doesn't tell me what the polaritiy actually is.
> +- interrupt-parent: Should be the phandle for the interrupt controller
> + that services interrupts for this device
> +
> +Example:
> +
> +esw@10110000 {
> + compatible = "ralink,rt3050-esw";
> + reg = <0x10110000 8000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <17>;
> +};
> diff --git a/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt b/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
> new file mode 100644
> index 0000000..596b385
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
> @@ -0,0 +1,48 @@
> +Mediatek Gigabit Switch
> +=======================
> +
> +The mediatek gigabit switch can be found on Mediatek SoCs.
> +
> +Required properties:
> +- compatible: Should be "mediatek,mt7620-gsw", "mediatek,mt7621-gsw",
> + "mediatek,mt7623-gsw"
This is an OR condition? Formatting like this would be better:
Should be one of:
"mediatek,mt7620-gsw"
"mediatek,mt7621-gsw"
"mediatek,mt7623-gsw"
> +- reg: Address and length of the register set for the device
> +- interrupts: Should contain the gigabit switches interrupt
s/switches/switch's/
> +
> +
> +Additional required properties for ARM based SoCs:
Which ones are those? Describe in terms of compatible properties.
> +- mediatek,reset-pin: phandle describing the reset GPIO
> +- clocks: the clocks used by the switch
> +- clock-names: the names of the clocks listed in the clocks property
> + these should be "trgpll", "esw", "gp2", "gp1"
> +- mt7530-supply: the phandle of the regulator used to power the switch
> +- mediatek,pctl-regmap: phandle to the port control regmap. this is used to
> + setup the drive current
> +
> +
> +Optional properties:
> +- interrupt-parent: Should be the phandle for the interrupt controller
> + that services interrupts for this device
> +
> +Example:
> +
> +gsw: switch@1b100000 {
> + compatible = "mediatek,mt7623-gsw";
> + reg = <0 0x1b110000 0 0x300000>;
> +
> + interrupt-parent = <&pio>;
> + interrupts = <168 IRQ_TYPE_EDGE_RISING>;
> +
> + clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
> + <ðsys CLK_ETHSYS_ESW>,
> + <ðsys CLK_ETHSYS_GP2>,
> + <ðsys CLK_ETHSYS_GP1>;
> + clock-names = "trgpll", "esw", "gp2", "gp1";
> +
> + mt7530-supply = <&mt6323_vpa_reg>;
> +
> + mediatek,pctl-regmap = <&syscfg_pctl_a>;
> + mediatek,reset-pin = <&pio 15 0>;
> +
> + status = "okay";
> +};
> diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
> new file mode 100644
> index 0000000..f8c5747
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
> @@ -0,0 +1,113 @@
> +iMEdiatek Frame Engine Ethernet controller
typo?
> +=======================================
> +
> +The frame engine ethernet controller can be found on Ralink and Mediatek SoCs
> +(RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).
> +
> +Depending on the SoC, there is a number of ports connected to the CPU port
> +directly and/or via a (gigabit-)switch. Newer gigabit SoCs can support
> +a dual MAC setup.
> +
> +* Ethernet controller node
> +
> +Required properties:
> +- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
> + "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
> + "mediatek,mt7620-eth", "mediatek,mt7621-eth", "mediatek,mt7623-eth"
Do one per line.
> +- reg: Address and length of the register set for the device
> +- interrupts: Should contain the frame engines interrupt
> +- mediatek,ethsys: phandle to the syscon node that handles the port setup
> +
> +Required properties for ARM based SoCs:
Which ones?
> +- clocks: the clock used by the core
> +- clock-names: the names of the clock listed in the clocks property
> +- power-domains: phandle the to power domain that the ethernet is part of
> +
> +Optional properties:
> +- interrupt-parent: Should be the phandle for the interrupt controller
> + that services interrupts for this device
> +- mediatek,switch : phandle pointing at the device node of the switch device
> +
> +
> +* Ethernet port node for MT7620
> +
> +We need to define which physical port is wired and how it should be setup.
> +
> +Required properties:
> +- compatible: Should be "mediatek,eth-port"
> +- reg: The number of the physical port
> +- phy-handle: reference to the node describing the phy
> +
> +
> +* Ethernet MAC node - dual MAC SoCs only
> +
> +Required properties:
> +- compatible: Should be "mediatek,eth-mac"
> +- reg: The number of the MAC
> +
> +
> +Example for singel MAC SoC:
s/singel/single/
> +
> +mdio-bus {
> + status = "okay";
> +
> + phy4: ethernet-phy@4 {
> + reg = <4>;
> + phy-mode = "rgmii";
> + };
> +};
> +
> +eth: ethernet@10100000 {
> + compatible = "mediatek,mt7620-eth";
> + reg = <0x10100000 10000>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <5>;
> +
> + mediatek,switch = <&gsw>;
> +
> + port@4 {
> + status = "okay";
> + phy-mode = "rgmii";
> + phy-handle = <&phy4>;
> + };
> +};
> +
> +
> +Example for dual MAC SoC:
> +
> +eth: ethernet@1b100000 {
> + compatible = "mediatek,mt7623-eth";
> + reg = <0 0x1b100000 0 0x10000>;
> +
> + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
> + clock-names = "ethif";
> +
> + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
> +
> + mediatek,ethsys = <ðsys>;
> + mediatek,switch = <&gsw>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + gmac1: mac@0 {
> + compatible = "mediatek,eth-mac";
> + reg = <0>;
> +
> + status = "okay";
The parent disabled and this enabled doesn't make sense. I'd just drop
status from examples.
> + };
> +
> + gmac2: mac@1 {
> + compatible = "mediatek,eth-mac";
> + reg = <1>;
> +
> + status = "okay";
> + };
> +};
> --
> 1.7.10.4
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH V2 01/12] net-next: mediatek: Document ralink/mediatek SoC ethernet binding
2016-03-02 18:46 ` Rob Herring
@ 2016-03-02 18:49 ` John Crispin
0 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-03-02 18:49 UTC (permalink / raw)
To: Rob Herring
Cc: Fred Chang (張嘉宏),
devicetree, Felix Fietkau, Steven Liu (劉人豪),
netdev, Carlos Huang (黃士彰),
linux-kernel, linux-mediatek, Matthias Brugger, Michael Lee,
David S. Miller, linux-arm-kernel
On 02/03/2016 19:46, Rob Herring wrote:
> On Fri, Feb 26, 2016 at 03:21:33PM +0100, John Crispin wrote:
>> Add three files. One describes the actual frame engine, the other two
>> describe fast ethernet and gigabit switches bindings.
>>
>> Signed-off-by: John Crispin <blogic@openwrt.org>
>> Signed-off-by: Felix Fietkau <nbd@openwrt.org>
>> Signed-off-by: Michael Lee <igvtee@gmail.com>
>
> Does this reflect the order people worked on this? Your SoB typically
> would be last.
yes it does and the series was NAK'ed so ignore this patch. i'll order
them differently in V3
>
>> Cc: devicetree@vger.kernel.org
>> ---
>> .../devicetree/bindings/net/mediatek-net-esw.txt | 25 +++++
>> .../devicetree/bindings/net/mediatek-net-gsw.txt | 48 +++++++++
>> .../devicetree/bindings/net/mediatek-net.txt | 113 ++++++++++++++++++++
>> 3 files changed, 186 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/net/mediatek-net-esw.txt
>> create mode 100644 Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
>> create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
>>
>> diff --git a/Documentation/devicetree/bindings/net/mediatek-net-esw.txt b/Documentation/devicetree/bindings/net/mediatek-net-esw.txt
>> new file mode 100644
>> index 0000000..84c51a0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/mediatek-net-esw.txt
>> @@ -0,0 +1,25 @@
>> +Ralink Fast Ethernet Embedded Switch
>> +====================================
>> +
>> +The ralink fast ethernet embedded switch can be found on Ralink and Mediatek
>> +SoCs (RT3x5x, RT5350, MT76x8).
>> +
>> +Required properties:
>> +- compatible: Should be "ralink,rt3050-esw"
>> +- reg: Address and length of the register set for the device
>> +- interrupts: Should contain the embedded switches interrupt
>> +
>> +Optional properties:
>> +- mediatek,led_polarity: override the active high/low settings of the leds
>
> Don't use '_'.
>
> This doesn't tell me what the polaritiy actually is.
>
>> +- interrupt-parent: Should be the phandle for the interrupt controller
>> + that services interrupts for this device
>> +
>> +Example:
>> +
>> +esw@10110000 {
>> + compatible = "ralink,rt3050-esw";
>> + reg = <0x10110000 8000>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <17>;
>> +};
>> diff --git a/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt b/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
>> new file mode 100644
>> index 0000000..596b385
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/mediatek-net-gsw.txt
>> @@ -0,0 +1,48 @@
>> +Mediatek Gigabit Switch
>> +=======================
>> +
>> +The mediatek gigabit switch can be found on Mediatek SoCs.
>> +
>> +Required properties:
>> +- compatible: Should be "mediatek,mt7620-gsw", "mediatek,mt7621-gsw",
>> + "mediatek,mt7623-gsw"
>
> This is an OR condition? Formatting like this would be better:
>
> Should be one of:
> "mediatek,mt7620-gsw"
> "mediatek,mt7621-gsw"
> "mediatek,mt7623-gsw"
>
>> +- reg: Address and length of the register set for the device
>> +- interrupts: Should contain the gigabit switches interrupt
>
> s/switches/switch's/
>
>> +
>> +
>> +Additional required properties for ARM based SoCs:
>
> Which ones are those? Describe in terms of compatible properties.
>
>> +- mediatek,reset-pin: phandle describing the reset GPIO
>> +- clocks: the clocks used by the switch
>> +- clock-names: the names of the clocks listed in the clocks property
>> + these should be "trgpll", "esw", "gp2", "gp1"
>> +- mt7530-supply: the phandle of the regulator used to power the switch
>> +- mediatek,pctl-regmap: phandle to the port control regmap. this is used to
>> + setup the drive current
>> +
>> +
>> +Optional properties:
>> +- interrupt-parent: Should be the phandle for the interrupt controller
>> + that services interrupts for this device
>> +
>> +Example:
>> +
>> +gsw: switch@1b100000 {
>> + compatible = "mediatek,mt7623-gsw";
>> + reg = <0 0x1b110000 0 0x300000>;
>> +
>> + interrupt-parent = <&pio>;
>> + interrupts = <168 IRQ_TYPE_EDGE_RISING>;
>> +
>> + clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
>> + <ðsys CLK_ETHSYS_ESW>,
>> + <ðsys CLK_ETHSYS_GP2>,
>> + <ðsys CLK_ETHSYS_GP1>;
>> + clock-names = "trgpll", "esw", "gp2", "gp1";
>> +
>> + mt7530-supply = <&mt6323_vpa_reg>;
>> +
>> + mediatek,pctl-regmap = <&syscfg_pctl_a>;
>> + mediatek,reset-pin = <&pio 15 0>;
>> +
>> + status = "okay";
>> +};
>> diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
>> new file mode 100644
>> index 0000000..f8c5747
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
>> @@ -0,0 +1,113 @@
>> +iMEdiatek Frame Engine Ethernet controller
>
> typo?
>
>> +=======================================
>> +
>> +The frame engine ethernet controller can be found on Ralink and Mediatek SoCs
>> +(RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).
>> +
>> +Depending on the SoC, there is a number of ports connected to the CPU port
>> +directly and/or via a (gigabit-)switch. Newer gigabit SoCs can support
>> +a dual MAC setup.
>> +
>> +* Ethernet controller node
>> +
>> +Required properties:
>> +- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
>> + "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
>> + "mediatek,mt7620-eth", "mediatek,mt7621-eth", "mediatek,mt7623-eth"
>
> Do one per line.
>
>> +- reg: Address and length of the register set for the device
>> +- interrupts: Should contain the frame engines interrupt
>> +- mediatek,ethsys: phandle to the syscon node that handles the port setup
>> +
>> +Required properties for ARM based SoCs:
>
> Which ones?
>
>> +- clocks: the clock used by the core
>> +- clock-names: the names of the clock listed in the clocks property
>> +- power-domains: phandle the to power domain that the ethernet is part of
>> +
>> +Optional properties:
>> +- interrupt-parent: Should be the phandle for the interrupt controller
>> + that services interrupts for this device
>> +- mediatek,switch : phandle pointing at the device node of the switch device
>> +
>> +
>> +* Ethernet port node for MT7620
>> +
>> +We need to define which physical port is wired and how it should be setup.
>> +
>> +Required properties:
>> +- compatible: Should be "mediatek,eth-port"
>> +- reg: The number of the physical port
>> +- phy-handle: reference to the node describing the phy
>> +
>> +
>> +* Ethernet MAC node - dual MAC SoCs only
>> +
>> +Required properties:
>> +- compatible: Should be "mediatek,eth-mac"
>> +- reg: The number of the MAC
>> +
>> +
>> +Example for singel MAC SoC:
>
> s/singel/single/
>
>> +
>> +mdio-bus {
>> + status = "okay";
>> +
>> + phy4: ethernet-phy@4 {
>> + reg = <4>;
>> + phy-mode = "rgmii";
>> + };
>> +};
>> +
>> +eth: ethernet@10100000 {
>> + compatible = "mediatek,mt7620-eth";
>> + reg = <0x10100000 10000>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <5>;
>> +
>> + mediatek,switch = <&gsw>;
>> +
>> + port@4 {
>> + status = "okay";
>> + phy-mode = "rgmii";
>> + phy-handle = <&phy4>;
>> + };
>> +};
>> +
>> +
>> +Example for dual MAC SoC:
>> +
>> +eth: ethernet@1b100000 {
>> + compatible = "mediatek,mt7623-eth";
>> + reg = <0 0x1b100000 0 0x10000>;
>> +
>> + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
>> + clock-names = "ethif";
>> +
>> + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
>> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
>> +
>> + mediatek,ethsys = <ðsys>;
>> + mediatek,switch = <&gsw>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + gmac1: mac@0 {
>> + compatible = "mediatek,eth-mac";
>> + reg = <0>;
>> +
>> + status = "okay";
>
> The parent disabled and this enabled doesn't make sense. I'd just drop
> status from examples.
>
>> + };
>> +
>> + gmac2: mac@1 {
>> + compatible = "mediatek,eth-mac";
>> + reg = <1>;
>> +
>> + status = "okay";
>> + };
>> +};
>> --
>> 1.7.10.4
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH V2 02/12] net-next: mediatek: add the drivers core files
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
2016-02-26 14:21 ` [PATCH V2 01/12] net-next: mediatek: Document ralink/mediatek SoC ethernet binding John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 14:21 ` [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW) John Crispin
` (9 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
This patch adds the main chunk of the driver. The ethernet core is used in
all of the Mediatek/Ralink Wireless SoCs. Over the years we have seen
various changes to
* the register layout
* the type of ports (single/dual gbit, internal FE/Gbit switch)
* dma engine (PDMA/QDMA)
and new offloading features were added, such as
* checksum
* VLAN TX/RX
* TSO
* LRO
The core functionality has however remained the same allowing us to use
the same code for all SoCs.
The abstraction for the various SoCs uses the typical ops struct pattern
which allows us to extend or override the core functionality depending on
which SoC we are on. The code to bring up the switches and external ports
has also been split into separate files.
There are 2 types of DMA engine, PDMA and the newer QDMA. PDMA uses a
typical ring buffer while QDMA uses a linked list. Unfortunatley we have
the MT7621 which has a few silicon issues. Due to these issues we need to
PDMA for RX and QDMA for TX. All SoCs newer than the MT7621 can can run on
QDMA exclusively.
Most of the SoCs have a switch frontend. Older silicon has a so called ESW
(Ethernet Switch) while newer cores have a GSW (Gigabit switch).
Additionally there is a MDIO bus that can be used to talk to PHYs. In these
cases one switch port get changed into a normal MAC port.
Some SoCs have a dual MAC, we currently only support this on MT7623.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
drivers/net/ethernet/mediatek/ethtool.c | 223 +++
drivers/net/ethernet/mediatek/ethtool.h | 22 +
drivers/net/ethernet/mediatek/mdio.c | 265 ++++
drivers/net/ethernet/mediatek/mdio.h | 27 +
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2170 +++++++++++++++++++++++++++
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 720 +++++++++
6 files changed, 3427 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/ethtool.c
create mode 100644 drivers/net/ethernet/mediatek/ethtool.h
create mode 100644 drivers/net/ethernet/mediatek/mdio.c
create mode 100644 drivers/net/ethernet/mediatek/mdio.h
create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.c
create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.h
diff --git a/drivers/net/ethernet/mediatek/ethtool.c b/drivers/net/ethernet/mediatek/ethtool.c
new file mode 100644
index 0000000..8c63685
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/ethtool.c
@@ -0,0 +1,223 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include "mtk_eth_soc.h"
+
+static const char mtk_gdma_str[][ETH_GSTRING_LEN] = {
+#define _FE(x...) # x,
+MTK_STAT_REG_DECLARE
+#undef _FE
+};
+
+static int mtk_get_settings(struct net_device *dev,
+ struct ethtool_cmd *cmd)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ int err;
+
+ if (!mac->phy_dev)
+ return -ENODEV;
+
+ if (mac->phy_flags == MTK_PHY_FLAG_ATTACH) {
+ err = phy_read_status(mac->phy_dev);
+ if (err)
+ return -ENODEV;
+ }
+
+ return phy_ethtool_gset(mac->phy_dev, cmd);
+}
+
+static int mtk_set_settings(struct net_device *dev,
+ struct ethtool_cmd *cmd)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+
+ if (!mac->phy_dev)
+ return -ENODEV;
+
+ if (cmd->phy_address != mac->phy_dev->addr) {
+ if (mac->hw->phy->phy_node[cmd->phy_address]) {
+ mac->phy_dev = mac->hw->phy->phy[cmd->phy_address];
+ mac->phy_flags = MTK_PHY_FLAG_PORT;
+ } else if (mac->hw->mii_bus &&
+ mac->hw->mii_bus->phy_map[cmd->phy_address]) {
+ mac->phy_dev =
+ mac->hw->mii_bus->phy_map[cmd->phy_address];
+ mac->phy_flags = MTK_PHY_FLAG_ATTACH;
+ } else {
+ return -ENODEV;
+ }
+ }
+
+ return phy_ethtool_sset(mac->phy_dev, cmd);
+}
+
+static void mtk_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_soc_data *soc = mac->hw->soc;
+
+ strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
+ strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
+
+ if (soc->reg_table[MTK_REG_MTK_COUNTER_BASE])
+ info->n_stats = ARRAY_SIZE(mtk_gdma_str);
+}
+
+static u32 mtk_get_msglevel(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+
+ return mac->hw->msg_enable;
+}
+
+static void mtk_set_msglevel(struct net_device *dev, u32 value)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+
+ mac->hw->msg_enable = value;
+}
+
+static int mtk_nway_reset(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+
+ if (!mac->phy_dev)
+ return -EOPNOTSUPP;
+
+ return genphy_restart_aneg(mac->phy_dev);
+}
+
+static u32 mtk_get_link(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ int err;
+
+ if (!mac->phy_dev)
+ goto out_get_link;
+
+ if (mac->phy_flags == MTK_PHY_FLAG_ATTACH) {
+ err = genphy_update_link(mac->phy_dev);
+ if (err)
+ goto out_get_link;
+ }
+
+ return mac->phy_dev->link;
+
+out_get_link:
+ return ethtool_op_get_link(dev);
+}
+
+static int mtk_set_ringparam(struct net_device *dev,
+ struct ethtool_ringparam *ring)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+
+ if ((ring->tx_pending < 2) ||
+ (ring->rx_pending < 2) ||
+ (ring->rx_pending > mac->hw->soc->dma_ring_size) ||
+ (ring->tx_pending > mac->hw->soc->dma_ring_size))
+ return -EINVAL;
+
+ dev->netdev_ops->ndo_stop(dev);
+
+ mac->hw->tx_ring.tx_ring_size = BIT(fls(ring->tx_pending) - 1);
+ mac->hw->rx_ring[0].rx_ring_size = BIT(fls(ring->rx_pending) - 1);
+
+ return dev->netdev_ops->ndo_open(dev);
+}
+
+static void mtk_get_ringparam(struct net_device *dev,
+ struct ethtool_ringparam *ring)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+
+ ring->rx_max_pending = mac->hw->soc->dma_ring_size;
+ ring->tx_max_pending = mac->hw->soc->dma_ring_size;
+ ring->rx_pending = mac->hw->rx_ring[0].rx_ring_size;
+ ring->tx_pending = mac->hw->tx_ring.tx_ring_size;
+}
+
+static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
+{
+ switch (stringset) {
+ case ETH_SS_STATS:
+ memcpy(data, *mtk_gdma_str, sizeof(mtk_gdma_str));
+ break;
+ }
+}
+
+static int mtk_get_sset_count(struct net_device *dev, int sset)
+{
+ switch (sset) {
+ case ETH_SS_STATS:
+ return ARRAY_SIZE(mtk_gdma_str);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static void mtk_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *stats, u64 *data)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_hw_stats *hwstats = mac->hw_stats;
+ u64 *data_src, *data_dst;
+ unsigned int start;
+ int i;
+
+ if (netif_running(dev) && netif_device_present(dev)) {
+ if (spin_trylock(&hwstats->stats_lock)) {
+ mtk_stats_update_mac(mac);
+ spin_unlock(&hwstats->stats_lock);
+ }
+ }
+
+ do {
+ data_src = &hwstats->tx_bytes;
+ data_dst = data;
+ start = u64_stats_fetch_begin_irq(&hwstats->syncp);
+
+ for (i = 0; i < ARRAY_SIZE(mtk_gdma_str); i++)
+ *data_dst++ = *data_src++;
+
+ } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
+}
+
+static struct ethtool_ops mtk_ethtool_ops = {
+ .get_settings = mtk_get_settings,
+ .set_settings = mtk_set_settings,
+ .get_drvinfo = mtk_get_drvinfo,
+ .get_msglevel = mtk_get_msglevel,
+ .set_msglevel = mtk_set_msglevel,
+ .nway_reset = mtk_nway_reset,
+ .get_link = mtk_get_link,
+ .set_ringparam = mtk_set_ringparam,
+ .get_ringparam = mtk_get_ringparam,
+};
+
+void mtk_set_ethtool_ops(struct net_device *netdev)
+{
+ struct mtk_mac *mac = netdev_priv(netdev);
+ struct mtk_soc_data *soc = mac->hw->soc;
+
+ if (soc->reg_table[MTK_REG_MTK_COUNTER_BASE]) {
+ mtk_ethtool_ops.get_strings = mtk_get_strings;
+ mtk_ethtool_ops.get_sset_count = mtk_get_sset_count;
+ mtk_ethtool_ops.get_ethtool_stats = mtk_get_ethtool_stats;
+ }
+
+ netdev->ethtool_ops = &mtk_ethtool_ops;
+}
diff --git a/drivers/net/ethernet/mediatek/ethtool.h b/drivers/net/ethernet/mediatek/ethtool.h
new file mode 100644
index 0000000..40b4cf0
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/ethtool.h
@@ -0,0 +1,22 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef MTK_ETHTOOL_H
+#define MTK_ETHTOOL_H
+
+#include <linux/ethtool.h>
+
+void mtk_set_ethtool_ops(struct net_device *netdev);
+
+#endif /* MTK_ETHTOOL_H */
diff --git a/drivers/net/ethernet/mediatek/mdio.c b/drivers/net/ethernet/mediatek/mdio.c
new file mode 100644
index 0000000..f3f73f0
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mdio.c
@@ -0,0 +1,265 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/phy.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio.h"
+
+static int mtk_mdio_reset(struct mii_bus *bus)
+{
+ /* TODO */
+ return 0;
+}
+
+static void mtk_phy_link_adjust(struct net_device *dev)
+{
+ struct mtk_eth *eth = netdev_priv(dev);
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(ð->phy->lock, flags);
+ for (i = 0; i < 8; i++) {
+ if (eth->phy->phy_node[i]) {
+ struct phy_device *phydev = eth->phy->phy[i];
+ int status_change = 0;
+
+ if (phydev->link)
+ if (eth->phy->duplex[i] != phydev->duplex ||
+ eth->phy->speed[i] != phydev->speed)
+ status_change = 1;
+
+ if (phydev->link != eth->link[i])
+ status_change = 1;
+
+ switch (phydev->speed) {
+ case SPEED_1000:
+ case SPEED_100:
+ case SPEED_10:
+ eth->link[i] = phydev->link;
+ eth->phy->duplex[i] = phydev->duplex;
+ eth->phy->speed[i] = phydev->speed;
+
+ if (status_change &&
+ eth->soc->mdio_adjust_link)
+ eth->soc->mdio_adjust_link(eth, i);
+ break;
+ }
+ }
+ }
+}
+
+int mtk_connect_phy_node(struct mtk_eth *eth, struct mtk_mac *mac,
+ struct device_node *phy_node)
+{
+ const __be32 *_port = NULL;
+ struct phy_device *phydev;
+ int phy_mode, port;
+
+ _port = of_get_property(phy_node, "reg", NULL);
+
+ if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
+ pr_err("%s: invalid port id\n", phy_node->name);
+ return -EINVAL;
+ }
+ port = be32_to_cpu(*_port);
+ phy_mode = of_get_phy_mode(phy_node);
+ if (phy_mode < 0) {
+ dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
+ eth->phy->phy_node[port] = NULL;
+ return -EINVAL;
+ }
+
+ phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
+ mtk_phy_link_adjust, 0, phy_mode);
+ if (IS_ERR(phydev)) {
+ dev_err(eth->dev, "could not connect to PHY\n");
+ eth->phy->phy_node[port] = NULL;
+ return PTR_ERR(phydev);
+ }
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ phydev->advertising = phydev->supported;
+
+ dev_info(eth->dev,
+ "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
+ port, dev_name(&phydev->dev), phydev->phy_id,
+ phydev->drv->name);
+
+ eth->phy->phy[port] = phydev;
+ eth->link[port] = 0;
+
+ return 0;
+}
+
+static void phy_init(struct mtk_eth *eth, struct mtk_mac *mac,
+ struct phy_device *phy)
+{
+ phy_attach(eth->netdev[mac->id], dev_name(&phy->dev),
+ PHY_INTERFACE_MODE_MII);
+
+ phy->autoneg = AUTONEG_ENABLE;
+ phy->speed = 0;
+ phy->duplex = 0;
+ phy->supported &= PHY_BASIC_FEATURES;
+ phy->advertising = phy->supported | ADVERTISED_Autoneg;
+
+ phy_start_aneg(phy);
+}
+
+static int mtk_phy_connect(struct mtk_mac *mac)
+{
+ struct mtk_eth *eth = mac->hw;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (eth->phy->phy_node[i]) {
+ if (!mac->phy_dev) {
+ mac->phy_dev = eth->phy->phy[i];
+ mac->phy_flags = MTK_PHY_FLAG_PORT;
+ }
+ } else if (eth->mii_bus && eth->mii_bus->phy_map[i]) {
+ phy_init(eth, mac, eth->mii_bus->phy_map[i]);
+ if (!mac->phy_dev) {
+ mac->phy_dev = eth->mii_bus->phy_map[i];
+ mac->phy_flags = MTK_PHY_FLAG_ATTACH;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static void mtk_phy_disconnect(struct mtk_mac *mac)
+{
+ struct mtk_eth *eth = mac->hw;
+ unsigned long flags;
+ int i;
+
+ for (i = 0; i < 8; i++)
+ if (eth->phy->phy_fixed[i]) {
+ spin_lock_irqsave(ð->phy->lock, flags);
+ eth->link[i] = 0;
+ if (eth->soc->mdio_adjust_link)
+ eth->soc->mdio_adjust_link(eth, i);
+ spin_unlock_irqrestore(ð->phy->lock, flags);
+ } else if (eth->phy->phy[i]) {
+ phy_disconnect(eth->phy->phy[i]);
+ } else if (eth->mii_bus && eth->mii_bus->phy_map[i]) {
+ phy_detach(eth->mii_bus->phy_map[i]);
+ }
+}
+
+static void mtk_phy_start(struct mtk_mac *mac)
+{
+ struct mtk_eth *eth = mac->hw;
+ unsigned long flags;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (eth->phy->phy_fixed[i]) {
+ spin_lock_irqsave(ð->phy->lock, flags);
+ eth->link[i] = 1;
+ if (eth->soc->mdio_adjust_link)
+ eth->soc->mdio_adjust_link(eth, i);
+ spin_unlock_irqrestore(ð->phy->lock, flags);
+ } else if (eth->phy->phy[i]) {
+ phy_start(eth->phy->phy[i]);
+ }
+ }
+}
+
+static void mtk_phy_stop(struct mtk_mac *mac)
+{
+ struct mtk_eth *eth = mac->hw;
+ unsigned long flags;
+ int i;
+
+ for (i = 0; i < 8; i++)
+ if (eth->phy->phy_fixed[i]) {
+ spin_lock_irqsave(ð->phy->lock, flags);
+ eth->link[i] = 0;
+ if (eth->soc->mdio_adjust_link)
+ eth->soc->mdio_adjust_link(eth, i);
+ spin_unlock_irqrestore(ð->phy->lock, flags);
+ } else if (eth->phy->phy[i]) {
+ phy_stop(eth->phy->phy[i]);
+ }
+}
+
+static struct mtk_phy phy_ralink = {
+ .connect = mtk_phy_connect,
+ .disconnect = mtk_phy_disconnect,
+ .start = mtk_phy_start,
+ .stop = mtk_phy_stop,
+};
+
+int mtk_mdio_init(struct mtk_eth *eth)
+{
+ struct device_node *mii_np;
+ int err;
+
+ if (!eth->soc->mdio_read || !eth->soc->mdio_write)
+ return 0;
+
+ spin_lock_init(&phy_ralink.lock);
+ eth->phy = &phy_ralink;
+
+ mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
+ if (!mii_np) {
+ dev_err(eth->dev, "no %s child node found", "mdio-bus");
+ return -ENODEV;
+ }
+
+ if (!of_device_is_available(mii_np)) {
+ err = 0;
+ goto err_put_node;
+ }
+
+ eth->mii_bus = mdiobus_alloc();
+ if (!eth->mii_bus) {
+ err = -ENOMEM;
+ goto err_put_node;
+ }
+
+ eth->mii_bus->name = "mdio";
+ eth->mii_bus->read = eth->soc->mdio_read;
+ eth->mii_bus->write = eth->soc->mdio_write;
+ eth->mii_bus->reset = mtk_mdio_reset;
+ eth->mii_bus->priv = eth;
+ eth->mii_bus->parent = eth->dev;
+
+ snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
+ err = of_mdiobus_register(eth->mii_bus, mii_np);
+ if (err)
+ goto err_free_bus;
+
+ return 0;
+
+err_free_bus:
+ kfree(eth->mii_bus);
+err_put_node:
+ of_node_put(mii_np);
+ eth->mii_bus = NULL;
+ return err;
+}
+
+void mtk_mdio_cleanup(struct mtk_eth *eth)
+{
+ if (!eth->mii_bus)
+ return;
+
+ mdiobus_unregister(eth->mii_bus);
+ of_node_put(eth->mii_bus->dev.of_node);
+ kfree(eth->mii_bus);
+}
diff --git a/drivers/net/ethernet/mediatek/mdio.h b/drivers/net/ethernet/mediatek/mdio.h
new file mode 100644
index 0000000..b14e238
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mdio.h
@@ -0,0 +1,27 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_MDIO_H__
+#define _RALINK_MDIO_H__
+
+#ifdef CONFIG_NET_MEDIATEK_MDIO
+int mtk_mdio_init(struct mtk_eth *eth);
+void mtk_mdio_cleanup(struct mtk_eth *eth);
+int mtk_connect_phy_node(struct mtk_eth *eth, struct mtk_mac *mac,
+ struct device_node *phy_node);
+#else
+static inline int mtk_mdio_init(struct mtk_eth *eth) { return 0; }
+static inline void mtk_mdio_cleanup(struct mtk_eth *eth) {}
+#endif
+#endif
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
new file mode 100644
index 0000000..079cf8b
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -0,0 +1,2170 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/skbuff.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/clk.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+#include <linux/if_vlan.h>
+#include <linux/reset.h>
+#include <linux/tcp.h>
+#include <linux/io.h>
+#include <linux/bug.h>
+#include <linux/regmap.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio.h"
+#include "ethtool.h"
+
+#define MAX_RX_LENGTH 1536
+#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
+#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
+#define DMA_DUMMY_DESC 0xffffffff
+#define MTK_DEFAULT_MSG_ENABLE \
+ (NETIF_MSG_DRV | \
+ NETIF_MSG_PROBE | \
+ NETIF_MSG_LINK | \
+ NETIF_MSG_TIMER | \
+ NETIF_MSG_IFDOWN | \
+ NETIF_MSG_IFUP | \
+ NETIF_MSG_RX_ERR | \
+ NETIF_MSG_TX_ERR)
+
+#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
+#define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
+#define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
+
+#define SYSC_REG_RSTCTRL 0x34
+
+static int mtk_msg_level = -1;
+module_param_named(msg_level, mtk_msg_level, int, 0);
+MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
+
+static const u16 mtk_reg_table_default[MTK_REG_COUNT] = {
+ [MTK_REG_PDMA_GLO_CFG] = MTK_PDMA_GLO_CFG,
+ [MTK_REG_PDMA_RST_CFG] = MTK_PDMA_RST_CFG,
+ [MTK_REG_DLY_INT_CFG] = MTK_DLY_INT_CFG,
+ [MTK_REG_TX_BASE_PTR0] = MTK_TX_BASE_PTR0,
+ [MTK_REG_TX_MAX_CNT0] = MTK_TX_MAX_CNT0,
+ [MTK_REG_TX_CTX_IDX0] = MTK_TX_CTX_IDX0,
+ [MTK_REG_TX_DTX_IDX0] = MTK_TX_DTX_IDX0,
+ [MTK_REG_RX_BASE_PTR0] = MTK_RX_BASE_PTR0,
+ [MTK_REG_RX_MAX_CNT0] = MTK_RX_MAX_CNT0,
+ [MTK_REG_RX_CALC_IDX0] = MTK_RX_CALC_IDX0,
+ [MTK_REG_RX_DRX_IDX0] = MTK_RX_DRX_IDX0,
+ [MTK_REG_MTK_INT_ENABLE] = MTK_INT_ENABLE,
+ [MTK_REG_MTK_INT_STATUS] = MTK_INT_STATUS,
+ [MTK_REG_MTK_DMA_VID_BASE] = MTK_DMA_VID0,
+ [MTK_REG_MTK_COUNTER_BASE] = MTK_GDMA1_TX_GBCNT,
+ [MTK_REG_MTK_RST_GL] = MTK_RST_GL,
+};
+
+static const u16 *mtk_reg_table = mtk_reg_table_default;
+
+void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
+{
+ __raw_writel(val, eth->base + reg);
+}
+
+u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
+{
+ return __raw_readl(eth->base + reg);
+}
+
+static void mtk_reg_w32(struct mtk_eth *eth, u32 val, enum mtk_reg reg)
+{
+ mtk_w32(eth, val, mtk_reg_table[reg]);
+}
+
+static u32 mtk_reg_r32(struct mtk_eth *eth, enum mtk_reg reg)
+{
+ return mtk_r32(eth, mtk_reg_table[reg]);
+}
+
+/* these bits are also exposed via the reset-controller API. however the switch
+ * and FE need to be brought out of reset in the exakt same moemtn and the
+ * reset-controller api does not provide this feature yet. Do the reset manually
+ * until we fixed the reset-controller api to be able to do this
+ */
+void mtk_reset(struct mtk_eth *eth, u32 reset_bits)
+{
+ u32 val;
+
+ regmap_read(eth->ethsys, SYSC_REG_RSTCTRL, &val);
+ val |= reset_bits;
+ regmap_write(eth->ethsys, SYSC_REG_RSTCTRL, val);
+ usleep_range(10, 20);
+ val &= ~reset_bits;
+ regmap_write(eth->ethsys, SYSC_REG_RSTCTRL, val);
+ usleep_range(10, 20);
+}
+
+static inline void mtk_irq_ack(struct mtk_eth *eth, u32 mask)
+{
+ if (eth->soc->dma_type & MTK_PDMA)
+ mtk_reg_w32(eth, mask, MTK_REG_MTK_INT_STATUS);
+ if (eth->soc->dma_type & MTK_QDMA)
+ mtk_w32(eth, mask, MTK_QMTK_INT_STATUS);
+}
+
+static inline u32 mtk_irq_pending(struct mtk_eth *eth)
+{
+ u32 status = 0;
+
+ if (eth->soc->dma_type & MTK_PDMA)
+ status |= mtk_reg_r32(eth, MTK_REG_MTK_INT_STATUS);
+ if (eth->soc->dma_type & MTK_QDMA)
+ status |= mtk_r32(eth, MTK_QMTK_INT_STATUS);
+
+ return status;
+}
+
+static void mtk_irq_ack_status(struct mtk_eth *eth, u32 mask)
+{
+ u32 status_reg = MTK_REG_MTK_INT_STATUS;
+
+ if (mtk_reg_table[MTK_REG_MTK_INT_STATUS2])
+ status_reg = MTK_REG_MTK_INT_STATUS2;
+
+ mtk_reg_w32(eth, mask, status_reg);
+}
+
+static u32 mtk_irq_pending_status(struct mtk_eth *eth)
+{
+ u32 status_reg = MTK_REG_MTK_INT_STATUS;
+
+ if (mtk_reg_table[MTK_REG_MTK_INT_STATUS2])
+ status_reg = MTK_REG_MTK_INT_STATUS2;
+
+ return mtk_reg_r32(eth, status_reg);
+}
+
+static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
+{
+ u32 val;
+
+ if (eth->soc->dma_type & MTK_PDMA) {
+ val = mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
+ mtk_reg_w32(eth, val & ~mask, MTK_REG_MTK_INT_ENABLE);
+ /* flush write */
+ mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
+ }
+ if (eth->soc->dma_type & MTK_QDMA) {
+ val = mtk_r32(eth, MTK_QMTK_INT_ENABLE);
+ mtk_w32(eth, val & ~mask, MTK_QMTK_INT_ENABLE);
+ /* flush write */
+ mtk_r32(eth, MTK_QMTK_INT_ENABLE);
+ }
+}
+
+static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
+{
+ u32 val;
+
+ if (eth->soc->dma_type & MTK_PDMA) {
+ val = mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
+ mtk_reg_w32(eth, val | mask, MTK_REG_MTK_INT_ENABLE);
+ /* flush write */
+ mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
+ }
+ if (eth->soc->dma_type & MTK_QDMA) {
+ val = mtk_r32(eth, MTK_QMTK_INT_ENABLE);
+ mtk_w32(eth, val | mask, MTK_QMTK_INT_ENABLE);
+ /* flush write */
+ mtk_r32(eth, MTK_QMTK_INT_ENABLE);
+ }
+}
+
+static inline u32 mtk_irq_enabled(struct mtk_eth *eth)
+{
+ u32 enabled = 0;
+
+ if (eth->soc->dma_type & MTK_PDMA)
+ enabled |= mtk_reg_r32(eth, MTK_REG_MTK_INT_ENABLE);
+ if (eth->soc->dma_type & MTK_QDMA)
+ enabled |= mtk_r32(eth, MTK_QMTK_INT_ENABLE);
+
+ return enabled;
+}
+
+static inline void mtk_hw_set_macaddr(struct mtk_mac *mac,
+ unsigned char *macaddr)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mac->hw->page_lock, flags);
+ mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], MTK_GDMA1_MAC_ADRH);
+ mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
+ (macaddr[4] << 8) | macaddr[5],
+ MTK_GDMA1_MAC_ADRL);
+ spin_unlock_irqrestore(&mac->hw->page_lock, flags);
+}
+
+static int mtk_set_mac_address(struct net_device *dev, void *p)
+{
+ int ret = eth_mac_addr(dev, p);
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+
+ if (ret)
+ return ret;
+
+ if (eth->soc->set_mac)
+ eth->soc->set_mac(mac, dev->dev_addr);
+ else
+ mtk_hw_set_macaddr(mac, p);
+
+ return 0;
+}
+
+static inline int mtk_max_frag_size(int mtu)
+{
+ /* make sure buf_size will be at least MAX_RX_LENGTH */
+ if (mtu + MTK_RX_ETH_HLEN < MAX_RX_LENGTH)
+ mtu = MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
+
+ return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
+}
+
+static inline int mtk_max_buf_size(int frag_size)
+{
+ int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
+
+ WARN_ON(buf_size < MAX_RX_LENGTH);
+
+ return buf_size;
+}
+
+static inline void mtk_get_rxd(struct mtk_rx_dma *rxd,
+ struct mtk_rx_dma *dma_rxd)
+{
+ rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
+ rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
+ rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
+ rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
+}
+
+static inline void mtk_set_txd_pdma(struct mtk_tx_dma *txd,
+ struct mtk_tx_dma *dma_txd)
+{
+ WRITE_ONCE(dma_txd->txd1, txd->txd1);
+ WRITE_ONCE(dma_txd->txd3, txd->txd3);
+ WRITE_ONCE(dma_txd->txd4, txd->txd4);
+ /* clean dma done flag last */
+ WRITE_ONCE(dma_txd->txd2, txd->txd2);
+}
+
+static void mtk_clean_rx(struct mtk_eth *eth, struct mtk_rx_ring *ring)
+{
+ int i;
+
+ if (ring->rx_data && ring->rx_dma) {
+ for (i = 0; i < ring->rx_ring_size; i++) {
+ if (!ring->rx_data[i])
+ continue;
+ if (!ring->rx_dma[i].rxd1)
+ continue;
+ dma_unmap_single(eth->dev,
+ ring->rx_dma[i].rxd1,
+ ring->rx_buf_size,
+ DMA_FROM_DEVICE);
+ skb_free_frag(ring->rx_data[i]);
+ }
+ kfree(ring->rx_data);
+ ring->rx_data = NULL;
+ }
+
+ if (ring->rx_dma) {
+ dma_free_coherent(eth->dev,
+ ring->rx_ring_size * sizeof(*ring->rx_dma),
+ ring->rx_dma,
+ ring->rx_phys);
+ ring->rx_dma = NULL;
+ }
+}
+
+static int mtk_dma_rx_alloc(struct mtk_eth *eth, struct mtk_rx_ring *ring)
+{
+ int i, pad = 0;
+
+ ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
+ ring->rx_buf_size = mtk_max_buf_size(ring->frag_size);
+ ring->rx_ring_size = eth->soc->dma_ring_size;
+ ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
+ GFP_KERNEL);
+ if (!ring->rx_data)
+ goto no_rx_mem;
+
+ for (i = 0; i < ring->rx_ring_size; i++) {
+ ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
+ if (!ring->rx_data[i])
+ goto no_rx_mem;
+ }
+
+ ring->rx_dma = dma_alloc_coherent(eth->dev,
+ ring->rx_ring_size * sizeof(*ring->rx_dma),
+ &ring->rx_phys,
+ GFP_ATOMIC | __GFP_ZERO);
+ if (!ring->rx_dma)
+ goto no_rx_mem;
+
+ if (!eth->soc->rx_2b_offset)
+ pad = NET_IP_ALIGN;
+
+ for (i = 0; i < ring->rx_ring_size; i++) {
+ dma_addr_t dma_addr = dma_map_single(eth->dev,
+ ring->rx_data[i] + NET_SKB_PAD + pad,
+ ring->rx_buf_size,
+ DMA_FROM_DEVICE);
+ if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
+ goto no_rx_mem;
+ ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
+
+ if (eth->soc->rx_sg_dma)
+ ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
+ else
+ ring->rx_dma[i].rxd2 = RX_DMA_LSO;
+ }
+ ring->rx_calc_idx = ring->rx_ring_size - 1;
+ /* make sure that all changes to the dma ring are flushed before we
+ * continue
+ */
+ wmb();
+
+ return 0;
+
+no_rx_mem:
+ return -ENOMEM;
+}
+
+static void mtk_txd_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
+{
+ if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
+ dma_unmap_single(dev,
+ dma_unmap_addr(tx_buf, dma_addr0),
+ dma_unmap_len(tx_buf, dma_len0),
+ DMA_TO_DEVICE);
+ } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
+ dma_unmap_page(dev,
+ dma_unmap_addr(tx_buf, dma_addr0),
+ dma_unmap_len(tx_buf, dma_len0),
+ DMA_TO_DEVICE);
+ }
+ if (tx_buf->flags & MTK_TX_FLAGS_PAGE1)
+ dma_unmap_page(dev,
+ dma_unmap_addr(tx_buf, dma_addr1),
+ dma_unmap_len(tx_buf, dma_len1),
+ DMA_TO_DEVICE);
+
+ tx_buf->flags = 0;
+ if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
+ dev_kfree_skb_any(tx_buf->skb);
+ tx_buf->skb = NULL;
+}
+
+static void mtk_pdma_tx_clean(struct mtk_eth *eth)
+{
+ struct mtk_tx_ring *ring = ð->tx_ring;
+ int i;
+
+ if (ring->tx_buf) {
+ for (i = 0; i < ring->tx_ring_size; i++)
+ mtk_txd_unmap(eth->dev, &ring->tx_buf[i]);
+ kfree(ring->tx_buf);
+ ring->tx_buf = NULL;
+ }
+
+ if (ring->tx_dma) {
+ dma_free_coherent(eth->dev,
+ ring->tx_ring_size * sizeof(*ring->tx_dma),
+ ring->tx_dma,
+ ring->tx_phys);
+ ring->tx_dma = NULL;
+ }
+}
+
+static void mtk_qdma_tx_clean(struct mtk_eth *eth)
+{
+ struct mtk_tx_ring *ring = ð->tx_ring;
+ int i;
+
+ if (ring->tx_buf) {
+ for (i = 0; i < ring->tx_ring_size; i++)
+ mtk_txd_unmap(eth->dev, &ring->tx_buf[i]);
+ kfree(ring->tx_buf);
+ ring->tx_buf = NULL;
+ }
+
+ if (ring->tx_dma) {
+ dma_free_coherent(eth->dev,
+ ring->tx_ring_size * sizeof(*ring->tx_dma),
+ ring->tx_dma,
+ ring->tx_phys);
+ ring->tx_dma = NULL;
+ }
+}
+
+void mtk_stats_update_mac(struct mtk_mac *mac)
+{
+ struct mtk_hw_stats *hw_stats = mac->hw_stats;
+ unsigned int base = mtk_reg_table[MTK_REG_MTK_COUNTER_BASE];
+ u64 stats;
+
+ base += hw_stats->reg_offset;
+
+ u64_stats_update_begin(&hw_stats->syncp);
+
+ if (mac->hw->soc->new_stats) {
+ hw_stats->rx_bytes += mtk_r32(mac->hw, base);
+ stats = mtk_r32(mac->hw, base + 0x04);
+ if (stats)
+ hw_stats->rx_bytes += (stats << 32);
+ hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
+ hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
+ hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
+ hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
+ hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
+ hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
+ hw_stats->rx_flow_control_packets +=
+ mtk_r32(mac->hw, base + 0x24);
+ hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
+ hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
+ hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
+ stats = mtk_r32(mac->hw, base + 0x34);
+ if (stats)
+ hw_stats->tx_bytes += (stats << 32);
+ hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
+ } else {
+ hw_stats->tx_bytes += mtk_r32(mac->hw, base);
+ hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x04);
+ hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x08);
+ hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x0c);
+ hw_stats->rx_bytes += mtk_r32(mac->hw, base + 0x20);
+ hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x24);
+ hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x28);
+ hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x2c);
+ hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x30);
+ hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x34);
+ hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x38);
+ hw_stats->rx_flow_control_packets +=
+ mtk_r32(mac->hw, base + 0x3c);
+ }
+
+ u64_stats_update_end(&hw_stats->syncp);
+}
+
+static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
+ struct rtnl_link_stats64 *storage)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_hw_stats *hw_stats = mac->hw_stats;
+ unsigned int base = mtk_reg_table[MTK_REG_MTK_COUNTER_BASE];
+ unsigned int start;
+
+ if (!base) {
+ netdev_stats_to_stats64(storage, &dev->stats);
+ return storage;
+ }
+
+ if (netif_running(dev) && netif_device_present(dev)) {
+ if (spin_trylock(&hw_stats->stats_lock)) {
+ mtk_stats_update_mac(mac);
+ spin_unlock(&hw_stats->stats_lock);
+ }
+ }
+
+ do {
+ start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
+ storage->rx_packets = hw_stats->rx_packets;
+ storage->tx_packets = hw_stats->tx_packets;
+ storage->rx_bytes = hw_stats->rx_bytes;
+ storage->tx_bytes = hw_stats->tx_bytes;
+ storage->collisions = hw_stats->tx_collisions;
+ storage->rx_length_errors = hw_stats->rx_short_errors +
+ hw_stats->rx_long_errors;
+ storage->rx_over_errors = hw_stats->rx_overflow;
+ storage->rx_crc_errors = hw_stats->rx_fcs_errors;
+ storage->rx_errors = hw_stats->rx_checksum_errors;
+ storage->tx_aborted_errors = hw_stats->tx_skip;
+ } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
+
+ storage->tx_errors = dev->stats.tx_errors;
+ storage->rx_dropped = dev->stats.rx_dropped;
+ storage->tx_dropped = dev->stats.tx_dropped;
+
+ return storage;
+}
+
+static int mtk_vlan_rx_add_vid(struct net_device *dev,
+ __be16 proto, u16 vid)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ u32 idx = (vid & 0xf);
+ u32 vlan_cfg;
+
+ if (!((mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE]) &&
+ (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
+ return 0;
+
+ if (test_bit(idx, ð->vlan_map)) {
+ netdev_warn(dev, "disable tx vlan offload\n");
+ dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
+ netdev_update_features(dev);
+ } else {
+ vlan_cfg = mtk_r32(eth,
+ mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
+ ((idx >> 1) << 2));
+ if (idx & 0x1) {
+ vlan_cfg &= 0xffff;
+ vlan_cfg |= (vid << 16);
+ } else {
+ vlan_cfg &= 0xffff0000;
+ vlan_cfg |= vid;
+ }
+ mtk_w32(eth,
+ vlan_cfg, mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
+ ((idx >> 1) << 2));
+ set_bit(idx, ð->vlan_map);
+ }
+
+ return 0;
+}
+
+static int mtk_vlan_rx_kill_vid(struct net_device *dev,
+ __be16 proto, u16 vid)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ u32 idx = (vid & 0xf);
+
+ if (!((mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE]) &&
+ (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
+ return 0;
+
+ clear_bit(idx, ð->vlan_map);
+
+ return 0;
+}
+
+static inline u32 mtk_pdma_empty_txd(struct mtk_tx_ring *ring)
+{
+ barrier();
+ return (u32)(ring->tx_ring_size -
+ ((ring->tx_next_idx - ring->tx_free_idx) &
+ (ring->tx_ring_size - 1)));
+}
+
+static int mtk_skb_padto(struct sk_buff *skb, struct mtk_eth *eth)
+{
+ unsigned int len;
+ int ret;
+
+ if (unlikely(skb->len >= VLAN_ETH_ZLEN))
+ return 0;
+
+ if (eth->soc->padding_64b && !eth->soc->padding_bug)
+ return 0;
+
+ if (skb_vlan_tag_present(skb))
+ len = ETH_ZLEN;
+ else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
+ len = VLAN_ETH_ZLEN;
+ else if (!eth->soc->padding_64b)
+ len = ETH_ZLEN;
+ else
+ return 0;
+
+ if (skb->len >= len)
+ return 0;
+
+ ret = skb_pad(skb, len - skb->len);
+ if (ret < 0)
+ return ret;
+ skb->len = len;
+ skb_set_tail_pointer(skb, len);
+
+ return ret;
+}
+
+static int mtk_pdma_tx_map(struct sk_buff *skb, struct net_device *dev,
+ int tx_num, struct mtk_tx_ring *ring, bool gso)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ struct skb_frag_struct *frag;
+ struct mtk_tx_dma txd, *ptxd;
+ struct mtk_tx_buf *tx_buf;
+ int i, j, k, frag_size, frag_map_size, offset;
+ dma_addr_t mapped_addr;
+ unsigned int nr_frags;
+ u32 def_txd4;
+
+ if (mtk_skb_padto(skb, eth)) {
+ netif_warn(eth, tx_err, dev, "tx padding failed!\n");
+ return -1;
+ }
+
+ tx_buf = &ring->tx_buf[ring->tx_next_idx];
+ memset(tx_buf, 0, sizeof(*tx_buf));
+ memset(&txd, 0, sizeof(txd));
+ nr_frags = skb_shinfo(skb)->nr_frags;
+
+ /* init tx descriptor */
+ def_txd4 = eth->soc->txd4;
+ txd.txd4 = def_txd4;
+
+ /* TX Checksum offload */
+ if (skb->ip_summed == CHECKSUM_PARTIAL)
+ txd.txd4 |= TX_DMA_CHKSUM;
+
+ /* VLAN header offload */
+ if (skb_vlan_tag_present(skb)) {
+ u16 tag = skb_vlan_tag_get(skb);
+
+ txd.txd4 |= TX_DMA_INS_VLAN |
+ ((tag >> VLAN_PRIO_SHIFT) << 4) |
+ (tag & 0xF);
+ }
+
+ mapped_addr = dma_map_single(&dev->dev, skb->data,
+ skb_headlen(skb), DMA_TO_DEVICE);
+ if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
+ return -1;
+
+ txd.txd1 = mapped_addr;
+ txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
+
+ tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
+ dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
+ dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
+
+ /* TX SG offload */
+ j = ring->tx_next_idx;
+ k = 0;
+ for (i = 0; i < nr_frags; i++) {
+ offset = 0;
+ frag = &skb_shinfo(skb)->frags[i];
+ frag_size = skb_frag_size(frag);
+
+ while (frag_size > 0) {
+ frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
+ mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
+ frag_map_size,
+ DMA_TO_DEVICE);
+ if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
+ goto err_dma;
+
+ if (k & 0x1) {
+ j = NEXT_TX_DESP_IDX(j);
+ txd.txd1 = mapped_addr;
+ txd.txd2 = TX_DMA_PLEN0(frag_map_size);
+ txd.txd4 = def_txd4;
+
+ tx_buf = &ring->tx_buf[j];
+ memset(tx_buf, 0, sizeof(*tx_buf));
+
+ tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
+ dma_unmap_addr_set(tx_buf, dma_addr0,
+ mapped_addr);
+ dma_unmap_len_set(tx_buf, dma_len0,
+ frag_map_size);
+ } else {
+ txd.txd3 = mapped_addr;
+ txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
+
+ tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
+ tx_buf->flags |= MTK_TX_FLAGS_PAGE1;
+ dma_unmap_addr_set(tx_buf, dma_addr1,
+ mapped_addr);
+ dma_unmap_len_set(tx_buf, dma_len1,
+ frag_map_size);
+
+ if (!((i == (nr_frags - 1)) &&
+ (frag_map_size == frag_size))) {
+ mtk_set_txd_pdma(&txd,
+ &ring->tx_dma[j]);
+ memset(&txd, 0, sizeof(txd));
+ }
+ }
+ frag_size -= frag_map_size;
+ offset += frag_map_size;
+ k++;
+ }
+ }
+
+ /* set last segment */
+ if (k & 0x1)
+ txd.txd2 |= TX_DMA_LS1;
+ else
+ txd.txd2 |= TX_DMA_LS0;
+ mtk_set_txd_pdma(&txd, &ring->tx_dma[j]);
+
+ /* store skb to cleanup */
+ tx_buf->skb = skb;
+
+ netdev_sent_queue(dev, skb->len);
+ skb_tx_timestamp(skb);
+
+ ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
+ /* make sure that all changes to the dma ring are flushed before we
+ * continue
+ */
+ wmb();
+ atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
+
+ if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
+ mtk_reg_w32(eth, ring->tx_next_idx, MTK_REG_TX_CTX_IDX0);
+
+ return 0;
+
+err_dma:
+ j = ring->tx_next_idx;
+ for (i = 0; i < tx_num; i++) {
+ ptxd = &ring->tx_dma[j];
+ tx_buf = &ring->tx_buf[j];
+
+ /* unmap dma */
+ mtk_txd_unmap(&dev->dev, tx_buf);
+
+ ptxd->txd2 = TX_DMA_DESP2_DEF;
+ j = NEXT_TX_DESP_IDX(j);
+ }
+ /* make sure that all changes to the dma ring are flushed before we
+ * continue
+ */
+ wmb();
+ return -1;
+}
+
+/* the qdma core needs scratch memory to be setup */
+static int mtk_init_fq_dma(struct mtk_eth *eth)
+{
+ unsigned int phy_ring_head, phy_ring_tail;
+ int cnt = eth->soc->dma_ring_size;
+ dma_addr_t dma_addr;
+ int i;
+
+ eth->scratch_ring = dma_alloc_coherent(eth->dev,
+ cnt * sizeof(struct mtk_tx_dma),
+ &phy_ring_head,
+ GFP_ATOMIC | __GFP_ZERO);
+ if (unlikely(!eth->scratch_ring))
+ return -ENOMEM;
+
+ eth->scratch_head = kcalloc(cnt, QDMA_PAGE_SIZE,
+ GFP_KERNEL);
+ dma_addr = dma_map_single(eth->dev,
+ eth->scratch_head, cnt * QDMA_PAGE_SIZE,
+ DMA_FROM_DEVICE);
+ if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
+ return -ENOMEM;
+
+ memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
+ phy_ring_tail = phy_ring_head + (sizeof(struct mtk_tx_dma) * (cnt - 1));
+
+ for (i = 0; i < cnt; i++) {
+ eth->scratch_ring[i].txd1 = (dma_addr + (i * QDMA_PAGE_SIZE));
+ if (i < cnt - 1)
+ eth->scratch_ring[i].txd2 = (phy_ring_head +
+ ((i + 1) * sizeof(struct mtk_tx_dma)));
+ eth->scratch_ring[i].txd3 = TX_QDMA_SDL(QDMA_PAGE_SIZE);
+ }
+
+ mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD);
+ mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
+ mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
+ mtk_w32(eth, QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
+
+ return 0;
+}
+
+static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
+{
+ void *ret = ring->tx_dma;
+
+ return ret + (desc - ring->tx_phys);
+}
+
+static struct mtk_tx_dma *mtk_tx_next_qdma(struct mtk_tx_ring *ring,
+ struct mtk_tx_dma *txd)
+{
+ return mtk_qdma_phys_to_virt(ring, txd->txd2);
+}
+
+static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
+ struct mtk_tx_dma *txd)
+{
+ int idx = txd - ring->tx_dma;
+
+ return &ring->tx_buf[idx];
+}
+
+static int mtk_qdma_tx_map(struct sk_buff *skb, struct net_device *dev,
+ int tx_num, struct mtk_tx_ring *ring, bool gso)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ struct mtk_tx_dma *itxd, *txd;
+ struct mtk_tx_buf *tx_buf;
+ dma_addr_t mapped_addr;
+ unsigned int nr_frags;
+ int i, n_desc = 1;
+ u32 txd4 = eth->soc->txd4;
+
+ itxd = ring->tx_next_free;
+ if (itxd == ring->tx_last_free)
+ return -ENOMEM;
+
+ if (eth->soc->mac_count > 1)
+ txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
+
+ tx_buf = mtk_desc_to_tx_buf(ring, itxd);
+ memset(tx_buf, 0, sizeof(*tx_buf));
+
+ if (gso)
+ txd4 |= TX_DMA_TSO;
+
+ /* TX Checksum offload */
+ if (skb->ip_summed == CHECKSUM_PARTIAL)
+ txd4 |= TX_DMA_CHKSUM;
+
+ /* VLAN header offload */
+ if (skb_vlan_tag_present(skb))
+ txd4 |= TX_DMA_INS_VLAN_MT7621 | skb_vlan_tag_get(skb);
+
+ mapped_addr = dma_map_single(&dev->dev, skb->data,
+ skb_headlen(skb), DMA_TO_DEVICE);
+ if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
+ return -ENOMEM;
+
+ WRITE_ONCE(itxd->txd1, mapped_addr);
+ tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
+ dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
+ dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
+
+ /* TX SG offload */
+ txd = itxd;
+ nr_frags = skb_shinfo(skb)->nr_frags;
+ for (i = 0; i < nr_frags; i++) {
+ struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
+ unsigned int offset = 0;
+ int frag_size = skb_frag_size(frag);
+
+ while (frag_size) {
+ bool last_frag = false;
+ unsigned int frag_map_size;
+
+ txd = mtk_tx_next_qdma(ring, txd);
+ if (txd == ring->tx_last_free)
+ goto err_dma;
+
+ n_desc++;
+ frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
+ mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
+ frag_map_size,
+ DMA_TO_DEVICE);
+ if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
+ goto err_dma;
+
+ if (i == nr_frags - 1 &&
+ (frag_size - frag_map_size) == 0)
+ last_frag = true;
+
+ WRITE_ONCE(txd->txd1, mapped_addr);
+ WRITE_ONCE(txd->txd3, (QDMA_TX_SWC |
+ TX_DMA_PLEN0(frag_map_size) |
+ last_frag * TX_DMA_LS0) |
+ mac->id);
+ WRITE_ONCE(txd->txd4, 0);
+
+ tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
+ tx_buf = mtk_desc_to_tx_buf(ring, txd);
+ memset(tx_buf, 0, sizeof(*tx_buf));
+
+ tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
+ dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
+ dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
+ frag_size -= frag_map_size;
+ offset += frag_map_size;
+ }
+ }
+
+ /* store skb to cleanup */
+ tx_buf->skb = skb;
+
+ WRITE_ONCE(itxd->txd4, txd4);
+ WRITE_ONCE(itxd->txd3, (QDMA_TX_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
+ (!nr_frags * TX_DMA_LS0)));
+
+ netdev_sent_queue(dev, skb->len);
+ skb_tx_timestamp(skb);
+
+ ring->tx_next_free = mtk_tx_next_qdma(ring, txd);
+ atomic_sub(n_desc, &ring->tx_free_count);
+
+ /* make sure that all changes to the dma ring are flushed before we
+ * continue
+ */
+ wmb();
+
+ if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
+ mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
+
+ return 0;
+
+err_dma:
+ do {
+ tx_buf = mtk_desc_to_tx_buf(ring, txd);
+
+ /* unmap dma */
+ mtk_txd_unmap(&dev->dev, tx_buf);
+
+ itxd->txd3 = TX_DMA_DESP2_DEF;
+ itxd = mtk_tx_next_qdma(ring, itxd);
+ } while (itxd != txd);
+
+ return -ENOMEM;
+}
+
+static inline int mtk_cal_txd_req(struct sk_buff *skb)
+{
+ int i, nfrags;
+ struct skb_frag_struct *frag;
+
+ nfrags = 1;
+ if (skb_is_gso(skb)) {
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ frag = &skb_shinfo(skb)->frags[i];
+ nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
+ }
+ } else {
+ nfrags += skb_shinfo(skb)->nr_frags;
+ }
+
+ return DIV_ROUND_UP(nfrags, 2);
+}
+
+static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ struct mtk_tx_ring *ring = ð->tx_ring;
+ struct net_device_stats *stats = &dev->stats;
+ int tx_num;
+ int len = skb->len;
+ bool gso = false;
+
+ tx_num = mtk_cal_txd_req(skb);
+ if (unlikely(atomic_read(&ring->tx_free_count) <= tx_num)) {
+ netif_stop_queue(dev);
+ netif_err(eth, tx_queued, dev,
+ "Tx Ring full when queue awake!\n");
+ return NETDEV_TX_BUSY;
+ }
+
+ /* TSO: fill MSS info in tcp checksum field */
+ if (skb_is_gso(skb)) {
+ if (skb_cow_head(skb, 0)) {
+ netif_warn(eth, tx_err, dev,
+ "GSO expand head fail.\n");
+ goto drop;
+ }
+
+ if (skb_shinfo(skb)->gso_type &
+ (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
+ gso = true;
+ tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
+ }
+ }
+
+ if (ring->tx_map(skb, dev, tx_num, ring, gso) < 0)
+ goto drop;
+
+ stats->tx_packets++;
+ stats->tx_bytes += len;
+
+ if (unlikely(atomic_read(&ring->tx_free_count) <= ring->tx_thresh)) {
+ netif_stop_queue(dev);
+ smp_mb();
+ if (unlikely(atomic_read(&ring->tx_free_count) >
+ ring->tx_thresh))
+ netif_wake_queue(dev);
+ }
+
+ return NETDEV_TX_OK;
+
+drop:
+ stats->tx_dropped++;
+ dev_kfree_skb(skb);
+ return NETDEV_TX_OK;
+}
+
+static int mtk_poll_rx(struct napi_struct *napi, int budget,
+ struct mtk_eth *eth, u32 rx_intr)
+{
+ struct mtk_soc_data *soc = eth->soc;
+ struct mtk_rx_ring *ring = ð->rx_ring[0];
+ int idx = ring->rx_calc_idx;
+ u32 checksum_bit;
+ struct sk_buff *skb;
+ u8 *data, *new_data;
+ struct mtk_rx_dma *rxd, trxd;
+ int done = 0, pad;
+
+ if (eth->soc->hw_features & NETIF_F_RXCSUM)
+ checksum_bit = soc->checksum_bit;
+ else
+ checksum_bit = 0;
+
+ if (eth->soc->rx_2b_offset)
+ pad = 0;
+ else
+ pad = NET_IP_ALIGN;
+
+ while (done < budget) {
+ struct net_device *netdev;
+ unsigned int pktlen;
+ dma_addr_t dma_addr;
+ int mac = 0;
+
+ idx = NEXT_RX_DESP_IDX(idx);
+ rxd = &ring->rx_dma[idx];
+ data = ring->rx_data[idx];
+
+ mtk_get_rxd(&trxd, rxd);
+ if (!(trxd.rxd2 & RX_DMA_DONE))
+ break;
+
+ /* find out which mac the packet come from. values start at 1 */
+ if (eth->soc->mac_count > 1) {
+ mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
+ RX_DMA_FPORT_MASK;
+ mac--;
+ }
+
+ netdev = eth->netdev[mac];
+
+ /* alloc new buffer */
+ new_data = napi_alloc_frag(ring->frag_size);
+ if (unlikely(!new_data)) {
+ netdev->stats.rx_dropped++;
+ goto release_desc;
+ }
+ dma_addr = dma_map_single(ð->netdev[mac]->dev,
+ new_data + NET_SKB_PAD + pad,
+ ring->rx_buf_size,
+ DMA_FROM_DEVICE);
+ if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
+ skb_free_frag(new_data);
+ goto release_desc;
+ }
+
+ /* receive data */
+ skb = build_skb(data, ring->frag_size);
+ if (unlikely(!skb)) {
+ put_page(virt_to_head_page(new_data));
+ goto release_desc;
+ }
+ skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
+
+ dma_unmap_single(&netdev->dev, trxd.rxd1,
+ ring->rx_buf_size, DMA_FROM_DEVICE);
+ pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
+ skb->dev = netdev;
+ skb_put(skb, pktlen);
+ if (trxd.rxd4 & checksum_bit)
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ else
+ skb_checksum_none_assert(skb);
+ skb->protocol = eth_type_trans(skb, netdev);
+
+ netdev->stats.rx_packets++;
+ netdev->stats.rx_bytes += pktlen;
+
+ if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
+ RX_DMA_VID(trxd.rxd3))
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
+ RX_DMA_VID(trxd.rxd3));
+ napi_gro_receive(napi, skb);
+
+ ring->rx_data[idx] = new_data;
+ rxd->rxd1 = (unsigned int)dma_addr;
+
+release_desc:
+ if (eth->soc->rx_sg_dma)
+ rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
+ else
+ rxd->rxd2 = RX_DMA_LSO;
+
+ ring->rx_calc_idx = idx;
+ /* make sure that all changes to the dma ring are flushed before
+ * we continue
+ */
+ wmb();
+ if (eth->soc->dma_type == MTK_QDMA)
+ mtk_w32(eth, ring->rx_calc_idx, MTK_QRX_CRX_IDX0);
+ else
+ mtk_reg_w32(eth, ring->rx_calc_idx,
+ MTK_REG_RX_CALC_IDX0);
+ done++;
+ }
+
+ if (done < budget)
+ mtk_irq_ack(eth, rx_intr);
+
+ return done;
+}
+
+static int mtk_pdma_tx_poll(struct mtk_eth *eth, int budget, bool *tx_again)
+{
+ struct sk_buff *skb;
+ struct mtk_tx_buf *tx_buf;
+ int done = 0;
+ u32 idx, hwidx;
+ struct mtk_tx_ring *ring = ð->tx_ring;
+ unsigned int bytes = 0;
+
+ idx = ring->tx_free_idx;
+ hwidx = mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0);
+
+ while ((idx != hwidx) && budget) {
+ tx_buf = &ring->tx_buf[idx];
+ skb = tx_buf->skb;
+
+ if (!skb)
+ break;
+
+ if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
+ bytes += skb->len;
+ done++;
+ budget--;
+ }
+ mtk_txd_unmap(eth->dev, tx_buf);
+ idx = NEXT_TX_DESP_IDX(idx);
+ }
+ ring->tx_free_idx = idx;
+ atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
+
+ /* read hw index again make sure no new tx packet */
+ if (idx != hwidx || idx != mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0))
+ *tx_again = 1;
+
+ if (done)
+ netdev_completed_queue(*eth->netdev, done, bytes);
+
+ return done;
+}
+
+static int mtk_qdma_tx_poll(struct mtk_eth *eth, int budget, bool *tx_again)
+{
+ struct mtk_tx_ring *ring = ð->tx_ring;
+ struct mtk_tx_dma *desc;
+ struct sk_buff *skb;
+ struct mtk_tx_buf *tx_buf;
+ int total = 0, done[MTK_MAX_DEVS];
+ unsigned int bytes[MTK_MAX_DEVS];
+ u32 cpu, dma;
+ static int condition;
+ int i;
+
+ memset(done, 0, sizeof(done));
+ memset(bytes, 0, sizeof(bytes));
+
+ cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
+ dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
+
+ desc = mtk_qdma_phys_to_virt(ring, cpu);
+
+ while ((cpu != dma) && budget) {
+ u32 next_cpu = desc->txd2;
+ int mac;
+
+ desc = mtk_tx_next_qdma(ring, desc);
+ if ((desc->txd3 & QDMA_TX_OWNER_CPU) == 0)
+ break;
+
+ mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
+ TX_DMA_FPORT_MASK;
+ mac--;
+
+ tx_buf = mtk_desc_to_tx_buf(ring, desc);
+ skb = tx_buf->skb;
+ if (!skb) {
+ condition = 1;
+ break;
+ }
+
+ if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
+ bytes[mac] += skb->len;
+ done[mac]++;
+ budget--;
+ }
+ mtk_txd_unmap(eth->dev, tx_buf);
+
+ ring->tx_last_free->txd2 = next_cpu;
+ ring->tx_last_free = desc;
+ atomic_inc(&ring->tx_free_count);
+
+ cpu = next_cpu;
+ }
+
+ mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
+
+ /* read hw index again make sure no new tx packet */
+ if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
+ *tx_again = true;
+
+ for (i = 0; i < eth->soc->mac_count; i++) {
+ if (!done[i])
+ continue;
+ netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
+ total += done[i];
+ }
+
+ return total;
+}
+
+static int mtk_poll_tx(struct mtk_eth *eth, int budget, u32 tx_intr,
+ bool *tx_again)
+{
+ struct mtk_tx_ring *ring = ð->tx_ring;
+ struct net_device *netdev = eth->netdev[0];
+ int done;
+
+ done = eth->tx_ring.tx_poll(eth, budget, tx_again);
+ if (!*tx_again)
+ mtk_irq_ack(eth, tx_intr);
+
+ if (!done)
+ return 0;
+
+ smp_mb();
+ if (unlikely(!netif_queue_stopped(netdev)))
+ return done;
+
+ if (atomic_read(&ring->tx_free_count) > ring->tx_thresh)
+ netif_wake_queue(netdev);
+
+ return done;
+}
+
+static void mtk_stats_update(struct mtk_eth *eth)
+{
+ int i;
+
+ for (i = 0; i < eth->soc->mac_count; i++) {
+ if (!eth->mac[i] || !eth->mac[i]->hw_stats)
+ continue;
+ if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
+ mtk_stats_update_mac(eth->mac[i]);
+ spin_unlock(ð->mac[i]->hw_stats->stats_lock);
+ }
+ }
+}
+
+static int mtk_poll(struct napi_struct *napi, int budget)
+{
+ struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
+ u32 status, mtk_status, mask, tx_intr, rx_intr, status_intr;
+ int tx_done, rx_done;
+ bool tx_again = false;
+
+ status = mtk_irq_pending(eth);
+ mtk_status = mtk_irq_pending_status(eth);
+ tx_intr = eth->soc->tx_int;
+ rx_intr = eth->soc->rx_int;
+ status_intr = eth->soc->status_int;
+ tx_done = 0;
+ rx_done = 0;
+ tx_again = 0;
+
+ if (status & tx_intr)
+ tx_done = mtk_poll_tx(eth, budget, tx_intr, &tx_again);
+
+ if (status & rx_intr)
+ rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
+
+ if (unlikely(mtk_status & status_intr)) {
+ mtk_stats_update(eth);
+ mtk_irq_ack_status(eth, status_intr);
+ }
+
+ if (unlikely(netif_msg_intr(eth))) {
+ mask = mtk_irq_enabled(eth);
+ netdev_info(eth->netdev[0],
+ "done tx %d, rx %d, intr 0x%08x/0x%x\n",
+ tx_done, rx_done, status, mask);
+ }
+
+ if (tx_again || rx_done == budget)
+ return budget;
+
+ status = mtk_irq_pending(eth);
+ if (status & (tx_intr | rx_intr))
+ return budget;
+
+ napi_complete(napi);
+ mtk_irq_enable(eth, tx_intr | rx_intr);
+
+ return rx_done;
+}
+
+static int mtk_pdma_tx_alloc(struct mtk_eth *eth)
+{
+ int i;
+ struct mtk_tx_ring *ring = ð->tx_ring;
+
+ ring->tx_ring_size = eth->soc->dma_ring_size;
+ ring->tx_free_idx = 0;
+ ring->tx_next_idx = 0;
+ ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
+ MAX_SKB_FRAGS);
+
+ ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
+ GFP_KERNEL);
+ if (!ring->tx_buf)
+ goto no_tx_mem;
+
+ ring->tx_dma = dma_alloc_coherent(eth->dev,
+ ring->tx_ring_size * sizeof(*ring->tx_dma),
+ &ring->tx_phys,
+ GFP_ATOMIC | __GFP_ZERO);
+ if (!ring->tx_dma)
+ goto no_tx_mem;
+
+ for (i = 0; i < ring->tx_ring_size; i++) {
+ ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
+ ring->tx_dma[i].txd4 = eth->soc->txd4;
+ }
+
+ atomic_set(&ring->tx_free_count, mtk_pdma_empty_txd(ring));
+ ring->tx_map = mtk_pdma_tx_map;
+ ring->tx_poll = mtk_pdma_tx_poll;
+ ring->tx_clean = mtk_pdma_tx_clean;
+
+ /* make sure that all changes to the dma ring are flushed before we
+ * continue
+ */
+ wmb();
+
+ mtk_reg_w32(eth, ring->tx_phys, MTK_REG_TX_BASE_PTR0);
+ mtk_reg_w32(eth, ring->tx_ring_size, MTK_REG_TX_MAX_CNT0);
+ mtk_reg_w32(eth, 0, MTK_REG_TX_CTX_IDX0);
+ mtk_reg_w32(eth, MTK_PST_DTX_IDX0, MTK_REG_PDMA_RST_CFG);
+
+ return 0;
+
+no_tx_mem:
+ return -ENOMEM;
+}
+
+static int mtk_qdma_tx_alloc_tx(struct mtk_eth *eth)
+{
+ struct mtk_tx_ring *ring = ð->tx_ring;
+ int i, sz = sizeof(*ring->tx_dma);
+
+ ring->tx_ring_size = eth->soc->dma_ring_size;
+ ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
+ GFP_KERNEL);
+ if (!ring->tx_buf)
+ goto no_tx_mem;
+
+ ring->tx_dma = dma_alloc_coherent(eth->dev,
+ ring->tx_ring_size * sz,
+ &ring->tx_phys,
+ GFP_ATOMIC | __GFP_ZERO);
+ if (!ring->tx_dma)
+ goto no_tx_mem;
+
+ memset(ring->tx_dma, 0, ring->tx_ring_size * sz);
+ for (i = 0; i < ring->tx_ring_size; i++) {
+ int next = (i + 1) % ring->tx_ring_size;
+ u32 next_ptr = ring->tx_phys + next * sz;
+
+ ring->tx_dma[i].txd2 = next_ptr;
+ ring->tx_dma[i].txd3 = TX_DMA_DESP2_DEF;
+ }
+
+ atomic_set(&ring->tx_free_count, ring->tx_ring_size - 2);
+ ring->tx_next_free = &ring->tx_dma[0];
+ ring->tx_last_free = &ring->tx_dma[ring->tx_ring_size - 2];
+ ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
+ MAX_SKB_FRAGS);
+
+ ring->tx_map = mtk_qdma_tx_map;
+ ring->tx_poll = mtk_qdma_tx_poll;
+ ring->tx_clean = mtk_qdma_tx_clean;
+
+ /* make sure that all changes to the dma ring are flushed before we
+ * continue
+ */
+ wmb();
+
+ mtk_w32(eth, ring->tx_phys, MTK_QTX_CTX_PTR);
+ mtk_w32(eth, ring->tx_phys, MTK_QTX_DTX_PTR);
+ mtk_w32(eth,
+ ring->tx_phys + ((ring->tx_ring_size - 1) * sz),
+ MTK_QTX_CRX_PTR);
+ mtk_w32(eth,
+ ring->tx_phys + ((ring->tx_ring_size - 1) * sz),
+ MTK_QTX_DRX_PTR);
+
+ return 0;
+
+no_tx_mem:
+ return -ENOMEM;
+}
+
+static int mtk_qdma_init(struct mtk_eth *eth, int ring)
+{
+ int err;
+
+ err = mtk_init_fq_dma(eth);
+ if (err)
+ return err;
+
+ err = mtk_qdma_tx_alloc_tx(eth);
+ if (err)
+ return err;
+
+ err = mtk_dma_rx_alloc(eth, ð->rx_ring[ring]);
+ if (err)
+ return err;
+
+ mtk_w32(eth, eth->rx_ring[ring].rx_phys, MTK_QRX_BASE_PTR0);
+ mtk_w32(eth, eth->rx_ring[ring].rx_ring_size, MTK_QRX_MAX_CNT0);
+ mtk_w32(eth, eth->rx_ring[ring].rx_calc_idx, MTK_QRX_CRX_IDX0);
+ mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
+ mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
+
+ /* Enable random early drop and set drop threshold automatically */
+ mtk_w32(eth, 0x174444, MTK_QDMA_FC_THRES);
+ mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
+
+ return 0;
+}
+
+static int mtk_pdma_qdma_init(struct mtk_eth *eth)
+{
+ int err = mtk_qdma_init(eth, 1);
+
+ if (err)
+ return err;
+
+ err = mtk_dma_rx_alloc(eth, ð->rx_ring[0]);
+ if (err)
+ return err;
+
+ mtk_reg_w32(eth, eth->rx_ring[0].rx_phys, MTK_REG_RX_BASE_PTR0);
+ mtk_reg_w32(eth, eth->rx_ring[0].rx_ring_size, MTK_REG_RX_MAX_CNT0);
+ mtk_reg_w32(eth, eth->rx_ring[0].rx_calc_idx, MTK_REG_RX_CALC_IDX0);
+ mtk_reg_w32(eth, MTK_PST_DRX_IDX0, MTK_REG_PDMA_RST_CFG);
+
+ return 0;
+}
+
+static int mtk_pdma_init(struct mtk_eth *eth)
+{
+ struct mtk_rx_ring *ring = ð->rx_ring[0];
+ int err;
+
+ err = mtk_pdma_tx_alloc(eth);
+ if (err)
+ return err;
+
+ err = mtk_dma_rx_alloc(eth, ring);
+ if (err)
+ return err;
+
+ mtk_reg_w32(eth, ring->rx_phys, MTK_REG_RX_BASE_PTR0);
+ mtk_reg_w32(eth, ring->rx_ring_size, MTK_REG_RX_MAX_CNT0);
+ mtk_reg_w32(eth, ring->rx_calc_idx, MTK_REG_RX_CALC_IDX0);
+ mtk_reg_w32(eth, MTK_PST_DRX_IDX0, MTK_REG_PDMA_RST_CFG);
+
+ return 0;
+}
+
+static void mtk_dma_free(struct mtk_eth *eth)
+{
+ int i;
+
+ for (i = 0; i < eth->soc->mac_count; i++)
+ if (eth->netdev[i])
+ netdev_reset_queue(eth->netdev[i]);
+ eth->tx_ring.tx_clean(eth);
+ mtk_clean_rx(eth, ð->rx_ring[0]);
+ mtk_clean_rx(eth, ð->rx_ring[1]);
+ kfree(eth->scratch_head);
+}
+
+static void mtk_tx_timeout(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ struct mtk_tx_ring *ring = ð->tx_ring;
+
+ eth->netdev[mac->id]->stats.tx_errors++;
+ netif_err(eth, tx_err, dev,
+ "transmit timed out\n");
+ if (eth->soc->dma_type & MTK_PDMA) {
+ netif_info(eth, drv, dev, "pdma_cfg:%08x\n",
+ mtk_reg_r32(eth, MTK_REG_PDMA_GLO_CFG));
+ netif_info(eth, drv, dev, "tx_ring=%d, "
+ "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
+ 0, mtk_reg_r32(eth, MTK_REG_TX_BASE_PTR0),
+ mtk_reg_r32(eth, MTK_REG_TX_MAX_CNT0),
+ mtk_reg_r32(eth, MTK_REG_TX_CTX_IDX0),
+ mtk_reg_r32(eth, MTK_REG_TX_DTX_IDX0),
+ ring->tx_free_idx,
+ ring->tx_next_idx);
+ }
+ if (eth->soc->dma_type & MTK_QDMA) {
+ netif_info(eth, drv, dev, "qdma_cfg:%08x\n",
+ mtk_r32(eth, MTK_QDMA_GLO_CFG));
+ netif_info(eth, drv, dev, "tx_ring=%d, "
+ "ctx=%08x, dtx=%08x, crx=%08x, drx=%08x, free=%hu\n",
+ 0, mtk_r32(eth, MTK_QTX_CTX_PTR),
+ mtk_r32(eth, MTK_QTX_DTX_PTR),
+ mtk_r32(eth, MTK_QTX_CRX_PTR),
+ mtk_r32(eth, MTK_QTX_DRX_PTR),
+ atomic_read(&ring->tx_free_count));
+ }
+ netif_info(eth, drv, dev,
+ "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
+ 0, mtk_reg_r32(eth, MTK_REG_RX_BASE_PTR0),
+ mtk_reg_r32(eth, MTK_REG_RX_MAX_CNT0),
+ mtk_reg_r32(eth, MTK_REG_RX_CALC_IDX0),
+ mtk_reg_r32(eth, MTK_REG_RX_DRX_IDX0));
+
+ schedule_work(&mac->pending_work);
+}
+
+static irqreturn_t mtk_handle_irq(int irq, void *_eth)
+{
+ struct mtk_eth *eth = _eth;
+ u32 status, int_mask;
+
+ status = mtk_irq_pending(eth);
+ if (unlikely(!status))
+ return IRQ_NONE;
+
+ int_mask = (eth->soc->rx_int | eth->soc->tx_int);
+ if (likely(status & int_mask)) {
+ if (likely(napi_schedule_prep(ð->rx_napi)))
+ __napi_schedule(ð->rx_napi);
+ } else {
+ mtk_irq_ack(eth, status);
+ }
+ mtk_irq_disable(eth, int_mask);
+
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void mtk_poll_controller(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ u32 int_mask = eth->soc->tx_int | eth->soc->rx_int;
+
+ mtk_irq_disable(eth, int_mask);
+ mtk_handle_irq(dev->irq, dev);
+ mtk_irq_enable(eth, int_mask);
+}
+#endif
+
+int mtk_set_clock_cycle(struct mtk_eth *eth)
+{
+ unsigned long sysclk = eth->sysclk;
+
+ sysclk /= MTK_US_CYC_CNT_DIVISOR;
+ sysclk <<= MTK_US_CYC_CNT_SHIFT;
+
+ mtk_w32(eth, (mtk_r32(eth, MTK_GLO_CFG) &
+ ~(MTK_US_CYC_CNT_MASK << MTK_US_CYC_CNT_SHIFT)) |
+ sysclk,
+ MTK_GLO_CFG);
+ return 0;
+}
+
+void mtk_fwd_config(struct mtk_eth *eth)
+{
+ u32 fwd_cfg;
+
+ fwd_cfg = mtk_r32(eth, MTK_GDMA1_FWD_CFG);
+
+ /* disable jumbo frame */
+ if (eth->soc->jumbo_frame)
+ fwd_cfg &= ~MTK_GDM1_JMB_EN;
+
+ /* set unicast/multicast/broadcast frame to cpu */
+ fwd_cfg &= ~0xffff;
+
+ mtk_w32(eth, fwd_cfg, MTK_GDMA1_FWD_CFG);
+}
+
+void mtk_csum_config(struct mtk_eth *eth)
+{
+ if (eth->soc->hw_features & NETIF_F_RXCSUM)
+ mtk_w32(eth, mtk_r32(eth, MTK_GDMA1_FWD_CFG) |
+ (MTK_GDM1_ICS_EN | MTK_GDM1_TCS_EN | MTK_GDM1_UCS_EN),
+ MTK_GDMA1_FWD_CFG);
+ else
+ mtk_w32(eth, mtk_r32(eth, MTK_GDMA1_FWD_CFG) &
+ ~(MTK_GDM1_ICS_EN | MTK_GDM1_TCS_EN | MTK_GDM1_UCS_EN),
+ MTK_GDMA1_FWD_CFG);
+ if (eth->soc->hw_features & NETIF_F_IP_CSUM)
+ mtk_w32(eth, mtk_r32(eth, MTK_CDMA_CSG_CFG) |
+ (MTK_ICS_GEN_EN | MTK_TCS_GEN_EN | MTK_UCS_GEN_EN),
+ MTK_CDMA_CSG_CFG);
+ else
+ mtk_w32(eth, mtk_r32(eth, MTK_CDMA_CSG_CFG) &
+ ~(MTK_ICS_GEN_EN | MTK_TCS_GEN_EN | MTK_UCS_GEN_EN),
+ MTK_CDMA_CSG_CFG);
+}
+
+static int mtk_start_dma(struct mtk_eth *eth)
+{
+ unsigned long flags;
+ u32 val;
+ int err;
+
+ if (eth->soc->dma_type == MTK_PDMA)
+ err = mtk_pdma_init(eth);
+ else if (eth->soc->dma_type == MTK_QDMA)
+ err = mtk_qdma_init(eth, 0);
+ else
+ err = mtk_pdma_qdma_init(eth);
+ if (err) {
+ mtk_dma_free(eth);
+ return err;
+ }
+
+ spin_lock_irqsave(ð->page_lock, flags);
+
+ val = MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN;
+ if (eth->soc->rx_2b_offset)
+ val |= MTK_RX_2B_OFFSET;
+ val |= eth->soc->pdma_glo_cfg;
+
+ if (eth->soc->dma_type & MTK_PDMA)
+ mtk_reg_w32(eth, val, MTK_REG_PDMA_GLO_CFG);
+
+ if (eth->soc->dma_type & MTK_QDMA)
+ mtk_w32(eth, val, MTK_QDMA_GLO_CFG);
+
+ spin_unlock_irqrestore(ð->page_lock, flags);
+
+ return 0;
+}
+
+static int mtk_open(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+
+ if (!atomic_read(ð->dma_refcnt)) {
+ int err = mtk_start_dma(eth);
+
+ if (err)
+ return err;
+
+ napi_enable(ð->rx_napi);
+ mtk_irq_enable(eth, eth->soc->tx_int | eth->soc->rx_int);
+ }
+ atomic_inc(ð->dma_refcnt);
+
+ if (eth->phy)
+ eth->phy->start(mac);
+
+ if (eth->soc->has_carrier && eth->soc->has_carrier(eth))
+ netif_carrier_on(dev);
+
+ netif_start_queue(dev);
+ eth->soc->fwd_config(eth);
+
+ return 0;
+}
+
+static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
+{
+ unsigned long flags;
+ u32 val;
+ int i;
+
+ /* stop the dma enfine */
+ spin_lock_irqsave(ð->page_lock, flags);
+ val = mtk_r32(eth, glo_cfg);
+ mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
+ glo_cfg);
+ spin_unlock_irqrestore(ð->page_lock, flags);
+
+ /* wait for dma stop */
+ for (i = 0; i < 10; i++) {
+ val = mtk_r32(eth, glo_cfg);
+ if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
+ msleep(20);
+ continue;
+ }
+ break;
+ }
+}
+
+static int mtk_stop(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+
+ netif_tx_disable(dev);
+ if (eth->phy)
+ eth->phy->stop(mac);
+
+ if (!atomic_dec_and_test(ð->dma_refcnt))
+ return 0;
+
+ mtk_irq_disable(eth, eth->soc->tx_int | eth->soc->rx_int);
+ napi_disable(ð->rx_napi);
+
+ if (eth->soc->dma_type & MTK_PDMA)
+ mtk_stop_dma(eth, mtk_reg_table[MTK_REG_PDMA_GLO_CFG]);
+
+ if (eth->soc->dma_type & MTK_QDMA)
+ mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
+
+ mtk_dma_free(eth);
+
+ return 0;
+}
+
+static int __init mtk_init_hw(struct mtk_eth *eth)
+{
+ int i, err;
+
+ eth->soc->reset_fe(eth);
+
+ if (eth->soc->switch_init)
+ if (eth->soc->switch_init(eth)) {
+ dev_err(eth->dev, "failed to initialize switch core\n");
+ return -ENODEV;
+ }
+
+ err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
+ dev_name(eth->dev), eth);
+ if (err)
+ return err;
+
+ err = mtk_mdio_init(eth);
+ if (err)
+ return err;
+
+ /* disable delay and normal interrupt */
+ mtk_reg_w32(eth, 0, MTK_REG_DLY_INT_CFG);
+ if (eth->soc->dma_type & MTK_QDMA)
+ mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
+ mtk_irq_disable(eth, eth->soc->tx_int | eth->soc->rx_int);
+
+ /* frame engine will push VLAN tag regarding to VIDX field in Tx desc */
+ if (mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE])
+ for (i = 0; i < 16; i += 2)
+ mtk_w32(eth, ((i + 1) << 16) + i,
+ mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE] +
+ (i * 2));
+
+ if (eth->soc->fwd_config(eth))
+ dev_err(eth->dev, "unable to get clock\n");
+
+ if (mtk_reg_table[MTK_REG_MTK_RST_GL]) {
+ mtk_reg_w32(eth, 1, MTK_REG_MTK_RST_GL);
+ mtk_reg_w32(eth, 0, MTK_REG_MTK_RST_GL);
+ }
+
+ return 0;
+}
+
+static int __init mtk_init(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ struct device_node *port;
+ const char *mac_addr;
+ int err;
+
+ mac_addr = of_get_mac_address(mac->of_node);
+ if (mac_addr)
+ ether_addr_copy(dev->dev_addr, mac_addr);
+
+ /* If the mac address is invalid, use random mac address */
+ if (!is_valid_ether_addr(dev->dev_addr)) {
+ random_ether_addr(dev->dev_addr);
+ dev_err(eth->dev, "generated random MAC address %pM\n",
+ dev->dev_addr);
+ dev->addr_assign_type = NET_ADDR_RANDOM;
+ }
+
+ if (eth->soc->port_init)
+ for_each_child_of_node(mac->of_node, port)
+ if (of_device_is_compatible(port,
+ "mediatek,eth-port") &&
+ of_device_is_available(port))
+ eth->soc->port_init(eth, mac, port);
+
+ if (eth->phy) {
+ err = eth->phy->connect(mac);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static void mtk_uninit(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+
+ if (eth->phy)
+ eth->phy->disconnect(mac);
+ mtk_mdio_cleanup(eth);
+
+ mtk_irq_disable(eth, ~0);
+ free_irq(dev->irq, dev);
+}
+
+static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+
+ if (!mac->phy_dev)
+ return -ENODEV;
+
+ switch (cmd) {
+ case SIOCGMIIPHY:
+ case SIOCGMIIREG:
+ case SIOCSMIIREG:
+ return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static int mtk_change_mtu(struct net_device *dev, int new_mtu)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ int frag_size, old_mtu;
+ u32 fwd_cfg;
+
+ if (!eth->soc->jumbo_frame)
+ return eth_change_mtu(dev, new_mtu);
+
+ frag_size = mtk_max_frag_size(new_mtu);
+ if (new_mtu < 68 || frag_size > PAGE_SIZE)
+ return -EINVAL;
+
+ old_mtu = dev->mtu;
+ dev->mtu = new_mtu;
+
+ /* return early if the buffer sizes will not change */
+ if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
+ return 0;
+ if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
+ return 0;
+
+ if (new_mtu <= ETH_DATA_LEN)
+ eth->rx_ring[0].frag_size = mtk_max_frag_size(ETH_DATA_LEN);
+ else
+ eth->rx_ring[0].frag_size = PAGE_SIZE;
+ eth->rx_ring[0].rx_buf_size =
+ mtk_max_buf_size(eth->rx_ring[0].frag_size);
+
+ if (!netif_running(dev))
+ return 0;
+
+ mtk_stop(dev);
+ fwd_cfg = mtk_r32(eth, MTK_GDMA1_FWD_CFG);
+ if (new_mtu <= ETH_DATA_LEN) {
+ fwd_cfg &= ~MTK_GDM1_JMB_EN;
+ } else {
+ fwd_cfg &= ~(MTK_GDM1_JMB_LEN_MASK << MTK_GDM1_JMB_LEN_SHIFT);
+ fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
+ MTK_GDM1_JMB_LEN_SHIFT) | MTK_GDM1_JMB_EN;
+ }
+ mtk_w32(eth, fwd_cfg, MTK_GDMA1_FWD_CFG);
+
+ return mtk_open(dev);
+}
+
+static void mtk_pending_work(struct work_struct *work)
+{
+ struct mtk_mac *mac = container_of(work, struct mtk_mac, pending_work);
+ struct mtk_eth *eth = mac->hw;
+ struct net_device *dev = eth->netdev[mac->id];
+ int err;
+
+ rtnl_lock();
+ mtk_stop(dev);
+
+ err = mtk_open(dev);
+ if (err) {
+ netif_alert(eth, ifup, dev,
+ "Driver up/down cycle failed, closing device.\n");
+ dev_close(dev);
+ }
+ rtnl_unlock();
+}
+
+static int mtk_cleanup(struct mtk_eth *eth)
+{
+ int i;
+
+ for (i = 0; i < eth->soc->mac_count; i++) {
+ struct mtk_mac *mac = netdev_priv(eth->netdev[i]);
+
+ if (!eth->netdev[i])
+ continue;
+
+ unregister_netdev(eth->netdev[i]);
+ free_netdev(eth->netdev[i]);
+ cancel_work_sync(&mac->pending_work);
+ }
+
+ return 0;
+}
+
+static const struct net_device_ops mtk_netdev_ops = {
+ .ndo_init = mtk_init,
+ .ndo_uninit = mtk_uninit,
+ .ndo_open = mtk_open,
+ .ndo_stop = mtk_stop,
+ .ndo_start_xmit = mtk_start_xmit,
+ .ndo_set_mac_address = mtk_set_mac_address,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_do_ioctl = mtk_do_ioctl,
+ .ndo_change_mtu = mtk_change_mtu,
+ .ndo_tx_timeout = mtk_tx_timeout,
+ .ndo_get_stats64 = mtk_get_stats64,
+ .ndo_vlan_rx_add_vid = mtk_vlan_rx_add_vid,
+ .ndo_vlan_rx_kill_vid = mtk_vlan_rx_kill_vid,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = mtk_poll_controller,
+#endif
+};
+
+static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+{
+ struct mtk_mac *mac;
+ const __be32 *_id = of_get_property(np, "reg", NULL);
+ int id, err;
+
+ if (!_id) {
+ dev_err(eth->dev, "missing mac id\n");
+ return -EINVAL;
+ }
+ id = be32_to_cpup(_id);
+ if (id >= eth->soc->mac_count || eth->netdev[id]) {
+ dev_err(eth->dev, "%d is not a valid mac id\n", id);
+ return -EINVAL;
+ }
+
+ eth->netdev[id] = alloc_etherdev(sizeof(*mac));
+ if (!eth->netdev[id]) {
+ dev_err(eth->dev, "alloc_etherdev failed\n");
+ return -ENOMEM;
+ }
+ mac = netdev_priv(eth->netdev[id]);
+ eth->mac[id] = mac;
+ mac->id = id;
+ mac->hw = eth;
+ mac->of_node = np;
+ INIT_WORK(&mac->pending_work, mtk_pending_work);
+
+ if (mtk_reg_table[MTK_REG_MTK_COUNTER_BASE]) {
+ mac->hw_stats = devm_kzalloc(eth->dev,
+ sizeof(*mac->hw_stats),
+ GFP_KERNEL);
+ if (!mac->hw_stats)
+ return -ENOMEM;
+ spin_lock_init(&mac->hw_stats->stats_lock);
+ mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
+ }
+
+ SET_NETDEV_DEV(eth->netdev[id], eth->dev);
+ eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
+ eth->netdev[id]->base_addr = (unsigned long)eth->base;
+
+ if (eth->soc->init_data)
+ eth->soc->init_data(eth->soc, eth->netdev[id]);
+
+ eth->netdev[id]->vlan_features = eth->soc->hw_features &
+ ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
+ eth->netdev[id]->features |= eth->soc->hw_features;
+
+ if (mtk_reg_table[MTK_REG_MTK_DMA_VID_BASE])
+ eth->netdev[id]->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
+
+ mtk_set_ethtool_ops(eth->netdev[id]);
+
+ err = register_netdev(eth->netdev[id]);
+ if (err) {
+ dev_err(eth->dev, "error bringing up device\n");
+ return err;
+ }
+ eth->netdev[id]->irq = eth->irq;
+ netif_info(eth, probe, eth->netdev[id],
+ "mediatek frame engine at 0x%08lx, irq %d\n",
+ eth->netdev[id]->base_addr, eth->netdev[id]->irq);
+
+ return 0;
+}
+
+static int mtk_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ const struct of_device_id *match;
+ struct device_node *mac_np;
+ struct mtk_soc_data *soc;
+ struct mtk_eth *eth;
+ struct clk *sysclk;
+ int err;
+
+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+
+ device_reset(&pdev->dev);
+
+ match = of_match_device(of_mtk_match, &pdev->dev);
+ soc = (struct mtk_soc_data *)match->data;
+
+ if (soc->reg_table)
+ mtk_reg_table = soc->reg_table;
+
+ eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
+ if (!eth)
+ return -ENOMEM;
+
+ eth->base = devm_ioremap_resource(&pdev->dev, res);
+ if (!eth->base)
+ return -EADDRNOTAVAIL;
+
+ spin_lock_init(ð->page_lock);
+
+ eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "mediatek,ethsys");
+ if (IS_ERR(eth->ethsys))
+ return PTR_ERR(eth->ethsys);
+
+ eth->irq = platform_get_irq(pdev, 0);
+ if (eth->irq < 0) {
+ dev_err(&pdev->dev, "no IRQ resource found\n");
+ return -ENXIO;
+ }
+
+ sysclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(sysclk)) {
+ dev_err(&pdev->dev,
+ "the clock is not defined in the devictree\n");
+ return -ENXIO;
+ }
+ eth->sysclk = clk_get_rate(sysclk);
+
+ eth->switch_np = of_parse_phandle(pdev->dev.of_node,
+ "mediatek,switch", 0);
+ if (soc->has_switch && !eth->switch_np) {
+ dev_err(&pdev->dev, "failed to read switch phandle\n");
+ return -ENODEV;
+ }
+
+ eth->dev = &pdev->dev;
+ eth->soc = soc;
+ eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
+
+ err = mtk_init_hw(eth);
+ if (err)
+ return err;
+
+ if (eth->soc->mac_count > 1) {
+ for_each_child_of_node(pdev->dev.of_node, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+ "mediatek,eth-mac"))
+ continue;
+
+ if (!of_device_is_available(mac_np))
+ continue;
+
+ err = mtk_add_mac(eth, mac_np);
+ if (err)
+ goto err_free_dev;
+ }
+
+ init_dummy_netdev(ð->dummy_dev);
+ netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_poll,
+ soc->napi_weight);
+ } else {
+ err = mtk_add_mac(eth, pdev->dev.of_node);
+ if (err)
+ goto err_free_dev;
+ netif_napi_add(eth->netdev[0], ð->rx_napi, mtk_poll,
+ soc->napi_weight);
+ }
+
+ platform_set_drvdata(pdev, eth);
+
+ return 0;
+
+err_free_dev:
+ mtk_cleanup(eth);
+ return err;
+}
+
+static int mtk_remove(struct platform_device *pdev)
+{
+ struct mtk_eth *eth = platform_get_drvdata(pdev);
+
+ netif_napi_del(ð->rx_napi);
+ mtk_cleanup(eth);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver mtk_driver = {
+ .probe = mtk_probe,
+ .remove = mtk_remove,
+ .driver = {
+ .name = "mtk_soc_eth",
+ .owner = THIS_MODULE,
+ .of_match_table = of_mtk_match,
+ },
+};
+
+module_platform_driver(mtk_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
new file mode 100644
index 0000000..2822a2f
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -0,0 +1,720 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef MTK_ETH_H
+#define MTK_ETH_H
+
+#include <linux/mii.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/dma-mapping.h>
+#include <linux/phy.h>
+#include <linux/ethtool.h>
+#include <linux/version.h>
+#include <linux/atomic.h>
+
+/* these registers have different offsets depending on the SoC. we use a lookup
+ * table for these
+ */
+enum mtk_reg {
+ MTK_REG_PDMA_GLO_CFG = 0,
+ MTK_REG_PDMA_RST_CFG,
+ MTK_REG_DLY_INT_CFG,
+ MTK_REG_TX_BASE_PTR0,
+ MTK_REG_TX_MAX_CNT0,
+ MTK_REG_TX_CTX_IDX0,
+ MTK_REG_TX_DTX_IDX0,
+ MTK_REG_RX_BASE_PTR0,
+ MTK_REG_RX_MAX_CNT0,
+ MTK_REG_RX_CALC_IDX0,
+ MTK_REG_RX_DRX_IDX0,
+ MTK_REG_MTK_INT_ENABLE,
+ MTK_REG_MTK_INT_STATUS,
+ MTK_REG_MTK_DMA_VID_BASE,
+ MTK_REG_MTK_COUNTER_BASE,
+ MTK_REG_MTK_RST_GL,
+ MTK_REG_MTK_INT_STATUS2,
+ MTK_REG_COUNT
+};
+
+/* delayed interrupt bits */
+#define MTK_DELAY_EN_INT 0x80
+#define MTK_DELAY_MAX_INT 0x04
+#define MTK_DELAY_MAX_TOUT 0x04
+#define MTK_DELAY_TIME 20
+#define MTK_DELAY_CHAN (((MTK_DELAY_EN_INT | MTK_DELAY_MAX_INT) << 8) \
+ | MTK_DELAY_MAX_TOUT)
+#define MTK_DELAY_INIT ((MTK_DELAY_CHAN << 16) | MTK_DELAY_CHAN)
+#define MTK_PSE_FQFC_CFG_INIT 0x80504000
+#define MTK_PSE_FQFC_CFG_256Q 0xff908000
+
+/* interrupt bits */
+#define MTK_CNT_PPE_AF BIT(31)
+#define MTK_CNT_GDM_AF BIT(29)
+#define MTK_PSE_P2_FC BIT(26)
+#define MTK_PSE_BUF_DROP BIT(24)
+#define MTK_GDM_OTHER_DROP BIT(23)
+#define MTK_PSE_P1_FC BIT(22)
+#define MTK_PSE_P0_FC BIT(21)
+#define MTK_PSE_FQ_EMPTY BIT(20)
+#define MTK_GE1_STA_CHG BIT(18)
+#define MTK_TX_COHERENT BIT(17)
+#define MTK_RX_COHERENT BIT(16)
+#define MTK_TX_DONE_INT3 BIT(11)
+#define MTK_TX_DONE_INT2 BIT(10)
+#define MTK_TX_DONE_INT1 BIT(9)
+#define MTK_TX_DONE_INT0 BIT(8)
+#define MTK_RX_DONE_INT0 BIT(2)
+#define MTK_TX_DLY_INT BIT(1)
+#define MTK_RX_DLY_INT BIT(0)
+
+#define MTK_RX_DONE_INT MTK_RX_DONE_INT0
+#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
+ MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
+
+#define RT5350_RX_DLY_INT BIT(30)
+#define RT5350_TX_DLY_INT BIT(28)
+#define RT5350_RX_DONE_INT1 BIT(17)
+#define RT5350_RX_DONE_INT0 BIT(16)
+#define RT5350_TX_DONE_INT3 BIT(3)
+#define RT5350_TX_DONE_INT2 BIT(2)
+#define RT5350_TX_DONE_INT1 BIT(1)
+#define RT5350_TX_DONE_INT0 BIT(0)
+
+#define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
+#define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
+ RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
+
+/* registers */
+#define MTK_GDMA_OFFSET 0x0020
+#define MTK_PSE_OFFSET 0x0040
+#define MTK_GDMA2_OFFSET 0x0060
+#define MTK_CDMA_OFFSET 0x0080
+#define MTK_DMA_VID0 0x00a8
+#define MTK_PDMA_OFFSET 0x0100
+#define MTK_PPE_OFFSET 0x0200
+#define MTK_CMTABLE_OFFSET 0x0400
+#define MTK_POLICYTABLE_OFFSET 0x1000
+
+#define MT7621_GDMA_OFFSET 0x0500
+#define MT7620_GDMA_OFFSET 0x0600
+
+#define RT5350_PDMA_OFFSET 0x0800
+#define RT5350_SDM_OFFSET 0x0c00
+
+#define MTK_MDIO_ACCESS 0x00
+#define MTK_MDIO_CFG 0x04
+#define MTK_GLO_CFG 0x08
+#define MTK_RST_GL 0x0C
+#define MTK_INT_STATUS 0x10
+#define MTK_INT_ENABLE 0x14
+#define MTK_MDIO_CFG2 0x18
+#define MTK_FOC_TS_T 0x1C
+
+#define MTK_GDMA1_FWD_CFG (MTK_GDMA_OFFSET + 0x00)
+#define MTK_GDMA1_SCH_CFG (MTK_GDMA_OFFSET + 0x04)
+#define MTK_GDMA1_SHPR_CFG (MTK_GDMA_OFFSET + 0x08)
+#define MTK_GDMA1_MAC_ADRL (MTK_GDMA_OFFSET + 0x0C)
+#define MTK_GDMA1_MAC_ADRH (MTK_GDMA_OFFSET + 0x10)
+
+#define MTK_GDMA2_FWD_CFG (MTK_GDMA2_OFFSET + 0x00)
+#define MTK_GDMA2_SCH_CFG (MTK_GDMA2_OFFSET + 0x04)
+#define MTK_GDMA2_SHPR_CFG (MTK_GDMA2_OFFSET + 0x08)
+#define MTK_GDMA2_MAC_ADRL (MTK_GDMA2_OFFSET + 0x0C)
+#define MTK_GDMA2_MAC_ADRH (MTK_GDMA2_OFFSET + 0x10)
+
+#define MTK_PSE_FQ_CFG (MTK_PSE_OFFSET + 0x00)
+#define MTK_CDMA_FC_CFG (MTK_PSE_OFFSET + 0x04)
+#define MTK_GDMA1_FC_CFG (MTK_PSE_OFFSET + 0x08)
+#define MTK_GDMA2_FC_CFG (MTK_PSE_OFFSET + 0x0C)
+
+#define MTK_CDMA_CSG_CFG (MTK_CDMA_OFFSET + 0x00)
+#define MTK_CDMA_SCH_CFG (MTK_CDMA_OFFSET + 0x04)
+
+#define MT7621_GDMA_FWD_CFG(x) (MT7621_GDMA_OFFSET + (x * 0x1000))
+
+#define MT7620_GDMA1_FWD_CFG (MT7620_GDMA_OFFSET + 0x00)
+
+#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
+#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
+#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
+#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
+#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
+#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
+#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
+#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
+#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
+#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
+#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
+#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
+#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
+#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
+#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
+#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
+#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
+#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
+#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
+#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
+#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
+#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
+#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
+#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
+#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
+#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
+#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
+#define RT5350_MTK_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
+#define RT5350_MTK_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
+#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
+
+#define MTK_PDMA_GLO_CFG (MTK_PDMA_OFFSET + 0x00)
+#define MTK_PDMA_RST_CFG (MTK_PDMA_OFFSET + 0x04)
+#define MTK_PDMA_SCH_CFG (MTK_PDMA_OFFSET + 0x08)
+#define MTK_DLY_INT_CFG (MTK_PDMA_OFFSET + 0x0C)
+#define MTK_TX_BASE_PTR0 (MTK_PDMA_OFFSET + 0x10)
+#define MTK_TX_MAX_CNT0 (MTK_PDMA_OFFSET + 0x14)
+#define MTK_TX_CTX_IDX0 (MTK_PDMA_OFFSET + 0x18)
+#define MTK_TX_DTX_IDX0 (MTK_PDMA_OFFSET + 0x1C)
+#define MTK_TX_BASE_PTR1 (MTK_PDMA_OFFSET + 0x20)
+#define MTK_TX_MAX_CNT1 (MTK_PDMA_OFFSET + 0x24)
+#define MTK_TX_CTX_IDX1 (MTK_PDMA_OFFSET + 0x28)
+#define MTK_TX_DTX_IDX1 (MTK_PDMA_OFFSET + 0x2C)
+#define MTK_RX_BASE_PTR0 (MTK_PDMA_OFFSET + 0x30)
+#define MTK_RX_MAX_CNT0 (MTK_PDMA_OFFSET + 0x34)
+#define MTK_RX_CALC_IDX0 (MTK_PDMA_OFFSET + 0x38)
+#define MTK_RX_DRX_IDX0 (MTK_PDMA_OFFSET + 0x3C)
+#define MTK_TX_BASE_PTR2 (MTK_PDMA_OFFSET + 0x40)
+#define MTK_TX_MAX_CNT2 (MTK_PDMA_OFFSET + 0x44)
+#define MTK_TX_CTX_IDX2 (MTK_PDMA_OFFSET + 0x48)
+#define MTK_TX_DTX_IDX2 (MTK_PDMA_OFFSET + 0x4C)
+#define MTK_TX_BASE_PTR3 (MTK_PDMA_OFFSET + 0x50)
+#define MTK_TX_MAX_CNT3 (MTK_PDMA_OFFSET + 0x54)
+#define MTK_TX_CTX_IDX3 (MTK_PDMA_OFFSET + 0x58)
+#define MTK_TX_DTX_IDX3 (MTK_PDMA_OFFSET + 0x5C)
+#define MTK_RX_BASE_PTR1 (MTK_PDMA_OFFSET + 0x60)
+#define MTK_RX_MAX_CNT1 (MTK_PDMA_OFFSET + 0x64)
+#define MTK_RX_CALC_IDX1 (MTK_PDMA_OFFSET + 0x68)
+#define MTK_RX_DRX_IDX1 (MTK_PDMA_OFFSET + 0x6C)
+
+/* Switch DMA configuration */
+#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00)
+#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04)
+#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08)
+#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C)
+#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10)
+#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100)
+#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104)
+#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108)
+#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C)
+#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110)
+
+#define RT5350_SDM_ICS_EN BIT(16)
+#define RT5350_SDM_TCS_EN BIT(17)
+#define RT5350_SDM_UCS_EN BIT(18)
+
+/* QDMA registers */
+#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
+#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
+#define MTK_QRX_BASE_PTR0 0x1900
+#define MTK_QRX_MAX_CNT0 0x1904
+#define MTK_QRX_CRX_IDX0 0x1908
+#define MTK_QRX_DRX_IDX0 0x190C
+#define MTK_QDMA_GLO_CFG 0x1A04
+#define MTK_QDMA_RST_IDX 0x1A08
+#define MTK_QDMA_DELAY_INT 0x1A0C
+#define MTK_QDMA_FC_THRES 0x1A10
+#define MTK_QMTK_INT_STATUS 0x1A18
+#define MTK_QMTK_INT_ENABLE 0x1A1C
+#define MTK_QDMA_HRED2 0x1A44
+
+#define MTK_QTX_CTX_PTR 0x1B00
+#define MTK_QTX_DTX_PTR 0x1B04
+
+#define MTK_QTX_CRX_PTR 0x1B10
+#define MTK_QTX_DRX_PTR 0x1B14
+
+#define MTK_QDMA_FQ_HEAD 0x1B20
+#define MTK_QDMA_FQ_TAIL 0x1B24
+#define MTK_QDMA_FQ_CNT 0x1B28
+#define MTK_QDMA_FQ_BLEN 0x1B2C
+
+#define QDMA_PAGE_SIZE 2048
+#define QDMA_TX_OWNER_CPU BIT(31)
+#define QDMA_TX_SWC BIT(14)
+#define TX_QDMA_SDL(_x) (((_x) & 0x3fff) << 16)
+#define QDMA_RES_THRES 4
+
+/* MDIO_CFG register bits */
+#define MTK_MDIO_CFG_AUTO_POLL_EN BIT(29)
+#define MTK_MDIO_CFG_GP1_BP_EN BIT(16)
+#define MTK_MDIO_CFG_GP1_FRC_EN BIT(15)
+#define MTK_MDIO_CFG_GP1_SPEED_10 (0 << 13)
+#define MTK_MDIO_CFG_GP1_SPEED_100 (1 << 13)
+#define MTK_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
+#define MTK_MDIO_CFG_GP1_DUPLEX BIT(12)
+#define MTK_MDIO_CFG_GP1_FC_TX BIT(11)
+#define MTK_MDIO_CFG_GP1_FC_RX BIT(10)
+#define MTK_MDIO_CFG_GP1_LNK_DWN BIT(9)
+#define MTK_MDIO_CFG_GP1_AN_FAIL BIT(8)
+#define MTK_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
+#define MTK_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
+#define MTK_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
+#define MTK_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
+#define MTK_MDIO_CFG_TURBO_MII_FREQ BIT(5)
+#define MTK_MDIO_CFG_TURBO_MII_MODE BIT(4)
+#define MTK_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
+#define MTK_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
+#define MTK_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
+#define MTK_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
+#define MTK_MDIO_CFG_TX_CLK_SKEW_0 0
+#define MTK_MDIO_CFG_TX_CLK_SKEW_200 1
+#define MTK_MDIO_CFG_TX_CLK_SKEW_400 2
+#define MTK_MDIO_CFG_TX_CLK_SKEW_INV 3
+
+/* uni-cast port */
+#define MTK_GDM1_JMB_LEN_MASK 0xf
+#define MTK_GDM1_JMB_LEN_SHIFT 28
+#define MTK_GDM1_ICS_EN BIT(22)
+#define MTK_GDM1_TCS_EN BIT(21)
+#define MTK_GDM1_UCS_EN BIT(20)
+#define MTK_GDM1_JMB_EN BIT(19)
+#define MTK_GDM1_STRPCRC BIT(16)
+#define MTK_GDM1_UFRC_P_CPU (0 << 12)
+#define MTK_GDM1_UFRC_P_GDMA1 (1 << 12)
+#define MTK_GDM1_UFRC_P_PPE (6 << 12)
+
+/* checksums */
+#define MTK_ICS_GEN_EN BIT(2)
+#define MTK_UCS_GEN_EN BIT(1)
+#define MTK_TCS_GEN_EN BIT(0)
+
+/* dma mode */
+#define MTK_PDMA BIT(0)
+#define MTK_QDMA BIT(1)
+#define MTK_PDMA_RX_QDMA_TX (MTK_PDMA | MTK_QDMA)
+
+/* dma ring */
+#define MTK_PST_DRX_IDX0 BIT(16)
+#define MTK_PST_DTX_IDX3 BIT(3)
+#define MTK_PST_DTX_IDX2 BIT(2)
+#define MTK_PST_DTX_IDX1 BIT(1)
+#define MTK_PST_DTX_IDX0 BIT(0)
+
+#define MTK_RX_2B_OFFSET BIT(31)
+#define MTK_TX_WB_DDONE BIT(6)
+#define MTK_RX_DMA_BUSY BIT(3)
+#define MTK_TX_DMA_BUSY BIT(1)
+#define MTK_RX_DMA_EN BIT(2)
+#define MTK_TX_DMA_EN BIT(0)
+
+#define MTK_PDMA_SIZE_4DWORDS (0 << 4)
+#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
+#define MTK_PDMA_SIZE_16DWORDS (2 << 4)
+
+#define MTK_US_CYC_CNT_MASK 0xff
+#define MTK_US_CYC_CNT_SHIFT 0x8
+#define MTK_US_CYC_CNT_DIVISOR 1000000
+
+/* PDMA descriptor rxd2 */
+#define RX_DMA_DONE BIT(31)
+#define RX_DMA_LSO BIT(30)
+#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
+#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
+#define RX_DMA_TAG BIT(15)
+
+/* PDMA descriptor rxd3 */
+#define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff)
+#define RX_DMA_VID(_x) ((_x) & 0xfff)
+
+/* PDMA descriptor rxd4 */
+#define RX_DMA_L4VALID BIT(30)
+#define RX_DMA_FPORT_SHIFT 19
+#define RX_DMA_FPORT_MASK 0x7
+
+struct mtk_rx_dma {
+ unsigned int rxd1;
+ unsigned int rxd2;
+ unsigned int rxd3;
+ unsigned int rxd4;
+} __packed __aligned(4);
+
+/* PDMA tx descriptor bits */
+#define TX_DMA_BUF_LEN 0x3fff
+#define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
+#define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
+#define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
+#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN)
+#define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
+#define TX_DMA_LS1 BIT(14)
+#define TX_DMA_LS0 BIT(30)
+#define TX_DMA_DONE BIT(31)
+#define TX_DMA_FPORT_SHIFT 25
+#define TX_DMA_FPORT_MASK 0x7
+#define TX_DMA_INS_VLAN_MT7621 BIT(16)
+#define TX_DMA_INS_VLAN BIT(7)
+#define TX_DMA_INS_PPPOE BIT(12)
+#define TX_DMA_TAG BIT(15)
+#define TX_DMA_TAG_MASK BIT(15)
+#define TX_DMA_QN(_x) ((_x) << 16)
+#define TX_DMA_PN(_x) ((_x) << 24)
+#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
+#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
+#define TX_DMA_UDF BIT(20)
+#define TX_DMA_CHKSUM (0x7 << 29)
+#define TX_DMA_TSO BIT(28)
+#define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
+
+/* frame engine counters */
+#define MTK_PPE_AC_BCNT0 (MTK_CMTABLE_OFFSET + 0x00)
+#define MTK_GDMA1_TX_GBCNT (MTK_CMTABLE_OFFSET + 0x300)
+#define MTK_GDMA2_TX_GBCNT (MTK_GDMA1_TX_GBCNT + 0x40)
+
+/* phy device flags */
+#define MTK_PHY_FLAG_PORT BIT(0)
+#define MTK_PHY_FLAG_ATTACH BIT(1)
+
+struct mtk_tx_dma {
+ unsigned int txd1;
+ unsigned int txd2;
+ unsigned int txd3;
+ unsigned int txd4;
+} __packed __aligned(4);
+
+struct mtk_eth;
+struct mtk_mac;
+
+/* manage the attached phys */
+struct mtk_phy {
+ spinlock_t lock;
+
+ struct phy_device *phy[8];
+ struct device_node *phy_node[8];
+ const __be32 *phy_fixed[8];
+ int duplex[8];
+ int speed[8];
+ int tx_fc[8];
+ int rx_fc[8];
+ int (*connect)(struct mtk_mac *mac);
+ void (*disconnect)(struct mtk_mac *mac);
+ void (*start)(struct mtk_mac *mac);
+ void (*stop)(struct mtk_mac *mac);
+};
+
+/* struct mtk_soc_data - the structure that holds the SoC specific data
+ * @reg_table: Some of the legacy registers changed their location
+ * over time. Their offsets are stored in this table
+ *
+ * @init_data: Some features depend on the silicon revision. This
+ * callback allows runtime modification of the content of
+ * this struct
+ * @reset_fe: This callback is used to trigger the reset of the frame
+ * engine
+ * @set_mac: This callback is used to set the unicast mac address
+ * filter
+ * @fwd_config: This callback is used to setup the forward config
+ * register of the MAC
+ * @switch_init: This callback is used to bring up the switch core
+ * @port_init: Some SoCs have ports that can be router to a switch port
+ * or an external PHY. This callback is used to setup these
+ * ports.
+ * @has_carrier: This callback allows driver to check if there is a cable
+ * attached.
+ * @mdio_init: This callbck is used to setup the MDIO bus if one is
+ * present
+ * @mdio_cleanup: This callback is used to cleanup the MDIO state.
+ * @mdio_write: This callback is used to write data to the MDIO bus.
+ * @mdio_read: This callback is used to write data to the MDIO bus.
+ * @mdio_adjust_link: This callback is used to apply the PHY settings.
+ * @piac_offset: the PIAC register has a different different base offset
+ * @hw_features: feature set depends on the SoC type
+ * @dma_ring_size: allow GBit SoCs to set bigger rings than FE SoCs
+ * @napi_weight: allow GBit SoCs to set bigger napi weight than FE SoCs
+ * @dma_type: SoCs is PDMA, QDMA or a mix of the 2
+ * @pdma_glo_cfg: the default DMA configuration
+ * @rx_int: the TX interrupt bits used by the SoC
+ * @tx_int: the TX interrupt bits used by the SoC
+ * @status_int: the Status interrupt bits used by the SoC
+ * @checksum_bit: the bits used to turn on HW checksumming
+ * @txd4: default value of the TXD4 descriptor
+ * @mac_count: the number of MACs that the SoC has
+ * @new_stats: there is a old and new way to read hardware stats
+ * registers
+ * @jumbo_frame: does the SoC support jumbo frames ?
+ * @rx_2b_offset: tell the rx dma to offset the data by 2 bytes
+ * @rx_sg_dma: scatter gather support
+ * @padding_64b enable 64 bit padding
+ * @padding_bug: rt2880 has a padding bug
+ * @has_switch: does the SoC have a built-in switch
+ *
+ * Although all of the supported SoCs share the same basic functionality, there
+ * are several SoC specific functions and features that we need to support. This
+ * struct holds the SoC specific data so that the common core can figure out
+ * how to setup and use these differences.
+ */
+struct mtk_soc_data {
+ const u16 *reg_table;
+
+ void (*init_data)(struct mtk_soc_data *data, struct net_device *netdev);
+ void (*reset_fe)(struct mtk_eth *eth);
+ void (*set_mac)(struct mtk_mac *mac, unsigned char *macaddr);
+ int (*fwd_config)(struct mtk_eth *eth);
+ int (*switch_init)(struct mtk_eth *eth);
+ void (*port_init)(struct mtk_eth *eth, struct mtk_mac *mac,
+ struct device_node *port);
+ int (*has_carrier)(struct mtk_eth *eth);
+ int (*mdio_init)(struct mtk_eth *eth);
+ void (*mdio_cleanup)(struct mtk_eth *eth);
+ int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg,
+ u16 val);
+ int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
+ void (*mdio_adjust_link)(struct mtk_eth *eth, int port);
+ u32 piac_offset;
+ netdev_features_t hw_features;
+ u32 dma_ring_size;
+ u32 napi_weight;
+ u32 dma_type;
+ u32 pdma_glo_cfg;
+ u32 rx_int;
+ u32 tx_int;
+ u32 status_int;
+ u32 checksum_bit;
+ u32 txd4;
+ u32 mac_count;
+
+ u32 new_stats:1;
+ u32 jumbo_frame:1;
+ u32 rx_2b_offset:1;
+ u32 rx_sg_dma:1;
+ u32 padding_64b:1;
+ u32 padding_bug:1;
+ u32 has_switch:1;
+};
+
+/* ugly macro hack to make sure hw_stats and ethtool strings are consistent */
+#define MTK_STAT_OFFSET 0x40
+#define MTK_STAT_REG_DECLARE \
+ _FE(tx_bytes) \
+ _FE(tx_packets) \
+ _FE(tx_skip) \
+ _FE(tx_collisions) \
+ _FE(rx_bytes) \
+ _FE(rx_packets) \
+ _FE(rx_overflow) \
+ _FE(rx_fcs_errors) \
+ _FE(rx_short_errors) \
+ _FE(rx_long_errors) \
+ _FE(rx_checksum_errors) \
+ _FE(rx_flow_control_packets)
+
+/* struct mtk_hw_stats - the structure that holds the traffic statistics.
+ * @stats_lock: make sure that stats operations are atomic
+ * @reg_offset: the status register offset of the SoC
+ * @syncp: the refcount
+ *
+ * All of the supported SoCs have hardware counters for traffic statstics.
+ * Whenever the status IRQ triggers we can read the latest stats from these
+ * counters and store them in this struct.
+ */
+struct mtk_hw_stats {
+ spinlock_t stats_lock;
+ u32 reg_offset;
+ struct u64_stats_sync syncp;
+
+#define _FE(x) u64 x;
+ MTK_STAT_REG_DECLARE
+#undef _FE
+};
+
+/* PDMA descriptor can point at 1-2 segments. This enum allows us to track how
+ * memory was allocated so that it can be freed properly
+ */
+enum mtk_tx_flags {
+ MTK_TX_FLAGS_SINGLE0 = 0x01,
+ MTK_TX_FLAGS_PAGE0 = 0x02,
+ MTK_TX_FLAGS_PAGE1 = 0x04,
+};
+
+/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
+ * by the TX descriptor s
+ * @skb: The SKB pointer of the packet being sent
+ * @dma_addr0: The base addr of the first segment
+ * @dma_len0: The length of the first segment
+ * @dma_addr1: The base addr of the second segment
+ * @dma_len1: The length of the second segment
+ */
+struct mtk_tx_buf {
+ struct sk_buff *skb;
+ u32 flags;
+ DEFINE_DMA_UNMAP_ADDR(dma_addr0);
+ DEFINE_DMA_UNMAP_LEN(dma_len0);
+ DEFINE_DMA_UNMAP_ADDR(dma_addr1);
+ DEFINE_DMA_UNMAP_LEN(dma_len1);
+};
+
+/* struct mtk_tx_ring - This struct holds info describing a TX ring
+ * @tx_dma: The descriptor ring
+ * @tx_buf: The memory pointed at by the ring
+ * @tx_phys: The physical addr of tx_buf
+ * @tx_next_free: Pointer to the next free descriptor
+ * @tx_last_free: Pointer to the last free descriptor
+ * @tx_thresh: The threshold of minimum amount of free descriptors
+ * @tx_map: Callback to map a new packet into the ring
+ * @tx_poll: Callback for the housekeeping function
+ * @tx_clean: Callback for the cleanup function
+ * @tx_ring_size: How many descriptors are in the ring
+ * @tx_free_idx: The index of th next free descriptor
+ * @tx_next_idx: QDMA uses a linked list. This element points to the next
+ * free descriptor in the list
+ * @tx_free_count: QDMA uses a linked list. Track how many free descriptors
+ * are present
+ */
+struct mtk_tx_ring {
+ struct mtk_tx_dma *tx_dma;
+ struct mtk_tx_buf *tx_buf;
+ dma_addr_t tx_phys;
+ struct mtk_tx_dma *tx_next_free;
+ struct mtk_tx_dma *tx_last_free;
+ u16 tx_thresh;
+ int (*tx_map)(struct sk_buff *skb, struct net_device *dev, int tx_num,
+ struct mtk_tx_ring *ring, bool gso);
+ int (*tx_poll)(struct mtk_eth *eth, int budget, bool *tx_again);
+ void (*tx_clean)(struct mtk_eth *eth);
+
+ /* PDMA only */
+ u16 tx_ring_size;
+ u16 tx_free_idx;
+
+ /* QDMA only */
+ u16 tx_next_idx;
+ atomic_t tx_free_count;
+};
+
+/* struct mtk_rx_ring - This struct holds info describing a RX ring
+ * @rx_dma: The descriptor ring
+ * @rx_data: The memory pointed at by the ring
+ * @trx_phys: The physical addr of rx_buf
+ * @rx_ring_size: How many descriptors are in the ring
+ * @rx_buf_size: The size of each packet buffer
+ * @rx_calc_idx: The current head of ring
+ */
+struct mtk_rx_ring {
+ struct mtk_rx_dma *rx_dma;
+ u8 **rx_data;
+ dma_addr_t rx_phys;
+ u16 rx_ring_size;
+ u16 frag_size;
+ u16 rx_buf_size;
+ u16 rx_calc_idx;
+};
+
+/* currently no SoC has more than 2 macs */
+#define MTK_MAX_DEVS 2
+
+/* struct mtk_eth - This is the main datasructure for holding the state
+ * of the driver
+ * @dev: The device pointer
+ * @base: The mapped register i/o base
+ * @page_lock: Make sure that register operations are atomic
+ * @soc: pointer to our SoC specific data
+ * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
+ * dummy for NAPI to work
+ * @netdev: The netdev instances
+ * @mac: Each netdev is linked to a physical MAC
+ * @switch_np: The phandle for the switch
+ * @irq: The IRQ that we are using
+ * @msg_enable: Ethtool msg level
+ * @ysclk: The sysclk rate - neeed for calibration
+ * @ethsys: The register map pointing at the range used to setup
+ * MII modes
+ * @dma_refcnt: track how many netdevs are using the DMA engine
+ * @tx_ring: Pointer to the memore holding info about the TX ring
+ * @rx_ring: Pointer to the memore holding info about the RX ring
+ * @rx_napi: The NAPI struct
+ * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
+ * @scratch_head: The scratch memory that scratch_ring points to.
+ * @phy: Info about the attached PHYs
+ * @mii_bus: If there is a bus we need to create an instance for it
+ * @link: Track if the ports have a physical link
+ * @sw_priv: Pointer to the switches private data
+ * @vlan_map: RX VID tracking
+ */
+
+struct mtk_eth {
+ struct device *dev;
+ void __iomem *base;
+ spinlock_t page_lock;
+ struct mtk_soc_data *soc;
+ struct net_device dummy_dev;
+ struct net_device *netdev[MTK_MAX_DEVS];
+ struct mtk_mac *mac[MTK_MAX_DEVS];
+ struct device_node *switch_np;
+ int irq;
+ u32 msg_enable;
+ unsigned long sysclk;
+ struct regmap *ethsys;
+ atomic_t dma_refcnt;
+ struct mtk_tx_ring tx_ring;
+ struct mtk_rx_ring rx_ring[2];
+ struct napi_struct rx_napi;
+ struct mtk_tx_dma *scratch_ring;
+ void *scratch_head;
+ struct mtk_phy *phy;
+ struct mii_bus *mii_bus;
+ int link[8];
+ void *sw_priv;
+ unsigned long vlan_map;
+};
+
+/* struct mtk_mac - the structure that holds the info about the MACs of the
+ * SoC
+ * @id: The number of the MAC
+ * @of_node: Our devicetree node
+ * @hw: Backpointer to our main datastruture
+ * @hw_stats: Packet statistics counter
+ * @phy_dev: The attached PHY if available
+ * @phy_flags: The PHYs flags
+ * @pending_work: The workqueue used to reset the dma ring
+ */
+struct mtk_mac {
+ int id;
+ struct device_node *of_node;
+ struct mtk_eth *hw;
+ struct mtk_hw_stats *hw_stats;
+ struct phy_device *phy_dev;
+ u32 phy_flags;
+ struct work_struct pending_work;
+};
+
+/* the struct describing the SoC. these are declared in the soc_xyz.c files */
+extern const struct of_device_id of_mtk_match[];
+
+/* read the hardware status register */
+void mtk_stats_update_mac(struct mtk_mac *mac);
+
+/* default checksum setup handler */
+void mtk_reset(struct mtk_eth *eth, u32 reset_bits);
+
+/* register i/o wrappers */
+void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
+u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
+
+/* default clock calibration handler */
+int mtk_set_clock_cycle(struct mtk_eth *eth);
+
+/* default checksum setup handler */
+void mtk_csum_config(struct mtk_eth *eth);
+
+/* default forward config handler */
+void mtk_fwd_config(struct mtk_eth *eth);
+
+#endif /* MTK_ETH_H */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
2016-02-26 14:21 ` [PATCH V2 01/12] net-next: mediatek: Document ralink/mediatek SoC ethernet binding John Crispin
2016-02-26 14:21 ` [PATCH V2 02/12] net-next: mediatek: add the drivers core files John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 15:18 ` Andrew Lunn
2016-02-26 14:21 ` [PATCH V2 04/12] net-next: mediatek: add gigabit switch driver (GSW) John Crispin
` (8 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin
The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
external ports, 1 cpu port and 1 further port that the internal HW
offloading engine connects to.
This driver is very basic and only provides basic init and irq support.
The SoC and switch core both have support for a special tag making DSA
support possible.
I have managed to work out all the names of the registers of the ESW,
however the init for the phys uses lots of voodoo magic which is based
on the SDK driver code. It will be hard to find out the real names for
the phy registers and their bits.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/ethernet/mediatek/esw_rt3050.c | 642 ++++++++++++++++++++++++++++
drivers/net/ethernet/mediatek/esw_rt3050.h | 21 +
2 files changed, 663 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/esw_rt3050.c
create mode 100644 drivers/net/ethernet/mediatek/esw_rt3050.h
diff --git a/drivers/net/ethernet/mediatek/esw_rt3050.c b/drivers/net/ethernet/mediatek/esw_rt3050.c
new file mode 100644
index 0000000..8da4bec
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/esw_rt3050.c
@@ -0,0 +1,642 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include "mtk_eth_soc.h"
+
+/* HW limitations for this switch:
+ * - No large frame support (PKT_MAX_LEN at most 1536)
+ * - Can't have untagged vlan and tagged vlan on one port at the same time,
+ * though this might be possible using the undocumented PPE.
+ */
+
+#define RT305X_ESW_REG_ISR 0x00
+#define RT305X_ESW_REG_IMR 0x04
+#define RT305X_ESW_REG_FCT0 0x08
+#define RT305X_ESW_REG_PFC1 0x14
+#define RT305X_ESW_REG_ATS 0x24
+#define RT305X_ESW_REG_ATS0 0x28
+#define RT305X_ESW_REG_ATS1 0x2c
+#define RT305X_ESW_REG_ATS2 0x30
+#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
+#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
+#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
+#define RT305X_ESW_REG_POA 0x80
+#define RT305X_ESW_REG_FPA 0x84
+#define RT305X_ESW_REG_SOCPC 0x8c
+#define RT305X_ESW_REG_POC0 0x90
+#define RT305X_ESW_REG_POC1 0x94
+#define RT305X_ESW_REG_POC2 0x98
+#define RT305X_ESW_REG_SGC 0x9c
+#define RT305X_ESW_REG_STRT 0xa0
+#define RT305X_ESW_REG_PCR0 0xc0
+#define RT305X_ESW_REG_PCR1 0xc4
+#define RT305X_ESW_REG_FPA2 0xc8
+#define RT305X_ESW_REG_FCT2 0xcc
+#define RT305X_ESW_REG_SGC2 0xe4
+#define RT305X_ESW_REG_P0LED 0xa4
+#define RT305X_ESW_REG_P1LED 0xa8
+#define RT305X_ESW_REG_P2LED 0xac
+#define RT305X_ESW_REG_P3LED 0xb0
+#define RT305X_ESW_REG_P4LED 0xb4
+#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
+#define RT305X_ESW_REG_P1PC 0xec
+#define RT305X_ESW_REG_P2PC 0xf0
+#define RT305X_ESW_REG_P3PC 0xf4
+#define RT305X_ESW_REG_P4PC 0xf8
+#define RT305X_ESW_REG_P5PC 0xfc
+
+#define RT305X_ESW_LED_LINK 0
+#define RT305X_ESW_LED_100M 1
+#define RT305X_ESW_LED_DUPLEX 2
+#define RT305X_ESW_LED_ACTIVITY 3
+#define RT305X_ESW_LED_COLLISION 4
+#define RT305X_ESW_LED_LINKACT 5
+#define RT305X_ESW_LED_DUPLCOLL 6
+#define RT305X_ESW_LED_10MACT 7
+#define RT305X_ESW_LED_100MACT 8
+/* Additional led states not in datasheet: */
+#define RT305X_ESW_LED_BLINK 10
+#define RT305X_ESW_LED_ON 12
+
+#define RT305X_ESW_LINK_S 25
+#define RT305X_ESW_DUPLEX_S 9
+#define RT305X_ESW_SPD_S 0
+
+#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
+#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
+#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
+
+#define RT305X_ESW_PCR1_WT_DONE BIT(0)
+
+#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
+#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
+
+#define RT305X_ESW_PVIDC_PVID_M 0xfff
+#define RT305X_ESW_PVIDC_PVID_S 12
+
+#define RT305X_ESW_VLANI_VID_M 0xfff
+#define RT305X_ESW_VLANI_VID_S 12
+
+#define RT305X_ESW_VMSC_MSC_M 0xff
+#define RT305X_ESW_VMSC_MSC_S 8
+
+#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
+#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
+#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
+#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
+
+#define RT305X_ESW_POC0_EN_BP_S 0
+#define RT305X_ESW_POC0_EN_FC_S 8
+#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
+#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
+#define RT305X_ESW_POC0_DIS_PORT_S 23
+
+#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
+#define RT305X_ESW_POC2_UNTAG_EN_S 0
+#define RT305X_ESW_POC2_ENAGING_S 8
+#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
+
+#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
+#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
+#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
+#define RT305X_ESW_SGC2_LAN_PMAP_S 24
+
+#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
+#define RT305X_ESW_PFC1_EN_VLAN_S 16
+#define RT305X_ESW_PFC1_EN_TOS_S 24
+
+#define RT305X_ESW_VLAN_NONE 0xfff
+
+#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
+#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
+
+#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
+#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
+
+#define RT305X_ESW_POA_LINK_MASK 0x1f
+#define RT305X_ESW_POA_LINK_SHIFT 25
+
+#define RT305X_ESW_PORT_ST_CHG BIT(26)
+#define RT305X_ESW_PORT0 0
+#define RT305X_ESW_PORT1 1
+#define RT305X_ESW_PORT2 2
+#define RT305X_ESW_PORT3 3
+#define RT305X_ESW_PORT4 4
+#define RT305X_ESW_PORT5 5
+#define RT305X_ESW_PORT6 6
+
+#define RT305X_ESW_PMAP_LLLLLL 0x3f
+#define RT305X_ESW_PMAP_LLLLWL 0x2f
+#define RT305X_ESW_PMAP_WLLLLL 0x3e
+
+#define RT305X_ESW_PORTS_INTERNAL \
+ (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
+ BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
+ BIT(RT305X_ESW_PORT4))
+
+#define RT305X_ESW_PORTS_NOCPU \
+ (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
+
+#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
+
+#define RT305X_ESW_PORTS_ALL \
+ (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
+
+#define RT305X_ESW_NUM_PORTS 7
+#define RT305X_ESW_NUM_LEDS 5
+
+#define RT5350_EWS_REG_LED_POLARITY 0x168
+#define RT5350_RESET_EPHY BIT(24)
+
+struct esw_port {
+ bool disable;
+ u8 led;
+};
+
+struct rt305x_esw {
+ struct device *dev;
+ void __iomem *base;
+ int irq;
+
+ /* Protects against concurrent register r/w operations. */
+ spinlock_t reg_rw_lock;
+
+ unsigned char port_map;
+ unsigned int reg_led_polarity;
+
+ struct esw_port ports[RT305X_ESW_NUM_PORTS];
+
+};
+
+static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
+{
+ __raw_writel(val, esw->base + reg);
+}
+
+static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
+{
+ return __raw_readl(esw->base + reg);
+}
+
+static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
+ unsigned long mask, unsigned long val)
+{
+ unsigned long t;
+
+ t = __raw_readl(esw->base + reg) & ~mask;
+ __raw_writel(t | val, esw->base + reg);
+}
+
+static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
+ unsigned long mask, unsigned long val)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&esw->reg_rw_lock, flags);
+ esw_rmw_raw(esw, reg, mask, val);
+ spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
+}
+
+static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
+ u32 phy_register, u32 write_data)
+{
+ unsigned long t_start = jiffies;
+ int ret = 0;
+
+ while (1) {
+ if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
+ RT305X_ESW_PCR1_WT_DONE))
+ break;
+ if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
+ ret = 1;
+ goto out;
+ }
+ }
+
+ write_data &= 0xffff;
+ esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
+ (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
+ (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
+ RT305X_ESW_REG_PCR0);
+
+ t_start = jiffies;
+ while (1) {
+ if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
+ RT305X_ESW_PCR1_WT_DONE)
+ break;
+
+ if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
+ ret = 1;
+ break;
+ }
+ }
+out:
+ if (ret)
+ dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
+ return ret;
+}
+
+static unsigned esw_get_port_disable(struct rt305x_esw *esw)
+{
+ unsigned reg;
+
+ reg = esw_r32(esw, RT305X_ESW_REG_POC0);
+ return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
+ RT305X_ESW_POC0_DIS_PORT_M;
+}
+
+static void esw_hw_init(struct mtk_eth *eth, struct rt305x_esw *esw)
+{
+ int i;
+ u8 port_disable = 0;
+ u8 port_map = RT305X_ESW_PMAP_LLLLLL;
+
+ /* vodoo from original driver */
+ esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
+ esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
+ /* Port priority 1 for all ports, vlan enabled. */
+ esw_w32(esw, 0x00005555 |
+ (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
+ RT305X_ESW_REG_PFC1);
+
+ /* Enable Back Pressure, and Flow Control */
+ esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
+ (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
+ RT305X_ESW_REG_POC0);
+
+ /* Enable Aging, and VLAN TAG removal */
+ esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
+ (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
+ RT305X_ESW_REG_POC2);
+
+ esw_w32(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
+
+ /* 300s aging timer, max packet len 1536, broadcast storm prevention
+ * disabled, disable collision abort, mac xor48 hash, 10 packet back
+ * pressure jam, GMII disable was_transmit, back pressure disabled,
+ * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
+ * ports.
+ */
+ esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
+
+ /* Setup SoC Port control register */
+ esw_w32(esw,
+ (RT305X_ESW_SOCPC_CRC_PADDING |
+ (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
+ (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
+ (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
+ RT305X_ESW_REG_SOCPC);
+
+ /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
+ * turbo mii off, rgmi 3.3v off
+ * port5: disabled
+ * port6: enabled, gige, full-duplex, rx/tx-flow-control
+ */
+ esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
+ esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
+
+ /* Force Link/Activity on ports */
+ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
+ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
+ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
+ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
+ esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
+
+ /* Copy disabled port configuration from bootloader setup */
+ port_disable = esw_get_port_disable(esw);
+ for (i = 0; i < 6; i++)
+ esw->ports[i].disable = (port_disable & (1 << i)) != 0;
+
+ if (ralink_soc == RT305X_SOC_RT3352) {
+ /* reset EPHY */
+ mtk_reset(eth, RT5350_RESET_EPHY);
+
+ rt305x_mii_write(esw, 0, 31, 0x8000);
+ for (i = 0; i < 5; i++) {
+ if (esw->ports[i].disable) {
+ rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
+ } else {
+ rt305x_mii_write(esw, i, MII_BMCR,
+ BMCR_FULLDPLX |
+ BMCR_ANENABLE |
+ BMCR_SPEED100);
+ }
+ /* TX10 waveform coefficient LSB=0 disable PHY */
+ rt305x_mii_write(esw, i, 26, 0x1601);
+ /* TX100/TX10 AD/DA current bias */
+ rt305x_mii_write(esw, i, 29, 0x7016);
+ /* TX100 slew rate control */
+ rt305x_mii_write(esw, i, 30, 0x0038);
+ }
+
+ /* select global register */
+ rt305x_mii_write(esw, 0, 31, 0x0);
+ /* enlarge agcsel threshold 3 and threshold 2 */
+ rt305x_mii_write(esw, 0, 1, 0x4a40);
+ /* enlarge agcsel threshold 5 and threshold 4 */
+ rt305x_mii_write(esw, 0, 2, 0x6254);
+ /* enlarge agcsel threshold */
+ rt305x_mii_write(esw, 0, 3, 0xa17f);
+ rt305x_mii_write(esw, 0, 12, 0x7eaa);
+ /* longer TP_IDL tail length */
+ rt305x_mii_write(esw, 0, 14, 0x65);
+ /* increased squelch pulse count threshold. */
+ rt305x_mii_write(esw, 0, 16, 0x0684);
+ /* set TX10 signal amplitude threshold to minimum */
+ rt305x_mii_write(esw, 0, 17, 0x0fe0);
+ /* set squelch amplitude to higher threshold */
+ rt305x_mii_write(esw, 0, 18, 0x40ba);
+ /* tune TP_IDL tail and head waveform, enable power
+ * down slew rate control
+ */
+ rt305x_mii_write(esw, 0, 22, 0x253f);
+ /* set PLL/Receive bias current are calibrated */
+ rt305x_mii_write(esw, 0, 27, 0x2fda);
+ /* change PLL/Receive bias current to internal(RT3350) */
+ rt305x_mii_write(esw, 0, 28, 0xc410);
+ /* change PLL bias current to internal(RT3052_MP3) */
+ rt305x_mii_write(esw, 0, 29, 0x598b);
+ /* select local register */
+ rt305x_mii_write(esw, 0, 31, 0x8000);
+ } else if (ralink_soc == RT305X_SOC_RT5350) {
+ /* reset EPHY */
+ mtk_reset(eth, RT5350_RESET_EPHY);
+
+ /* set the led polarity */
+ esw_w32(esw, esw->reg_led_polarity & 0x1F,
+ RT5350_EWS_REG_LED_POLARITY);
+
+ /* local registers */
+ rt305x_mii_write(esw, 0, 31, 0x8000);
+ for (i = 0; i < 5; i++) {
+ if (esw->ports[i].disable) {
+ rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
+ } else {
+ rt305x_mii_write(esw, i, MII_BMCR,
+ BMCR_FULLDPLX |
+ BMCR_ANENABLE |
+ BMCR_SPEED100);
+ }
+ /* TX10 waveform coefficient LSB=0 disable PHY */
+ rt305x_mii_write(esw, i, 26, 0x1601);
+ /* TX100/TX10 AD/DA current bias */
+ rt305x_mii_write(esw, i, 29, 0x7015);
+ /* TX100 slew rate control */
+ rt305x_mii_write(esw, i, 30, 0x0038);
+ }
+
+ /* global registers */
+ rt305x_mii_write(esw, 0, 31, 0x0);
+ /* enlarge agcsel threshold 3 and threshold 2 */
+ rt305x_mii_write(esw, 0, 1, 0x4a40);
+ /* enlarge agcsel threshold 5 and threshold 4 */
+ rt305x_mii_write(esw, 0, 2, 0x6254);
+ /* enlarge agcsel threshold 6 */
+ rt305x_mii_write(esw, 0, 3, 0xa17f);
+ rt305x_mii_write(esw, 0, 12, 0x7eaa);
+ /* longer TP_IDL tail length */
+ rt305x_mii_write(esw, 0, 14, 0x65);
+ /* increased squelch pulse count threshold. */
+ rt305x_mii_write(esw, 0, 16, 0x0684);
+ /* set TX10 signal amplitude threshold to minimum */
+ rt305x_mii_write(esw, 0, 17, 0x0fe0);
+ /* set squelch amplitude to higher threshold */
+ rt305x_mii_write(esw, 0, 18, 0x40ba);
+ /* tune TP_IDL tail and head waveform, enable power
+ * down slew rate control
+ */
+ rt305x_mii_write(esw, 0, 22, 0x253f);
+ /* set PLL/Receive bias current are calibrated */
+ rt305x_mii_write(esw, 0, 27, 0x2fda);
+ /* change PLL/Receive bias current to internal(RT3350) */
+ rt305x_mii_write(esw, 0, 28, 0xc410);
+ /* change PLL bias current to internal(RT3052_MP3) */
+ rt305x_mii_write(esw, 0, 29, 0x598b);
+ /* select local register */
+ rt305x_mii_write(esw, 0, 31, 0x8000);
+ } else if (ralink_soc == MT762X_SOC_MT7628AN ||
+ ralink_soc == MT762X_SOC_MT7688) {
+ int i;
+
+ /* reset EPHY */
+ mtk_reset(eth, RT5350_RESET_EPHY);
+
+ rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
+ rt305x_mii_write(esw, 0, 26, 0x0020);
+
+ for (i = 0; i < 5; i++) {
+ rt305x_mii_write(esw, i, 31, 0x8000);
+ rt305x_mii_write(esw, i, 0, 0x3100);
+ rt305x_mii_write(esw, i, 30, 0xa000);
+ rt305x_mii_write(esw, i, 31, 0xa000);
+ rt305x_mii_write(esw, i, 16, 0x0606);
+ rt305x_mii_write(esw, i, 23, 0x0f0e);
+ rt305x_mii_write(esw, i, 24, 0x1610);
+ rt305x_mii_write(esw, i, 30, 0x1f15);
+ rt305x_mii_write(esw, i, 28, 0x6111);
+ rt305x_mii_write(esw, i, 31, 0x2000);
+ rt305x_mii_write(esw, i, 26, 0x0000);
+ }
+
+ /* 100Base AOI setting */
+ rt305x_mii_write(esw, 0, 31, 0x5000);
+ rt305x_mii_write(esw, 0, 19, 0x004a);
+ rt305x_mii_write(esw, 0, 20, 0x015a);
+ rt305x_mii_write(esw, 0, 21, 0x00ee);
+ rt305x_mii_write(esw, 0, 22, 0x0033);
+ rt305x_mii_write(esw, 0, 23, 0x020a);
+ rt305x_mii_write(esw, 0, 24, 0x0000);
+ rt305x_mii_write(esw, 0, 25, 0x024a);
+ rt305x_mii_write(esw, 0, 26, 0x035a);
+ rt305x_mii_write(esw, 0, 27, 0x02ee);
+ rt305x_mii_write(esw, 0, 28, 0x0233);
+ rt305x_mii_write(esw, 0, 29, 0x000a);
+ rt305x_mii_write(esw, 0, 30, 0x0000);
+ } else {
+ rt305x_mii_write(esw, 0, 31, 0x8000);
+ for (i = 0; i < 5; i++) {
+ if (esw->ports[i].disable) {
+ rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
+ } else {
+ rt305x_mii_write(esw, i, MII_BMCR,
+ BMCR_FULLDPLX |
+ BMCR_ANENABLE |
+ BMCR_SPEED100);
+ }
+ /* TX10 waveform coefficient */
+ rt305x_mii_write(esw, i, 26, 0x1601);
+ /* TX100/TX10 AD/DA current bias */
+ rt305x_mii_write(esw, i, 29, 0x7058);
+ /* TX100 slew rate control */
+ rt305x_mii_write(esw, i, 30, 0x0018);
+ }
+
+ /* PHY IOT */
+ /* select global register */
+ rt305x_mii_write(esw, 0, 31, 0x0);
+ /* tune TP_IDL tail and head waveform */
+ rt305x_mii_write(esw, 0, 22, 0x052f);
+ /* set TX10 signal amplitude threshold to minimum */
+ rt305x_mii_write(esw, 0, 17, 0x0fe0);
+ /* set squelch amplitude to higher threshold */
+ rt305x_mii_write(esw, 0, 18, 0x40ba);
+ /* longer TP_IDL tail length */
+ rt305x_mii_write(esw, 0, 14, 0x65);
+ /* select local register */
+ rt305x_mii_write(esw, 0, 31, 0x8000);
+ }
+
+ if (esw->port_map)
+ port_map = esw->port_map;
+ else
+ port_map = RT305X_ESW_PMAP_LLLLLL;
+
+ /* Unused HW feature, but still nice to be consistent here...
+ * This is also exported to userspace ('lan' attribute) so it's
+ * conveniently usable to decide which ports go into the wan vlan by
+ * default.
+ */
+ esw_rmw(esw, RT305X_ESW_REG_SGC2,
+ RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
+ port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
+
+ /* make the switch leds blink */
+ for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
+ esw->ports[i].led = 0x05;
+
+ /* Only unmask the port change interrupt */
+ esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
+}
+
+static irqreturn_t esw_interrupt(int irq, void *_esw)
+{
+ struct rt305x_esw *esw = (struct rt305x_esw *)_esw;
+ u32 status;
+
+ status = esw_r32(esw, RT305X_ESW_REG_ISR);
+ if (status & RT305X_ESW_PORT_ST_CHG) {
+ u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
+
+ link >>= RT305X_ESW_POA_LINK_SHIFT;
+ link &= RT305X_ESW_POA_LINK_MASK;
+ dev_info(esw->dev, "link changed 0x%02X\n", link);
+ }
+ esw_w32(esw, status, RT305X_ESW_REG_ISR);
+
+ return IRQ_HANDLED;
+}
+
+static const struct of_device_id mediatek_esw_match[] = {
+ { .compatible = "ralink,rt3050-esw" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mediatek_esw_match);
+
+int mtk_esw_init(struct mtk_eth *eth)
+{
+ struct device_node *np = eth->switch_np;
+ struct platform_device *pdev = of_find_device_by_node(np);
+ struct rt305x_esw *esw;
+ int ret;
+
+ if (!pdev)
+ return -ENODEV;
+
+ if (!of_device_is_compatible(np, mediatek_esw_match->compatible))
+ return -EINVAL;
+
+ esw = platform_get_drvdata(pdev);
+ if (!esw)
+ return -ENODEV;
+ eth->sw_priv = esw;
+
+ esw_hw_init(eth, esw);
+
+ ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
+ esw);
+ if (!ret) {
+ esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
+ esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
+ }
+
+ return 0;
+}
+
+static int esw_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct device_node *np = pdev->dev.of_node;
+ const __be32 *port_map, *reg_init;
+ struct rt305x_esw *esw;
+ int ret;
+
+ esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
+ if (!esw)
+ return -ENOMEM;
+
+ esw->dev = &pdev->dev;
+ esw->irq = irq_of_parse_and_map(np, 0);
+ esw->base = devm_ioremap_resource(&pdev->dev, res);
+ if (!esw->base)
+ return -EADDRNOTAVAIL;
+
+ port_map = of_get_property(np, "mediatek,portmap", NULL);
+ if (port_map)
+ esw->port_map = be32_to_cpu(*port_map);
+
+ reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
+ if (reg_init)
+ esw->reg_led_polarity = be32_to_cpu(*reg_init);
+
+ platform_set_drvdata(pdev, esw);
+
+ spin_lock_init(&esw->reg_rw_lock);
+
+ return ret;
+}
+
+static int esw_remove(struct platform_device *pdev)
+{
+ struct rt305x_esw *esw = platform_get_drvdata(pdev);
+
+ if (esw) {
+ esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
+ platform_set_drvdata(pdev, NULL);
+ }
+
+ return 0;
+}
+
+static struct platform_driver esw_driver = {
+ .probe = esw_probe,
+ .remove = esw_remove,
+ .driver = {
+ .name = "rt3050-esw",
+ .owner = THIS_MODULE,
+ .of_match_table = mediatek_esw_match,
+ },
+};
+
+module_platform_driver(esw_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("Switch driver for RT305X SoC");
diff --git a/drivers/net/ethernet/mediatek/esw_rt3050.h b/drivers/net/ethernet/mediatek/esw_rt3050.h
new file mode 100644
index 0000000..9b0837a
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/esw_rt3050.h
@@ -0,0 +1,21 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_ESW_RT3052_H__
+#define _RALINK_ESW_RT3052_H__
+
+int __init mtk_esw_init(struct mtk_eth *eth);
+void mtk_switch_exit(struct mtk_eth *eth);
+
+#endif
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 14:21 ` [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW) John Crispin
@ 2016-02-26 15:18 ` Andrew Lunn
2016-02-26 15:24 ` John Crispin
` (2 more replies)
0 siblings, 3 replies; 26+ messages in thread
From: Andrew Lunn @ 2016-02-26 15:18 UTC (permalink / raw)
To: John Crispin
Cc: David S. Miller, netdev, linux-arm-kernel, linux-mediatek,
linux-kernel, Matthias Brugger, Steven Liu (?????????),
Carlos Huang (?????????), Fred Chang (?????????)
On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
> external ports, 1 cpu port and 1 further port that the internal HW
> offloading engine connects to.
>
> This driver is very basic and only provides basic init and irq support.
> The SoC and switch core both have support for a special tag making DSA
> support possible.
Hi Crispin
There was recently a discussion about adding switches without using
DSA or switchdev. It was pretty much decided we would not accept such
drivers.
Sorry
Andrew
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 15:18 ` Andrew Lunn
@ 2016-02-26 15:24 ` John Crispin
2016-02-26 17:05 ` Andrew Lunn
` (2 more replies)
2016-02-26 16:25 ` Felix Fietkau
2016-02-26 17:35 ` David Miller
2 siblings, 3 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 15:24 UTC (permalink / raw)
To: Andrew Lunn
Cc: Fred Chang (?????????), Steven Liu (?????????),
netdev, Carlos Huang (?????????),
linux-kernel, linux-mediatek, Matthias Brugger, David S. Miller,
linux-arm-kernel
On 26/02/2016 16:18, Andrew Lunn wrote:
> On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
>> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
>> external ports, 1 cpu port and 1 further port that the internal HW
>> offloading engine connects to.
>>
>> This driver is very basic and only provides basic init and irq support.
>> The SoC and switch core both have support for a special tag making DSA
>> support possible.
>
> Hi Crispin
>
> There was recently a discussion about adding switches without using
> DSA or switchdev. It was pretty much decided we would not accept such
> drivers.
>
> Sorry
>
> Andrew
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
Hi,
would the series be ok if we just dropped those parts and then have a
driver in the kernel that wont do much with the out of tree patches ?
the problem here is that on one side people complain about vendors not
sending code upstream. once they start being a good citizen and provide
funding to send stuff upstream the feedback tends to be very bad as seen
here. we are planning on doing a DSA driver but one step at a time. this
kind of feedback will inevitably lead to vendors doing second thoughts
of upstream contributions.
John
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 15:24 ` John Crispin
@ 2016-02-26 17:05 ` Andrew Lunn
2016-02-26 17:44 ` David Miller
2016-02-26 17:36 ` David Miller
2016-02-26 18:34 ` Florian Fainelli
2 siblings, 1 reply; 26+ messages in thread
From: Andrew Lunn @ 2016-02-26 17:05 UTC (permalink / raw)
To: John Crispin
Cc: Fred Chang (?????????), Steven Liu (?????????),
netdev, Carlos Huang (?????????),
linux-kernel, linux-mediatek, Matthias Brugger, David S. Miller,
linux-arm-kernel
> the problem here is that on one side people complain about vendors not
> sending code upstream. once they start being a good citizen and provide
> funding to send stuff upstream the feedback tends to be very bad as seen
> here. we are planning on doing a DSA driver but one step at a time. this
> kind of feedback will inevitably lead to vendors doing second thoughts
> of upstream contributions.
I think it is great a vendor is providing funding to get code
upstream. However, that code needs to conform with current kernel
architecture and design philosophy.
We as a community also need to be consistent. We have recently push
back on Microchip with there LAN9352 who want to do something very
similar, introduce the MAC and a very dumb switch driver. They are now
looking at what it means to do a DSA driver. There is also talk of
writing a DSA driver for the ks8995 family.
As David said recently, a year ago this probably would of been
accepted. But now, switches need to be DSA or switchdev.
Andrew
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 17:05 ` Andrew Lunn
@ 2016-02-26 17:44 ` David Miller
0 siblings, 0 replies; 26+ messages in thread
From: David Miller @ 2016-02-26 17:44 UTC (permalink / raw)
To: andrew
Cc: blogic, Fred.Chang, steven.liu, netdev, Carlos.Huang,
linux-kernel, linux-mediatek, matthias.bgg, linux-arm-kernel
From: Andrew Lunn <andrew@lunn.ch>
Date: Fri, 26 Feb 2016 18:05:45 +0100
> I think it is great a vendor is providing funding to get code
> upstream. However, that code needs to conform with current kernel
> architecture and design philosophy.
>
> We as a community also need to be consistent. We have recently push
> back on Microchip with there LAN9352 who want to do something very
> similar, introduce the MAC and a very dumb switch driver. They are now
> looking at what it means to do a DSA driver. There is also talk of
> writing a DSA driver for the ks8995 family.
>
> As David said recently, a year ago this probably would of been
> accepted. But now, switches need to be DSA or switchdev.
+1
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 15:24 ` John Crispin
2016-02-26 17:05 ` Andrew Lunn
@ 2016-02-26 17:36 ` David Miller
2016-02-26 18:34 ` Florian Fainelli
2 siblings, 0 replies; 26+ messages in thread
From: David Miller @ 2016-02-26 17:36 UTC (permalink / raw)
To: blogic
Cc: andrew, Fred.Chang, steven.liu, netdev, Carlos.Huang,
linux-kernel, linux-mediatek, matthias.bgg, linux-arm-kernel
From: John Crispin <blogic@openwrt.org>
Date: Fri, 26 Feb 2016 16:24:47 +0100
> the problem here is that on one side people complain about vendors not
> sending code upstream. once they start being a good citizen and provide
> funding to send stuff upstream the feedback tends to be very bad as seen
> here.
The feedback is not bad, on the contrary it is very positive and people
like Andrew want to help people like you write proper switch drivers.
If you were ignored, or rejected purely on the grounds of coding style
issues, that would be "very bad" feedback.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 15:24 ` John Crispin
2016-02-26 17:05 ` Andrew Lunn
2016-02-26 17:36 ` David Miller
@ 2016-02-26 18:34 ` Florian Fainelli
2 siblings, 0 replies; 26+ messages in thread
From: Florian Fainelli @ 2016-02-26 18:34 UTC (permalink / raw)
To: John Crispin, Andrew Lunn
Cc: Fred Chang (?????????), Steven Liu (?????????),
netdev, Carlos Huang (?????????),
linux-kernel, linux-mediatek, Matthias Brugger, David S. Miller,
linux-arm-kernel
On 26/02/16 07:24, John Crispin wrote:
>
> Hi,
>
> would the series be ok if we just dropped those parts and then have a
> driver in the kernel that wont do much with the out of tree patches ?
>
> the problem here is that on one side people complain about vendors not
> sending code upstream. once they start being a good citizen and provide
> funding to send stuff upstream the feedback tends to be very bad as seen
> here.
I agree with David here, the feedback from Andrew is very constructive,
you just don't like the feedback you are being given, which is a
different thing. You can't always get a 12 series patches adding a new
driver accepted after second try, look at all the recent submissions
that occured, it took 5-6-7 maybe more submissions until things were in
a shape where they could be merged. If for your next submission you get
the feedback that switchdev/DSA is deprecated, and something new needs
to be used, then I would agree that feedback is not acceptable, I doubt
this will be the case unless we wait another 10 years to get these
patches out.
> we are planning on doing a DSA driver but one step at a time. this
> kind of feedback will inevitably lead to vendors doing second thoughts
> of upstream contributions.
If you are planning on a DSA driver, which sounds like a good plan, then
maybe drop the integrated switch parts for now, keep it as a local set
of patches for your testing, and just get the basic CPU Ethernet MAC
driver to work for data movement, so that part gets in, and later on,
when your DSA driver is ready, that's one less thing to take care of.
They ultimately are logically spearated drivers if you use DSA, a little
less if you use switchdev.
--
Florian
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 15:18 ` Andrew Lunn
2016-02-26 15:24 ` John Crispin
@ 2016-02-26 16:25 ` Felix Fietkau
2016-02-26 17:29 ` Andrew Lunn
2016-02-26 17:43 ` David Miller
2016-02-26 17:35 ` David Miller
2 siblings, 2 replies; 26+ messages in thread
From: Felix Fietkau @ 2016-02-26 16:25 UTC (permalink / raw)
To: Andrew Lunn, John Crispin
Cc: David S. Miller, netdev, linux-arm-kernel, linux-mediatek,
linux-kernel, Matthias Brugger, Steven Liu (?????????),
Carlos Huang (?????????), Fred Chang (?????????)
On 2016-02-26 16:18, Andrew Lunn wrote:
> On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
>> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
>> external ports, 1 cpu port and 1 further port that the internal HW
>> offloading engine connects to.
>>
>> This driver is very basic and only provides basic init and irq support.
>> The SoC and switch core both have support for a special tag making DSA
>> support possible.
>
> Hi Crispin
>
> There was recently a discussion about adding switches without using
> DSA or switchdev. It was pretty much decided we would not accept such
> drivers.
For exactly this reason, the code does not provide any non-standard API
for allowing the user to configure the switch. The hardware needs to be
programmed with some defaults for the driver to be functional (since the
switch logic is built into the SoC).
In my opinion, leaving this part out does not make much sense and
neither does deferring the entire patch series until we have a
switchdev/DSA capable driver. This is just a starting point, which will
be turned into a proper driver with the right APIs later.
- Felix
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 16:25 ` Felix Fietkau
@ 2016-02-26 17:29 ` Andrew Lunn
2016-02-26 17:43 ` David Miller
1 sibling, 0 replies; 26+ messages in thread
From: Andrew Lunn @ 2016-02-26 17:29 UTC (permalink / raw)
To: Felix Fietkau
Cc: John Crispin, David S. Miller, netdev, linux-arm-kernel,
linux-mediatek, linux-kernel, Matthias Brugger,
Steven Liu (?????????), Carlos Huang (?????????),
Fred Chang (?????????)
On Fri, Feb 26, 2016 at 05:25:38PM +0100, Felix Fietkau wrote:
> On 2016-02-26 16:18, Andrew Lunn wrote:
> > On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
> >> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
> >> external ports, 1 cpu port and 1 further port that the internal HW
> >> offloading engine connects to.
> >>
> >> This driver is very basic and only provides basic init and irq support.
> >> The SoC and switch core both have support for a special tag making DSA
> >> support possible.
> >
> > Hi Crispin
> >
> > There was recently a discussion about adding switches without using
> > DSA or switchdev. It was pretty much decided we would not accept such
> > drivers.
> For exactly this reason, the code does not provide any non-standard API
> for allowing the user to configure the switch. The hardware needs to be
> programmed with some defaults for the driver to be functional (since the
> switch logic is built into the SoC).
>
>
> In my opinion, leaving this part out does not make much sense and
> neither does deferring the entire patch series until we have a
> switchdev/DSA capable driver. This is just a starting point, which will
> be turned into a proper driver with the right APIs later.
You are however introducing APIs which become things you need to
support. Your device tree binding for example. The device tree
maintainers consider this a stable API you need to maintain forever.
Can you guarantee that you can maintain this binding, and also support
the DSA binding? How messy is it going to make your code supporting
two bindings?
You currently have one netdev interface for five switch ports. When
you have a DSA driver, you have 5 additional netdev interfaces, one
per port, and your original interface is now unusable. Isn't that an
API change.
You need to find incremental steps towards a switchdev/DSA driver
which are not going to hinder you in the long run.
Andrew
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 16:25 ` Felix Fietkau
2016-02-26 17:29 ` Andrew Lunn
@ 2016-02-26 17:43 ` David Miller
1 sibling, 0 replies; 26+ messages in thread
From: David Miller @ 2016-02-26 17:43 UTC (permalink / raw)
To: nbd
Cc: andrew, blogic, netdev, linux-arm-kernel, linux-mediatek,
linux-kernel, matthias.bgg, steven.liu, Carlos.Huang, Fred.Chang
From: Felix Fietkau <nbd@openwrt.org>
Date: Fri, 26 Feb 2016 17:25:38 +0100
> In my opinion, leaving this part out does not make much sense and
> neither does deferring the entire patch series until we have a
> switchdev/DSA capable driver. This is just a starting point, which will
> be turned into a proper driver with the right APIs later.
I disagree, and we want people to concentrate on writing proper
switchdev/DSA drivers.
People like Andrew have offered to help in any way possible to make
this as easy as possible, so please take this seriously.
I would have accepted your arguments a year ago when we didn't have
the right infrastructure, but now we do and there is no real excuse
to submit partial or bastardized drivers for these kinds of hardware
anymore
Thanks in advance for your understanding, and I'm plan to stand
very firm on this.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW)
2016-02-26 15:18 ` Andrew Lunn
2016-02-26 15:24 ` John Crispin
2016-02-26 16:25 ` Felix Fietkau
@ 2016-02-26 17:35 ` David Miller
2 siblings, 0 replies; 26+ messages in thread
From: David Miller @ 2016-02-26 17:35 UTC (permalink / raw)
To: andrew
Cc: blogic, netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
matthias.bgg, steven.liu, Carlos.Huang, Fred.Chang
From: Andrew Lunn <andrew@lunn.ch>
Date: Fri, 26 Feb 2016 16:18:13 +0100
> On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
>> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
>> external ports, 1 cpu port and 1 further port that the internal HW
>> offloading engine connects to.
>>
>> This driver is very basic and only provides basic init and irq support.
>> The SoC and switch core both have support for a special tag making DSA
>> support possible.
>
> Hi Crispin
>
> There was recently a discussion about adding switches without using
> DSA or switchdev. It was pretty much decided we would not accept such
> drivers.
>
> Sorry
+1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH V2 04/12] net-next: mediatek: add gigabit switch driver (GSW)
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (2 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 03/12] net-next: mediatek: add embedded switch driver (ESW) John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 14:21 ` [PATCH V2 05/12] net-next: mediatek: add support for rt2880 John Crispin
` (7 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin
The GSW is found in all of the 1000mbit SoCs. it has 5 external ports,
1-2 cpu ports and 1 further port that the internal HW offloading engine
connects to. The switch core used is a MT7530, which also exists as a
standalone chip. Although these SoCs (mt7620/1/3) share the same switch
core, the bring up of these is slightly different. One of the reasons is
that on mt7620 the switch core is mmio mapped while MT7621/3 talks to the
switch via MDIO addr 0x1f. Additionally, the SoCs have different MAC types
and some of them have TRGMII support. MT7621 can do 1,2gbit and MT7623 is
able to do 2,6gbit. The support for the TRGMII bring up is not part of this
series as the code is based on the SDK driver and has between 1500 and 2000
magic values that still need to be converted to defines.
Because of these differences we have 3 separate drivers for these 3 SoCs.
These drivers are very basic and only provides basic init and irq support.
The SoC and switch core both have support for a special tag making DSA
support possible.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/ethernet/mediatek/gsw_mt7620.c | 256 +++++++++++++++++
drivers/net/ethernet/mediatek/gsw_mt7620.h | 277 ++++++++++++++++++
drivers/net/ethernet/mediatek/gsw_mt7621.c | 265 ++++++++++++++++++
drivers/net/ethernet/mediatek/gsw_mt7623.c | 417 ++++++++++++++++++++++++++++
4 files changed, 1215 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.c
create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.h
create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7621.c
create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7623.c
diff --git a/drivers/net/ethernet/mediatek/gsw_mt7620.c b/drivers/net/ethernet/mediatek/gsw_mt7620.c
new file mode 100644
index 0000000..8a81048
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/gsw_mt7620.c
@@ -0,0 +1,256 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+
+void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
+{
+ iowrite32(val, gsw->base + reg);
+}
+
+u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
+{
+ return ioread32(gsw->base + reg);
+}
+
+static irqreturn_t gsw_interrupt_mt7620(int irq, void *_eth)
+{
+ struct mtk_eth *eth = (struct mtk_eth *)_eth;
+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
+ int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
+ u32 status;
+
+ status = mtk_switch_r32(gsw, GSW_REG_ISR);
+ if (status & PORT_IRQ_ST_CHG)
+ for (i = 0; i <= max; i++) {
+ u32 status = mtk_switch_r32(gsw,
+ GSW_REG_PORT_STATUS(i));
+ int link = status & 0x1;
+
+ if (link != eth->link[i])
+ mt7620_print_link_state(eth, i, link,
+ (status >> 2) & 3,
+ (status & 0x2));
+
+ eth->link[i] = link;
+ }
+ mtk_switch_w32(gsw, status, GSW_REG_ISR);
+
+ return IRQ_HANDLED;
+}
+
+static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
+{
+ u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
+
+ rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
+ mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4),
+ GSW_REG_CKGCR);
+
+ if (of_property_read_bool(np, "mediatek,mt7530")) {
+ u32 val;
+
+ /* turn off ephy and set phy base addr to 12 */
+ mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
+ (0x1f << 24) | (0xc << 16),
+ GSW_REG_GPC1);
+
+ /* set MT7530 central align */
+ val = mt7530_mdio_r32(gsw, 0x7830);
+ val &= ~BIT(0);
+ val |= BIT(1);
+ mt7530_mdio_w32(gsw, 0x7830, val);
+
+ val = mt7530_mdio_r32(gsw, 0x7a40);
+ val &= ~BIT(30);
+ mt7530_mdio_w32(gsw, 0x7a40, val);
+
+ mt7530_mdio_w32(gsw, 0x7a78, 0x855);
+ } else {
+ /* global page 4 */
+ _mt7620_mii_write(gsw, 1, 31, 0x4000);
+
+ _mt7620_mii_write(gsw, 1, 17, 0x7444);
+ if (is_BGA)
+ _mt7620_mii_write(gsw, 1, 19, 0x0114);
+ else
+ _mt7620_mii_write(gsw, 1, 19, 0x0117);
+
+ _mt7620_mii_write(gsw, 1, 22, 0x10cf);
+ _mt7620_mii_write(gsw, 1, 25, 0x6212);
+ _mt7620_mii_write(gsw, 1, 26, 0x0777);
+ _mt7620_mii_write(gsw, 1, 29, 0x4000);
+ _mt7620_mii_write(gsw, 1, 28, 0xc077);
+ _mt7620_mii_write(gsw, 1, 24, 0x0000);
+
+ /* global page 3 */
+ _mt7620_mii_write(gsw, 1, 31, 0x3000);
+ _mt7620_mii_write(gsw, 1, 17, 0x4838);
+
+ /* global page 2 */
+ _mt7620_mii_write(gsw, 1, 31, 0x2000);
+ if (is_BGA) {
+ _mt7620_mii_write(gsw, 1, 21, 0x0515);
+ _mt7620_mii_write(gsw, 1, 22, 0x0053);
+ _mt7620_mii_write(gsw, 1, 23, 0x00bf);
+ _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
+ _mt7620_mii_write(gsw, 1, 25, 0x0fad);
+ _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
+ } else {
+ _mt7620_mii_write(gsw, 1, 21, 0x0517);
+ _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
+ _mt7620_mii_write(gsw, 1, 23, 0x00bf);
+ _mt7620_mii_write(gsw, 1, 24, 0x0aab);
+ _mt7620_mii_write(gsw, 1, 25, 0x00ae);
+ _mt7620_mii_write(gsw, 1, 26, 0x0fff);
+ }
+ /* global page 1 */
+ _mt7620_mii_write(gsw, 1, 31, 0x1000);
+ _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
+ }
+
+ /* global page 0 */
+ _mt7620_mii_write(gsw, 1, 31, 0x8000);
+ _mt7620_mii_write(gsw, 0, 30, 0xa000);
+ _mt7620_mii_write(gsw, 1, 30, 0xa000);
+ _mt7620_mii_write(gsw, 2, 30, 0xa000);
+ _mt7620_mii_write(gsw, 3, 30, 0xa000);
+
+ _mt7620_mii_write(gsw, 0, 4, 0x05e1);
+ _mt7620_mii_write(gsw, 1, 4, 0x05e1);
+ _mt7620_mii_write(gsw, 2, 4, 0x05e1);
+ _mt7620_mii_write(gsw, 3, 4, 0x05e1);
+
+ /* global page 2 */
+ _mt7620_mii_write(gsw, 1, 31, 0xa000);
+ _mt7620_mii_write(gsw, 0, 16, 0x1111);
+ _mt7620_mii_write(gsw, 1, 16, 0x1010);
+ _mt7620_mii_write(gsw, 2, 16, 0x1515);
+ _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
+
+ /* CPU Port6 Force Link 1G, FC ON */
+ mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
+
+ /* Set Port 6 as CPU Port */
+ mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
+
+ /* setup port 4 */
+ if (gsw->port4 == PORT4_EPHY) {
+ u32 val = rt_sysc_r32(SYSC_REG_CFG1);
+
+ val |= 3 << 14;
+ rt_sysc_w32(val, SYSC_REG_CFG1);
+ _mt7620_mii_write(gsw, 4, 30, 0xa000);
+ _mt7620_mii_write(gsw, 4, 4, 0x05e1);
+ _mt7620_mii_write(gsw, 4, 16, 0x1313);
+ pr_info("gsw: setting port4 to ephy mode\n");
+ }
+}
+
+static const struct of_device_id mediatek_gsw_match[] = {
+ { .compatible = "mediatek,mt7620-gsw" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
+
+int mtk_gsw_init(struct mtk_eth *eth)
+{
+ struct device_node *np = eth->switch_np;
+ struct platform_device *pdev = of_find_device_by_node(np);
+ struct mt7620_gsw *gsw;
+
+ if (!pdev)
+ return -ENODEV;
+
+ if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
+ return -EINVAL;
+
+ gsw = platform_get_drvdata(pdev);
+ eth->sw_priv = gsw;
+
+ mt7620_hw_init(gsw, np);
+
+ if (gsw->irq) {
+ request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
+ "gsw", eth);
+ mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
+ }
+
+ return 0;
+}
+
+static int mt7620_gsw_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct device_node *np = pdev->dev.of_node;
+ const char *port4 = NULL;
+ struct mt7620_gsw *gsw;
+
+ gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
+ if (!gsw)
+ return -ENOMEM;
+
+ gsw->base = devm_ioremap_resource(&pdev->dev, res);
+ if (!gsw->base)
+ return -EADDRNOTAVAIL;
+
+ gsw->dev = &pdev->dev;
+
+ of_property_read_string(np, "mediatek,port4", &port4);
+ if (port4 && !strcmp(port4, "ephy"))
+ gsw->port4 = PORT4_EPHY;
+ else if (port4 && !strcmp(port4, "mac"))
+ gsw->port4 = PORT4_EXT;
+ else
+ gsw->port4 = PORT4_EPHY;
+
+ gsw->irq = irq_of_parse_and_map(np, 0);
+
+ platform_set_drvdata(pdev, gsw);
+
+ return 0;
+}
+
+static int mt7620_gsw_remove(struct platform_device *pdev)
+{
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver gsw_driver = {
+ .probe = mt7620_gsw_probe,
+ .remove = mt7620_gsw_remove,
+ .driver = {
+ .name = "mt7620-gsw",
+ .owner = THIS_MODULE,
+ .of_match_table = mediatek_gsw_match,
+ },
+};
+
+module_platform_driver(gsw_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
diff --git a/drivers/net/ethernet/mediatek/gsw_mt7620.h b/drivers/net/ethernet/mediatek/gsw_mt7620.h
new file mode 100644
index 0000000..1766939
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
@@ -0,0 +1,277 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_GSW_MT7620_H__
+#define _RALINK_GSW_MT7620_H__
+
+#define GSW_REG_PHY_TIMEOUT (5 * HZ)
+
+#define MT7620_GSW_REG_PIAC 0x0004
+
+#define GSW_NUM_VLANS 16
+#define GSW_NUM_VIDS 4096
+#define GSW_NUM_PORTS 7
+#define GSW_PORT6 6
+
+#define GSW_MDIO_ACCESS BIT(31)
+#define GSW_MDIO_READ BIT(19)
+#define GSW_MDIO_WRITE BIT(18)
+#define GSW_MDIO_START BIT(16)
+#define GSW_MDIO_ADDR_SHIFT 20
+#define GSW_MDIO_REG_SHIFT 25
+
+#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
+#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
+#define GSW_REG_SMACCR0 0x3fE4
+#define GSW_REG_SMACCR1 0x3fE8
+#define GSW_REG_CKGCR 0x3ff0
+
+#define GSW_REG_IMR 0x7008
+#define GSW_REG_ISR 0x700c
+#define GSW_REG_GPC1 0x7014
+
+#define SYSC_REG_CHIP_REV_ID 0x0c
+#define SYSC_REG_CFG 0x10
+#define SYSC_REG_CFG1 0x14
+#define RST_CTRL_MCM BIT(2)
+#define SYSC_PAD_RGMII2_MDIO 0x58
+#define SYSC_GPIO_MODE 0x60
+
+#define PORT_IRQ_ST_CHG 0x7f
+
+#define MT7621_ESW_PHY_POLLING 0x0000
+#define MT7620_ESW_PHY_POLLING 0x7000
+
+#define PMCR_IPG BIT(18)
+#define PMCR_MAC_MODE BIT(16)
+#define PMCR_FORCE BIT(15)
+#define PMCR_TX_EN BIT(14)
+#define PMCR_RX_EN BIT(13)
+#define PMCR_BACKOFF BIT(9)
+#define PMCR_BACKPRES BIT(8)
+#define PMCR_RX_FC BIT(5)
+#define PMCR_TX_FC BIT(4)
+#define PMCR_SPEED(_x) (_x << 2)
+#define PMCR_DUPLEX BIT(1)
+#define PMCR_LINK BIT(0)
+
+#define PHY_AN_EN BIT(31)
+#define PHY_PRE_EN BIT(30)
+#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
+
+/* ethernet subsystem config register */
+#define ETHSYS_SYSCFG0 0x14
+/* ethernet subsystem clock register */
+#define ETHSYS_CLKCFG0 0x2c
+#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
+
+/* p5 RGMII wrapper TX clock control register */
+#define MT7530_P5RGMIITXCR 0x7b04
+/* p5 RGMII wrapper RX clock control register */
+#define MT7530_P5RGMIIRXCR 0x7b00
+/* TRGMII TDX ODT registers */
+#define MT7530_TRGMII_TD0_ODT 0x7a54
+#define MT7530_TRGMII_TD1_ODT 0x7a5c
+#define MT7530_TRGMII_TD2_ODT 0x7a64
+#define MT7530_TRGMII_TD3_ODT 0x7a6c
+#define MT7530_TRGMII_TD4_ODT 0x7a74
+#define MT7530_TRGMII_TD5_ODT 0x7a7c
+/* TRGMII TCK ctrl register */
+#define MT7530_TRGMII_TCK_CTRL 0x7a78
+/* TRGMII Tx ctrl register */
+#define MT7530_TRGMII_TXCTRL 0x7a40
+/* port 6 extended control register */
+#define MT7530_P6ECR 0x7830
+/* IO driver control register */
+#define MT7530_IO_DRV_CR 0x7810
+/* top signal control register */
+#define MT7530_TOP_SIG_CTRL 0x7808
+/* modified hwtrap register */
+#define MT7530_MHWTRAP 0x7804
+/* hwtrap status register */
+#define MT7530_HWTRAP 0x7800
+/* status interrupt register */
+#define MT7530_SYS_INT_STS 0x700c
+/* system nterrupt register */
+#define MT7530_SYS_INT_EN 0x7008
+/* system control register */
+#define MT7530_SYS_CTRL 0x7000
+/* port MAC status register */
+#define MT7530_PMSR_P(x) (0x3008 + (x * 0x100))
+/* port MAC control register */
+#define MT7530_PMCR_P(x) (0x3000 + (x * 0x100))
+
+#define MT7621_XTAL_SHIFT 6
+#define MT7621_XTAL_MASK 0x7
+#define MT7621_XTAL_25 6
+#define MT7621_XTAL_40 3
+#define MT7621_MDIO_DRV_MASK (3 << 4)
+#define MT7621_GE1_MODE_MASK (3 << 12)
+
+#define TRGMII_TXCTRL_TXC_INV BIT(30)
+#define P6ECR_INTF_MODE_RGMII BIT(1)
+#define P5RGMIIRXCR_C_ALIGN BIT(8)
+#define P5RGMIIRXCR_DELAY_2 BIT(1)
+#define P5RGMIITXCR_DELAY_2 (BIT(8) | BIT(2))
+
+/* TOP_SIG_CTRL bits */
+#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
+
+/* MHWTRAP bits */
+#define MHWTRAP_MANUAL BIT(16)
+#define MHWTRAP_P5_MAC_SEL BIT(13)
+#define MHWTRAP_P6_DIS BIT(8)
+#define MHWTRAP_P5_RGMII_MODE BIT(7)
+#define MHWTRAP_P5_DIS BIT(6)
+#define MHWTRAP_PHY_ACCESS BIT(5)
+
+/* HWTRAP bits */
+#define HWTRAP_XTAL_SHIFT 9
+#define HWTRAP_XTAL_MASK 0x3
+
+/* SYS_CTRL bits */
+#define SYS_CTRL_SW_RST BIT(1)
+#define SYS_CTRL_REG_RST BIT(0)
+
+/* PMCR bits */
+#define PMCR_IFG_XMIT_96 BIT(18)
+#define PMCR_MAC_MODE BIT(16)
+#define PMCR_FORCE_MODE BIT(15)
+#define PMCR_TX_EN BIT(14)
+#define PMCR_RX_EN BIT(13)
+#define PMCR_BACK_PRES_EN BIT(9)
+#define PMCR_BACKOFF_EN BIT(8)
+#define PMCR_TX_FC_EN BIT(5)
+#define PMCR_RX_FC_EN BIT(4)
+#define PMCR_FORCE_SPEED_1000 BIT(3)
+#define PMCR_FORCE_FDX BIT(1)
+#define PMCR_FORCE_LNK BIT(0)
+#define PMCR_FIXED_LINK (PMCR_IFG_XMIT_96 | PMCR_MAC_MODE | \
+ PMCR_FORCE_MODE | PMCR_TX_EN | PMCR_RX_EN | \
+ PMCR_BACK_PRES_EN | PMCR_BACKOFF_EN | \
+ PMCR_FORCE_SPEED_1000 | PMCR_FORCE_FDX | \
+ PMCR_FORCE_LNK)
+
+#define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN)
+
+/* TRGMII control registers */
+#define GSW_INTF_MODE 0x390
+#define GSW_TRGMII_TD0_ODT 0x354
+#define GSW_TRGMII_TD1_ODT 0x35c
+#define GSW_TRGMII_TD2_ODT 0x364
+#define GSW_TRGMII_TD3_ODT 0x36c
+#define GSW_TRGMII_TXCTL_ODT 0x374
+#define GSW_TRGMII_TCK_ODT 0x37c
+#define GSW_TRGMII_RCK_CTRL 0x300
+
+#define INTF_MODE_TRGMII BIT(1)
+#define TRGMII_RCK_CTRL_RX_RST BIT(31)
+
+/* Mac control registers */
+#define MTK_MAC_P2_MCR 0x200
+#define MTK_MAC_P1_MCR 0x100
+
+#define MAC_MCR_MAX_RX_2K BIT(29)
+#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
+#define MAC_MCR_FORCE_MODE BIT(15)
+#define MAC_MCR_TX_EN BIT(14)
+#define MAC_MCR_RX_EN BIT(13)
+#define MAC_MCR_BACKOFF_EN BIT(9)
+#define MAC_MCR_BACKPR_EN BIT(8)
+#define MAC_MCR_FORCE_RX_FC BIT(5)
+#define MAC_MCR_FORCE_TX_FC BIT(4)
+#define MAC_MCR_SPEED_1000 BIT(3)
+#define MAC_MCR_FORCE_DPX BIT(1)
+#define MAC_MCR_FORCE_LINK BIT(0)
+#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_2K | MAC_MCR_IPG_CFG | \
+ MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
+ MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
+ MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
+ MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
+ MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
+#define MAC_MCR_FIXED_LINK_FC (MAC_MCR_MAX_RX_2K | MAC_MCR_IPG_CFG | \
+ MAC_MCR_FIXED_LINK)
+
+/* possible XTAL speed */
+#define MT7623_XTAL_40 0
+#define MT7623_XTAL_20 1
+#define MT7623_XTAL_25 3
+
+/* GPIO port control registers */
+#define GPIO_OD33_CTRL8 0x4c0
+#define GPIO_BIAS_CTRL 0xed0
+#define GPIO_DRV_SEL10 0xf00
+
+/* on MT7620 the functio of port 4 can be software configured */
+enum {
+ PORT4_EPHY = 0,
+ PORT4_EXT,
+};
+
+/* struct mt7620_gsw - the structure that holds the SoC specific data
+ * @dev: The Device struct
+ * @base: The base address
+ * @piac_offset: The PIAC base may change depending on SoC
+ * @irq: The IRQ we are using
+ * @port4: The port4 mode on MT7620
+ * @autopoll: Is MDIO autopolling enabled
+ * @ethsys: The ethsys register map
+ * @pctl: The pin control register map
+ * @clk_gsw: The switch clock
+ * @clk_gp1: The gmac1 clock
+ * @clk_gp2: The gmac2 clock
+ * @clk_trgpll: The trgmii pll clock
+ */
+struct mt7620_gsw {
+ struct device *dev;
+ void __iomem *base;
+ u32 piac_offset;
+ int irq;
+ int port4;
+ unsigned long int autopoll;
+
+ struct regmap *ethsys;
+ struct regmap *pctl;
+
+ struct clk *clk_gsw;
+ struct clk *clk_gp1;
+ struct clk *clk_gp2;
+ struct clk *clk_trgpll;
+};
+
+/* switch register I/O wrappers */
+void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
+u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
+
+/* the callback used by the driver core to bringup the switch */
+int mtk_gsw_init(struct mtk_eth *eth);
+
+/* MDIO access wrappers */
+int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
+int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
+void mt7620_mdio_link_adjust(struct mtk_eth *eth, int port);
+int mt7620_has_carrier(struct mtk_eth *eth);
+void mt7620_print_link_state(struct mtk_eth *eth, int port, int link,
+ int speed, int duplex);
+void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
+u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
+void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg);
+
+u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
+ u32 phy_register, u32 write_data);
+u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
+void mt7620_handle_carrier(struct mtk_eth *eth);
+
+#endif
diff --git a/drivers/net/ethernet/mediatek/gsw_mt7621.c b/drivers/net/ethernet/mediatek/gsw_mt7621.c
new file mode 100644
index 0000000..3e0a37f
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/gsw_mt7621.c
@@ -0,0 +1,265 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+
+#include <ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+
+void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
+{
+ iowrite32(val, gsw->base + reg);
+}
+
+u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
+{
+ return ioread32(gsw->base + reg);
+}
+
+static irqreturn_t gsw_interrupt_mt7621(int irq, void *_eth)
+{
+ struct mtk_eth *eth = (struct mtk_eth *)_eth;
+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
+ u32 reg, i;
+
+ reg = mt7530_mdio_r32(gsw, MT7530_SYS_INT_STS);
+
+ for (i = 0; i < 5; i++) {
+ unsigned int link;
+
+ if ((reg & BIT(i)) == 0)
+ continue;
+
+ link = mt7530_mdio_r32(gsw, MT7530_PMSR_P(i)) & 0x1;
+
+ if (link == eth->link[i])
+ continue;
+
+ eth->link[i] = link;
+ if (link)
+ netdev_info(*eth->netdev,
+ "port %d link up\n", i);
+ else
+ netdev_info(*eth->netdev,
+ "port %d link down\n", i);
+ }
+
+ mt7530_mdio_w32(gsw, MT7530_SYS_INT_STS, 0x1f);
+
+ return IRQ_HANDLED;
+}
+
+static void mt7621_hw_init(struct mtk_eth *eth, struct mt7620_gsw *gsw,
+ struct device_node *np)
+{
+ u32 i;
+ u32 val;
+
+ /* wardware reset the switch */
+ mtk_reset(eth, RST_CTRL_MCM);
+ mdelay(10);
+
+ /* reduce RGMII2 PAD driving strength */
+ rt_sysc_m32(MT7621_MDIO_DRV_MASK, 0, SYSC_PAD_RGMII2_MDIO);
+
+ /* set GMAC1 RGMII mode */
+ rt_sysc_m32(MT7621_GE1_MODE_MASK, 0, SYSC_REG_CFG1);
+
+ /* turn off all PHYs */
+ for (i = 0; i <= 4; i++) {
+ val = _mt7620_mii_read(gsw, i, 0x0);
+ val |= BIT(11);
+ _mt7620_mii_write(gsw, i, 0x0, val);
+ }
+
+ /* reset the switch */
+ mt7530_mdio_w32(gsw, MT7530_SYS_CTRL,
+ SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+ usleep_range(10, 20);
+
+ if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
+ /* GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536 */
+ mtk_switch_w32(gsw, MAC_MCR_FIXED_LINK, MTK_MAC_P2_MCR);
+ mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK);
+ } else {
+ /* GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536 */
+ mtk_switch_w32(gsw, MAC_MCR_FIXED_LINK_FC, MTK_MAC_P1_MCR);
+ mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK_FC);
+ }
+
+ /* GE2, Link down */
+ mtk_switch_w32(gsw, MAC_MCR_FORCE_MODE, MTK_MAC_P2_MCR);
+
+ /* Enable Port 6, P5 as GMAC5, P5 disable */
+ val = mt7530_mdio_r32(gsw, MT7530_MHWTRAP);
+ /* Enable Port 6 */
+ val &= ~MHWTRAP_P6_DIS;
+ /* Disable Port 5 */
+ val |= MHWTRAP_P5_DIS;
+ /* manual override of HW-Trap */
+ val |= MHWTRAP_MANUAL;
+ mt7530_mdio_w32(gsw, MT7530_MHWTRAP, val);
+
+ val = rt_sysc_r32(SYSC_REG_CFG);
+ val = (val >> MT7621_XTAL_SHIFT) & MT7621_XTAL_MASK;
+ if (val < MT7621_XTAL_25 && val >= MT7621_XTAL_40) {
+ /* 40Mhz */
+
+ /* disable MT7530 core clock */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x410);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ _mt7620_mii_write(gsw, 0, 14, 0x0);
+
+ /* disable MT7530 PLL */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x40d);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ _mt7620_mii_write(gsw, 0, 14, 0x2020);
+
+ /* for MT7530 core clock = 500Mhz */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x40e);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ _mt7620_mii_write(gsw, 0, 14, 0x119);
+
+ /* enable MT7530 PLL */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x40d);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ _mt7620_mii_write(gsw, 0, 14, 0x2820);
+
+ usleep_range(20, 40);
+
+ /* enable MT7530 core clock */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x410);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ }
+
+ /* RGMII */
+ _mt7620_mii_write(gsw, 0, 14, 0x1);
+
+ /* set MT7530 central align */
+ mt7530_mdio_w32(gsw, MT7530_P6ECR, P6ECR_INTF_MODE_RGMII);
+ mt7530_mdio_m32(gsw, TRGMII_TXCTRL_TXC_INV, 0,
+ MT7530_TRGMII_TXCTRL);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TCK_CTRL, 0x855);
+
+ /* delay setting for 10/1000M */
+ mt7530_mdio_w32(gsw, MT7530_P5RGMIIRXCR,
+ P5RGMIIRXCR_C_ALIGN | P5RGMIIRXCR_DELAY_2);
+ mt7530_mdio_w32(gsw, MT7530_P5RGMIITXCR, P5RGMIITXCR_DELAY_2);
+
+ /* lower Tx Driving*/
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x44);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x44);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x44);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x44);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x44);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x44);
+
+ /* turn on all PHYs */
+ for (i = 0; i <= 4; i++) {
+ val = _mt7620_mii_read(gsw, i, 0);
+ val &= ~BIT(11);
+ _mt7620_mii_write(gsw, i, 0, val);
+ }
+
+ /* enable irq */
+ mt7530_mdio_m32(gsw, 0, 3 << 16, MT7530_SYS_INT_EN);
+}
+
+static const struct of_device_id mediatek_gsw_match[] = {
+ { .compatible = "mediatek,mt7621-gsw" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
+
+int mtk_gsw_init(struct mtk_eth *eth)
+{
+ struct device_node *np = eth->switch_np;
+ struct platform_device *pdev = of_find_device_by_node(np);
+ struct mt7620_gsw *gsw;
+
+ if (!pdev)
+ return -ENODEV;
+
+ if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
+ return -EINVAL;
+
+ gsw = platform_get_drvdata(pdev);
+ eth->sw_priv = gsw;
+
+ mt7621_hw_init(eth, gsw, np);
+
+ if (gsw->irq) {
+ request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
+ "gsw", eth);
+ mt7530_mdio_w32(gsw, MT7530_SYS_INT_EN, 0x1f);
+ }
+
+ return 0;
+}
+
+static int mt7621_gsw_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct mt7620_gsw *gsw;
+
+ gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
+ if (!gsw)
+ return -ENOMEM;
+
+ gsw->base = devm_ioremap_resource(&pdev->dev, res);
+ if (!gsw->base)
+ return -EADDRNOTAVAIL;
+
+ gsw->dev = &pdev->dev;
+ gsw->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+
+ platform_set_drvdata(pdev, gsw);
+
+ return 0;
+}
+
+static int mt7621_gsw_remove(struct platform_device *pdev)
+{
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver gsw_driver = {
+ .probe = mt7621_gsw_probe,
+ .remove = mt7621_gsw_remove,
+ .driver = {
+ .name = "mt7621-gsw",
+ .owner = THIS_MODULE,
+ .of_match_table = mediatek_gsw_match,
+ },
+};
+
+module_platform_driver(gsw_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
diff --git a/drivers/net/ethernet/mediatek/gsw_mt7623.c b/drivers/net/ethernet/mediatek/gsw_mt7623.c
new file mode 100644
index 0000000..a64bae1
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/gsw_mt7623.c
@@ -0,0 +1,417 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+
+void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
+{
+ iowrite32(val, gsw->base + reg);
+}
+
+u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
+{
+ return ioread32(gsw->base + reg);
+}
+
+void mtk_switch_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, unsigned reg)
+{
+ u32 val = ioread32(gsw->base + reg);
+
+ val &= mask;
+ val |= set;
+
+ iowrite32(val, gsw->base + reg);
+}
+
+static irqreturn_t gsw_interrupt_mt7623(int irq, void *_eth)
+{
+ struct mtk_eth *eth = (struct mtk_eth *)_eth;
+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
+ u32 reg, i;
+
+ reg = mt7530_mdio_r32(gsw, MT7530_SYS_INT_STS);
+
+ for (i = 0; i < 5; i++) {
+ unsigned int link;
+
+ if ((reg & BIT(i)) == 0)
+ continue;
+
+ link = mt7530_mdio_r32(gsw, MT7530_PMSR_P(i)) & 0x1;
+
+ if (link == eth->link[i])
+ continue;
+
+ eth->link[i] = link;
+ if (link)
+ dev_info(gsw->dev, "port %d link up\n", i);
+ else
+ dev_info(gsw->dev, "port %d link down\n", i);
+ }
+
+ mt7530_mdio_w32(gsw, MT7530_SYS_INT_STS, 0x1f);
+
+ return IRQ_HANDLED;
+}
+
+static void mt7623_hw_init(struct mtk_eth *eth, struct mt7620_gsw *gsw,
+ struct device_node *np)
+{
+ u32 i;
+ u32 val, reg;
+ u32 xtal_mode;
+
+ regmap_update_bits(gsw->ethsys, ETHSYS_CLKCFG0,
+ ETHSYS_TRGMII_CLK_SEL362_5,
+ ETHSYS_TRGMII_CLK_SEL362_5);
+
+ /* reset the TRGMII core */
+ mtk_switch_m32(gsw, 0, INTF_MODE_TRGMII, GSW_INTF_MODE);
+ mtk_switch_m32(gsw, 0, TRGMII_RCK_CTRL_RX_RST, GSW_TRGMII_RCK_CTRL);
+
+ /* Hardware reset Switch */
+ mtk_reset(eth, RST_CTRL_MCM);
+
+ /* Wait for Switch Reset Completed*/
+ for (i = 0; i < 100; i++) {
+ mdelay(10);
+ if (mt7530_mdio_r32(gsw, MT7530_HWTRAP))
+ break;
+ }
+
+ /* turn off all PHYs */
+ for (i = 0; i <= 4; i++) {
+ val = _mt7620_mii_read(gsw, i, 0x0);
+ val |= BIT(11);
+ _mt7620_mii_write(gsw, i, 0x0, val);
+ }
+
+ /* reset the switch */
+ mt7530_mdio_w32(gsw, MT7530_SYS_CTRL,
+ SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+ udelay(100);
+
+ /* GE1, Force 1000M/FD, FC ON */
+ mtk_switch_w32(gsw, MAC_MCR_FIXED_LINK_FC, MTK_MAC_P1_MCR);
+ mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK_FC);
+
+ /* GE2, Force 1000M/FD, FC ON */
+ mtk_switch_w32(gsw, MAC_MCR_FIXED_LINK_FC, MTK_MAC_P2_MCR);
+ mt7530_mdio_w32(gsw, MT7530_PMCR_P(5), PMCR_FIXED_LINK_FC);
+
+ regmap_read(gsw->ethsys, ETHSYS_SYSCFG0, ®);
+ /* clear the GE2_MODE bits, setting the port to RGMII */
+ reg &= ~(0x3 << 14);
+ /* clear the GE1_MODE bits, setting the port to RGMII */
+ reg &= ~(0x3 << 12);
+ regmap_write(gsw->ethsys, ETHSYS_SYSCFG0, reg);
+
+ /* Enable Port 6, P5 as GMAC5, P5 disable */
+ val = mt7530_mdio_r32(gsw, MT7530_MHWTRAP);
+ /* Enable Port 6 */
+ val &= ~MHWTRAP_P6_DIS;
+ /* Enable Port 5 */
+ val &= ~MHWTRAP_P5_DIS;
+ /* Port 5 as GMAC */
+ val |= MHWTRAP_P5_MAC_SEL;
+ /* Port 5 Interface mode */
+ val |= MHWTRAP_P5_RGMII_MODE;
+ /* Set MT7530 phy direct access mode**/
+ val &= ~MHWTRAP_PHY_ACCESS;
+ /* manual override of HW-Trap */
+ val |= MHWTRAP_MANUAL;
+ mt7530_mdio_w32(gsw, MT7530_MHWTRAP, val);
+
+ xtal_mode = mt7530_mdio_r32(gsw, MT7530_HWTRAP);
+ xtal_mode >>= HWTRAP_XTAL_SHIFT;
+ xtal_mode &= HWTRAP_XTAL_MASK;
+ if (xtal_mode == MT7623_XTAL_40) {
+ /* disable MT7530 core clock */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x410);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ _mt7620_mii_write(gsw, 0, 14, 0x0);
+
+ /* disable MT7530 PLL */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x40d);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ _mt7620_mii_write(gsw, 0, 14, 0x2020);
+
+ /* for MT7530 core clock = 500Mhz */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x40e);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ _mt7620_mii_write(gsw, 0, 14, 0x119);
+
+ /* enable MT7530 PLL */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x40d);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ _mt7620_mii_write(gsw, 0, 14, 0x2820);
+
+ udelay(20);
+
+ /* enable MT7530 core clock */
+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
+ _mt7620_mii_write(gsw, 0, 14, 0x410);
+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
+ }
+
+ /* RGMII */
+ _mt7620_mii_write(gsw, 0, 14, 0x1);
+
+ /* set MT7530 central align */
+ mt7530_mdio_m32(gsw, ~BIT(0), BIT(1), MT7530_P6ECR);
+ mt7530_mdio_m32(gsw, ~BIT(30), 0, MT7530_TRGMII_TXCTRL);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TCK_CTRL, 0x855);
+
+ /* delay setting for 10/1000M */
+ mt7530_mdio_w32(gsw, MT7530_P5RGMIIRXCR, 0x104);
+ mt7530_mdio_w32(gsw, MT7530_P5RGMIITXCR, 0x10);
+
+ /* lower Tx Driving */
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x88);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD1_ODT, 0x88);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD2_ODT, 0x88);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD3_ODT, 0x88);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD4_ODT, 0x88);
+ mt7530_mdio_w32(gsw, MT7530_TRGMII_TD5_ODT, 0x88);
+ mt7530_mdio_w32(gsw, MT7530_IO_DRV_CR, 0x11);
+
+ /* Set MT7623/MT7683 TX Driving */
+ mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TD0_ODT);
+ mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TD0_ODT);
+ mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TD0_ODT);
+ mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TD0_ODT);
+ mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TXCTL_ODT);
+ mtk_switch_w32(gsw, 0x88, GSW_TRGMII_TCK_ODT);
+
+ /* disable EEE */
+ for (i = 0; i <= 4; i++) {
+ _mt7620_mii_write(gsw, i, 13, 0x7);
+ _mt7620_mii_write(gsw, i, 14, 0x3C);
+ _mt7620_mii_write(gsw, i, 13, 0x4007);
+ _mt7620_mii_write(gsw, i, 14, 0x0);
+
+ /* Increase SlvDPSready time */
+ _mt7620_mii_write(gsw, i, 31, 0x52b5);
+ _mt7620_mii_write(gsw, i, 16, 0xafae);
+ _mt7620_mii_write(gsw, i, 18, 0x2f);
+ _mt7620_mii_write(gsw, i, 16, 0x8fae);
+
+ /* Incease post_update_timer */
+ _mt7620_mii_write(gsw, i, 31, 0x3);
+ _mt7620_mii_write(gsw, i, 17, 0x4b);
+
+ /* Adjust 100_mse_threshold */
+ _mt7620_mii_write(gsw, i, 13, 0x1e);
+ _mt7620_mii_write(gsw, i, 14, 0x123);
+ _mt7620_mii_write(gsw, i, 13, 0x401e);
+ _mt7620_mii_write(gsw, i, 14, 0xffff);
+
+ /* Disable mcc */
+ _mt7620_mii_write(gsw, i, 13, 0x1e);
+ _mt7620_mii_write(gsw, i, 14, 0xa6);
+ _mt7620_mii_write(gsw, i, 13, 0x401e);
+ _mt7620_mii_write(gsw, i, 14, 0x300);
+
+ /* Disable HW auto downshift*/
+ _mt7620_mii_write(gsw, i, 31, 0x1);
+ val = _mt7620_mii_read(gsw, i, 0x14);
+ val &= ~BIT(4);
+ _mt7620_mii_write(gsw, i, 0x14, val);
+ }
+
+ /* turn on all PHYs */
+ for (i = 0; i <= 4; i++) {
+ val = _mt7620_mii_read(gsw, i, 0);
+ val &= ~BIT(11);
+ _mt7620_mii_write(gsw, i, 0, val);
+ }
+
+ /* enable irq */
+ mt7530_mdio_m32(gsw, 0, TOP_SIG_CTRL_NORMAL, MT7530_TOP_SIG_CTRL);
+}
+
+static const struct of_device_id mediatek_gsw_match[] = {
+ { .compatible = "mediatek,mt7623-gsw" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
+
+int mtk_gsw_init(struct mtk_eth *eth)
+{
+ struct device_node *np = eth->switch_np;
+ struct platform_device *pdev = of_find_device_by_node(np);
+ struct mt7620_gsw *gsw;
+
+ if (!pdev)
+ return -ENODEV;
+
+ if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
+ return -EINVAL;
+
+ gsw = platform_get_drvdata(pdev);
+ if (!gsw)
+ return -ENODEV;
+ eth->sw_priv = gsw;
+
+ mt7623_hw_init(eth, gsw, np);
+
+ request_threaded_irq(gsw->irq, gsw_interrupt_mt7623, NULL, 0,
+ "gsw", eth);
+ mt7530_mdio_w32(gsw, MT7530_SYS_INT_EN, 0x1f);
+
+ return 0;
+}
+
+static int mt7623_gsw_probe(struct platform_device *pdev)
+{
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *pctl;
+ int reset_pin, ret;
+ struct mt7620_gsw *gsw;
+ struct regulator *supply;
+
+ gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
+ if (!gsw)
+ return -ENOMEM;
+
+ gsw->dev = &pdev->dev;
+ gsw->irq = irq_of_parse_and_map(np, 0);
+ if (gsw->irq < 0)
+ return -EINVAL;
+
+ gsw->base = devm_ioremap_resource(&pdev->dev, res);
+ if (!gsw->base)
+ return -EADDRNOTAVAIL;
+
+ gsw->ethsys = syscon_regmap_lookup_by_phandle(np, "mediatek,ethsys");
+ if (IS_ERR(gsw->ethsys))
+ return PTR_ERR(gsw->ethsys);
+
+ reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0);
+ if (reset_pin < 0)
+ return reset_pin;
+
+ pctl = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
+ if (IS_ERR(pctl))
+ return PTR_ERR(pctl);
+
+ gsw->pctl = syscon_node_to_regmap(pctl);
+ if (IS_ERR(pctl))
+ return PTR_ERR(pctl);
+
+ ret = devm_gpio_request(&pdev->dev, reset_pin, "mt7530-reset");
+ if (ret)
+ return ret;
+
+ gsw->clk_gsw = devm_clk_get(&pdev->dev, "esw");
+ gsw->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
+ gsw->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
+ gsw->clk_trgpll = devm_clk_get(&pdev->dev, "trgpll");
+
+ if (IS_ERR(gsw->clk_gsw) || IS_ERR(gsw->clk_gp1) ||
+ IS_ERR(gsw->clk_gp2) || IS_ERR(gsw->clk_trgpll))
+ return -ENODEV;
+
+ supply = devm_regulator_get(&pdev->dev, "mt7530");
+ if (IS_ERR(supply))
+ return PTR_ERR(supply);
+
+ regulator_set_voltage(supply, 1000000, 1000000);
+ ret = regulator_enable(supply);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to enable reg-7530: %d\n", ret);
+ return ret;
+ }
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_get_sync(&pdev->dev);
+
+ ret = clk_set_rate(gsw->clk_trgpll, 500000000);
+ if (ret)
+ return ret;
+
+ clk_prepare_enable(gsw->clk_gsw);
+ clk_prepare_enable(gsw->clk_gp1);
+ clk_prepare_enable(gsw->clk_gp2);
+ clk_prepare_enable(gsw->clk_trgpll);
+
+ gpio_direction_output(reset_pin, 0);
+ udelay(1000);
+ gpio_set_value(reset_pin, 1);
+ mdelay(100);
+
+ /* Set GE2 driving and slew rate */
+ regmap_write(gsw->pctl, GPIO_DRV_SEL10, 0xa00);
+
+ /* set GE2 TDSEL */
+ regmap_write(gsw->pctl, GPIO_OD33_CTRL8, 0x5);
+
+ /* set GE2 TUNE */
+ regmap_write(gsw->pctl, GPIO_BIAS_CTRL, 0x0);
+
+ platform_set_drvdata(pdev, gsw);
+
+ return 0;
+}
+
+static int mt7623_gsw_remove(struct platform_device *pdev)
+{
+ struct mt7620_gsw *gsw = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(gsw->clk_gsw);
+ clk_disable_unprepare(gsw->clk_gp1);
+ clk_disable_unprepare(gsw->clk_gp2);
+ clk_disable_unprepare(gsw->clk_trgpll);
+
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver gsw_driver = {
+ .probe = mt7623_gsw_probe,
+ .remove = mt7623_gsw_remove,
+ .driver = {
+ .name = "mt7623-gsw",
+ .owner = THIS_MODULE,
+ .of_match_table = mediatek_gsw_match,
+ },
+};
+
+module_platform_driver(gsw_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7623 SoC");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH V2 05/12] net-next: mediatek: add support for rt2880
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (3 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 04/12] net-next: mediatek: add gigabit switch driver (GSW) John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 14:21 ` [PATCH V2 06/12] net-next: mediatek: add support for rt3050 John Crispin
` (6 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
rt2880 is the oldest SoC with this core. It has a single gBit port that
will normally be attached to an external phy or switch. The patch also
adds the code required to drive the mdio bus os these SoCs. According to
the datasheet, this SoC has has checksum offloading and 2 byte dma padding.
On device testing has however shown that this does not work reliably so we
do not enable it.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
drivers/net/ethernet/mediatek/mdio_rt2880.c | 224 +++++++++++++++++++++++++++
drivers/net/ethernet/mediatek/mdio_rt2880.h | 24 +++
drivers/net/ethernet/mediatek/soc_rt2880.c | 71 +++++++++
3 files changed, 319 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.c
create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.h
create mode 100644 drivers/net/ethernet/mediatek/soc_rt2880.c
diff --git a/drivers/net/ethernet/mediatek/mdio_rt2880.c b/drivers/net/ethernet/mediatek/mdio_rt2880.c
new file mode 100644
index 0000000..25db957
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mdio_rt2880.c
@@ -0,0 +1,224 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+#include "mdio.h"
+
+#define MTK_MDIO_RETRY 1000
+
+static unsigned char *rt2880_speed_str(struct mtk_eth *eth)
+{
+ switch (eth->phy->speed[0]) {
+ case SPEED_1000:
+ return "1000";
+ case SPEED_100:
+ return "100";
+ case SPEED_10:
+ return "10";
+ }
+
+ return "?";
+}
+
+void rt2880_mdio_link_adjust(struct mtk_eth *eth, int port)
+{
+ u32 mdio_cfg;
+
+ if (!eth->link[0]) {
+ netif_carrier_off(*eth->netdev);
+ netdev_info(*eth->netdev, "link down\n");
+ return;
+ }
+
+ mdio_cfg = MTK_MDIO_CFG_TX_CLK_SKEW_200 |
+ MTK_MDIO_CFG_RX_CLK_SKEW_200 |
+ MTK_MDIO_CFG_GP1_FRC_EN;
+
+ if (eth->phy->duplex[0] == DUPLEX_FULL)
+ mdio_cfg |= MTK_MDIO_CFG_GP1_DUPLEX;
+
+ if (eth->phy->tx_fc[0])
+ mdio_cfg |= MTK_MDIO_CFG_GP1_FC_TX;
+
+ if (eth->phy->rx_fc[0])
+ mdio_cfg |= MTK_MDIO_CFG_GP1_FC_RX;
+
+ switch (eth->phy->speed[0]) {
+ case SPEED_10:
+ mdio_cfg |= MTK_MDIO_CFG_GP1_SPEED_10;
+ break;
+ case SPEED_100:
+ mdio_cfg |= MTK_MDIO_CFG_GP1_SPEED_100;
+ break;
+ case SPEED_1000:
+ mdio_cfg |= MTK_MDIO_CFG_GP1_SPEED_1000;
+ break;
+ default:
+ netdev_err(*eth->netdev, "unknown link speed\n");
+ return;
+ }
+
+ mtk_w32(eth, mdio_cfg, MTK_MDIO_CFG);
+
+ netif_carrier_on(*eth->netdev);
+ netdev_info(*eth->netdev, "link up (%sMbps/%s duplex)\n",
+ rt2880_speed_str(eth),
+ (eth->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
+}
+
+static int rt2880_mdio_wait_ready(struct mtk_eth *eth)
+{
+ int retries;
+
+ retries = MTK_MDIO_RETRY;
+ while (1) {
+ u32 t;
+
+ t = mtk_r32(eth, MTK_MDIO_ACCESS);
+ if ((t & BIT(31)) == 0)
+ return 0;
+
+ if (retries-- == 0)
+ break;
+
+ udelay(1);
+ }
+
+ dev_err(eth->dev, "MDIO operation timed out\n");
+ return -ETIMEDOUT;
+}
+
+int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+ struct mtk_eth *eth = bus->priv;
+ int err;
+ u32 t;
+
+ err = rt2880_mdio_wait_ready(eth);
+ if (err)
+ return 0xffff;
+
+ t = (phy_addr << 24) | (phy_reg << 16);
+ mtk_w32(eth, t, MTK_MDIO_ACCESS);
+ t |= BIT(31);
+ mtk_w32(eth, t, MTK_MDIO_ACCESS);
+
+ err = rt2880_mdio_wait_ready(eth);
+ if (err)
+ return 0xffff;
+
+ pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
+ phy_addr, phy_reg, mtk_r32(eth, MTK_MDIO_ACCESS) & 0xffff);
+
+ return mtk_r32(eth, MTK_MDIO_ACCESS) & 0xffff;
+}
+
+int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
+{
+ struct mtk_eth *eth = bus->priv;
+ int err;
+ u32 t;
+
+ pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
+ phy_addr, phy_reg, mtk_r32(eth, MTK_MDIO_ACCESS) & 0xffff);
+
+ err = rt2880_mdio_wait_ready(eth);
+ if (err)
+ return err;
+
+ t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
+ mtk_w32(eth, t, MTK_MDIO_ACCESS);
+ t |= BIT(31);
+ mtk_w32(eth, t, MTK_MDIO_ACCESS);
+
+ return rt2880_mdio_wait_ready(eth);
+}
+
+void rt2880_port_init(struct mtk_eth *eth, struct mtk_mac *mac,
+ struct device_node *np)
+{
+ const __be32 *id = of_get_property(np, "reg", NULL);
+ const __be32 *link;
+ int size;
+ int phy_mode;
+
+ if (!id || (be32_to_cpu(*id) != 0)) {
+ pr_err("%s: invalid port id\n", np->name);
+ return;
+ }
+
+ eth->phy->phy_fixed[0] = of_get_property(np,
+ "mediatek,fixed-link", &size);
+ if (eth->phy->phy_fixed[0] &&
+ (size != (4 * sizeof(*eth->phy->phy_fixed[0])))) {
+ pr_err("%s: invalid fixed link property\n", np->name);
+ eth->phy->phy_fixed[0] = NULL;
+ return;
+ }
+
+ phy_mode = of_get_phy_mode(np);
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ break;
+ case PHY_INTERFACE_MODE_MII:
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ break;
+ default:
+ if (!eth->phy->phy_fixed[0])
+ dev_err(eth->dev, "port %d - invalid phy mode\n",
+ eth->phy->speed[0]);
+ break;
+ }
+
+ eth->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
+ if (!eth->phy->phy_node[0] && !eth->phy->phy_fixed[0])
+ return;
+
+ if (eth->phy->phy_fixed[0]) {
+ link = eth->phy->phy_fixed[0];
+ eth->phy->speed[0] = be32_to_cpup(link++);
+ eth->phy->duplex[0] = be32_to_cpup(link++);
+ eth->phy->tx_fc[0] = be32_to_cpup(link++);
+ eth->phy->rx_fc[0] = be32_to_cpup(link++);
+
+ eth->link[0] = 1;
+ switch (eth->phy->speed[0]) {
+ case SPEED_10:
+ break;
+ case SPEED_100:
+ break;
+ case SPEED_1000:
+ break;
+ default:
+ dev_err(eth->dev, "invalid link speed: %d\n",
+ eth->phy->speed[0]);
+ eth->phy->phy_fixed[0] = 0;
+ return;
+ }
+ dev_info(eth->dev, "using fixed link parameters\n");
+ rt2880_mdio_link_adjust(eth, 0);
+ return;
+ }
+
+ if (eth->phy->phy_node[0] && eth->mii_bus->phy_map[0])
+ mtk_connect_phy_node(eth, mac, eth->phy->phy_node[0]);
+}
diff --git a/drivers/net/ethernet/mediatek/mdio_rt2880.h b/drivers/net/ethernet/mediatek/mdio_rt2880.h
new file mode 100644
index 0000000..26f273d
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mdio_rt2880.h
@@ -0,0 +1,24 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#ifndef _RALINK_MDIO_RT2880_H__
+#define _RALINK_MDIO_RT2880_H__
+
+void rt2880_mdio_link_adjust(struct mtk_eth *eth, int port);
+int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
+int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
+void rt2880_port_init(struct mtk_eth *eth, struct mtk_mac *mac,
+ struct device_node *np);
+
+#endif
diff --git a/drivers/net/ethernet/mediatek/soc_rt2880.c b/drivers/net/ethernet/mediatek/soc_rt2880.c
new file mode 100644
index 0000000..854d5a7
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/soc_rt2880.c
@@ -0,0 +1,71 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+
+#define RT2880_RESET_FE BIT(18)
+
+void rt2880_mtk_reset(struct mtk_eth *eth)
+{
+ mtk_reset(eth, RT2880_RESET_FE);
+}
+
+static int rt2880_fwd_config(struct mtk_eth *eth)
+{
+ int ret;
+
+ ret = mtk_set_clock_cycle(eth);
+ if (ret)
+ return ret;
+
+ mtk_fwd_config(eth);
+ mtk_w32(eth, MTK_PSE_FQFC_CFG_INIT, MTK_PSE_FQ_CFG);
+ mtk_csum_config(eth);
+
+ return ret;
+}
+
+struct mtk_soc_data rt2880_data = {
+ .hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX,
+ .dma_type = MTK_PDMA,
+ .dma_ring_size = 128,
+ .napi_weight = 32,
+ .padding_64b = 1,
+ .padding_bug = 1,
+ .mac_count = 1,
+ .txd4 = TX_DMA_DESP4_DEF,
+ .reset_fe = rt2880_mtk_reset,
+ .fwd_config = rt2880_fwd_config,
+ .pdma_glo_cfg = MTK_PDMA_SIZE_8DWORDS,
+ .checksum_bit = RX_DMA_L4VALID,
+ .rx_int = MTK_RX_DONE_INT,
+ .tx_int = MTK_TX_DONE_INT,
+ .status_int = MTK_CNT_GDM_AF,
+ .mdio_read = rt2880_mdio_read,
+ .mdio_write = rt2880_mdio_write,
+ .mdio_adjust_link = rt2880_mdio_link_adjust,
+ .port_init = rt2880_port_init,
+};
+
+const struct of_device_id of_mtk_match[] = {
+ { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_mtk_match);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH V2 06/12] net-next: mediatek: add support for rt3050
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (4 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 05/12] net-next: mediatek: add support for rt2880 John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 14:21 ` [PATCH V2 07/12] net-next: mediatek: add support for rt3883 John Crispin
` (5 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
Add support for SoCs from the rt3050 family. This include rt3050, rt3052,
rt3352 and rt5350. These all have a builtin 5 port 100mbit switch (ESW).
There are a huge amount of CPEs in the wild that use this SoC as they were
some of the first to have builtin 802.11n wmacs.
rt5350 was an ultra low cost device, that had seen some changes in the
reset bits and register layout. However as the difference are rather minor
support for all of these is in the same driver. OpenWrt builds generic
images where the kernel works on all of the SoCs listed above.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
drivers/net/ethernet/mediatek/soc_rt3050.c | 138 ++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/soc_rt3050.c
diff --git a/drivers/net/ethernet/mediatek/soc_rt3050.c b/drivers/net/ethernet/mediatek/soc_rt3050.c
new file mode 100644
index 0000000..5c4739a
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/soc_rt3050.c
@@ -0,0 +1,138 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "esw_rt3050.h"
+#include "mdio_rt2880.h"
+
+#define RT305X_RESET_FE BIT(21)
+#define RT305X_RESET_ESW BIT(23)
+
+static const u16 rt5350_reg_table[MTK_REG_COUNT] = {
+ [MTK_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
+ [MTK_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
+ [MTK_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
+ [MTK_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+ [MTK_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+ [MTK_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+ [MTK_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+ [MTK_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+ [MTK_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+ [MTK_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+ [MTK_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+ [MTK_REG_MTK_INT_ENABLE] = RT5350_MTK_INT_ENABLE,
+ [MTK_REG_MTK_INT_STATUS] = RT5350_MTK_INT_STATUS,
+ [MTK_REG_MTK_RST_GL] = 0,
+ [MTK_REG_MTK_DMA_VID_BASE] = 0,
+};
+
+static int rt3050_fwd_config(struct mtk_eth *eth)
+{
+ int ret;
+
+ if (ralink_soc != RT305X_SOC_RT3052) {
+ ret = mtk_set_clock_cycle(eth);
+ if (ret)
+ return ret;
+ }
+
+ mtk_fwd_config(eth);
+ if (ralink_soc != RT305X_SOC_RT3352)
+ mtk_w32(eth, MTK_PSE_FQFC_CFG_INIT, MTK_PSE_FQ_CFG);
+ mtk_csum_config(eth);
+
+ return 0;
+}
+
+static void rt305x_mtk_reset(struct mtk_eth *eth)
+{
+ mtk_reset(eth, RT305X_RESET_FE);
+}
+
+static void rt5350_set_mac(struct mtk_mac *mac, unsigned char *hwaddr)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mac->hw->page_lock, flags);
+ mtk_w32(mac->hw, (hwaddr[0] << 8) | hwaddr[1], RT5350_SDM_MAC_ADRH);
+ mtk_w32(mac->hw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
+ (hwaddr[4] << 8) | hwaddr[5],
+ RT5350_SDM_MAC_ADRL);
+ spin_unlock_irqrestore(&mac->hw->page_lock, flags);
+}
+
+static int rt5350_fwd_config(struct mtk_eth *eth)
+{
+ /* enable rx checksums */
+ mtk_w32(eth,
+ mtk_r32(eth, RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
+ RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
+ RT5350_SDM_CFG);
+ return 0;
+}
+
+static void rt5350_mtk_reset(struct mtk_eth *eth)
+{
+ mtk_reset(eth, RT305X_RESET_FE | RT305X_RESET_ESW);
+}
+
+static struct mtk_soc_data rt3050_data = {
+ .hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
+ NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX,
+ .dma_type = MTK_PDMA,
+ .dma_ring_size = 128,
+ .napi_weight = 32,
+ .padding_64b = 1,
+ .padding_bug = 1,
+ .has_switch = 1,
+ .mac_count = 1,
+ .reset_fe = rt305x_mtk_reset,
+ .fwd_config = rt3050_fwd_config,
+ .switch_init = mtk_esw_init,
+ .pdma_glo_cfg = MTK_PDMA_SIZE_8DWORDS,
+ .checksum_bit = RX_DMA_L4VALID,
+ .rx_int = MTK_RX_DONE_INT,
+ .tx_int = MTK_TX_DONE_INT,
+ .status_int = MTK_CNT_GDM_AF,
+};
+
+static struct mtk_soc_data rt5350_data = {
+ .hw_features = NETIF_F_SG | NETIF_F_RXCSUM,
+ .dma_type = MTK_PDMA,
+ .dma_ring_size = 128,
+ .napi_weight = 32,
+ .has_switch = 1,
+ .mac_count = 1,
+ .reg_table = rt5350_reg_table,
+ .reset_fe = rt5350_mtk_reset,
+ .set_mac = rt5350_set_mac,
+ .fwd_config = rt5350_fwd_config,
+ .switch_init = mtk_esw_init,
+ .pdma_glo_cfg = MTK_PDMA_SIZE_8DWORDS,
+ .checksum_bit = RX_DMA_L4VALID,
+ .rx_int = RT5350_RX_DONE_INT,
+ .tx_int = RT5350_TX_DONE_INT,
+};
+
+const struct of_device_id of_mtk_match[] = {
+ { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
+ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_mtk_match);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH V2 07/12] net-next: mediatek: add support for rt3883
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (5 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 06/12] net-next: mediatek: add support for rt3050 John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 14:21 ` [PATCH V2 08/12] net-next: mediatek: add support for mt7620 John Crispin
` (4 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
Add support for rt3883 and its smaller version rt3662. They both have a
single gBit port that will normally be attached to an external phy or
switch. There are not many rt3883 based routers in the field. I think
there is a second MAC on these SoCs. Due to lack of hardware utilizing this
I never added support. RT3883 is somewhat unique as it is the only SoC made
by Ralink that uses the mips74 core.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
drivers/net/ethernet/mediatek/soc_rt3883.c | 72 ++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/soc_rt3883.c
diff --git a/drivers/net/ethernet/mediatek/soc_rt3883.c b/drivers/net/ethernet/mediatek/soc_rt3883.c
new file mode 100644
index 0000000..8138370
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/soc_rt3883.c
@@ -0,0 +1,72 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "mdio_rt2880.h"
+
+#define RT3883_RSTCTRL_FE BIT(21)
+
+static void rt3883_mtk_reset(struct mtk_eth *eth)
+{
+ mtk_reset(eth, RT3883_RSTCTRL_FE);
+}
+
+static int rt3883_fwd_config(struct mtk_eth *eth)
+{
+ int ret;
+
+ ret = mtk_set_clock_cycle(eth);
+ if (ret)
+ return ret;
+
+ mtk_fwd_config(eth);
+ mtk_w32(eth, MTK_PSE_FQFC_CFG_256Q, MTK_PSE_FQ_CFG);
+ mtk_csum_config(eth);
+
+ return ret;
+}
+
+static struct mtk_soc_data rt3883_data = {
+ .hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
+ NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX,
+ .dma_type = MTK_PDMA,
+ .dma_ring_size = 128,
+ .napi_weight = 32,
+ .padding_64b = 1,
+ .padding_bug = 1,
+ .mac_count = 1,
+ .txd4 = TX_DMA_DESP4_DEF,
+ .reset_fe = rt3883_mtk_reset,
+ .fwd_config = rt3883_fwd_config,
+ .pdma_glo_cfg = MTK_PDMA_SIZE_8DWORDS,
+ .rx_int = MTK_RX_DONE_INT,
+ .tx_int = MTK_TX_DONE_INT,
+ .status_int = MTK_CNT_GDM_AF,
+ .checksum_bit = RX_DMA_L4VALID,
+ .mdio_read = rt2880_mdio_read,
+ .mdio_write = rt2880_mdio_write,
+ .mdio_adjust_link = rt2880_mdio_link_adjust,
+ .port_init = rt2880_port_init,
+};
+
+const struct of_device_id of_mtk_match[] = {
+ { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_mtk_match);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH V2 08/12] net-next: mediatek: add support for mt7620
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (6 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 07/12] net-next: mediatek: add support for rt3883 John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 14:21 ` [PATCH V2 09/12] net-next: mediatek: add support for mt7621 John Crispin
` (3 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
Add support for SoCs from the mt7620 family. These all have one dedicated
external gbit port and a builtin 5 port 100mbit switch. Additionally one
of the 5 switch ports can be changed to become an additional gbit port
that we can attach a phy to. MT7620 was the first SoC released after
Ralink was acquired by MTK and has seen a lot of changes to the core.
With MT7620 we have seen the addition of some advanced features such as
TX vlan offloading, RX scatter gather and TSO. Newer MTK SoCs are based on
this design.
Although the builtin MT7530 is gbit capable, the builtin PHYs are only
100mbit. There are boards in the wild that use one of the gbit MACs to
attach an external MT7530. For this to work a few hacks need to be applied
to reorganize the MDIO address mappings and autopolling for the SoC to
correctly work with the external switch. This is however not part of the
series and will be part of a later series once we evaluated if we want to
use DSA or switchdev.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
drivers/net/ethernet/mediatek/mdio_mt7620.c | 168 +++++++++++++++
drivers/net/ethernet/mediatek/soc_mt7620.c | 296 +++++++++++++++++++++++++++
2 files changed, 464 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/mdio_mt7620.c
create mode 100644 drivers/net/ethernet/mediatek/soc_mt7620.c
diff --git a/drivers/net/ethernet/mediatek/mdio_mt7620.c b/drivers/net/ethernet/mediatek/mdio_mt7620.c
new file mode 100644
index 0000000..b9e0eb2
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/mdio_mt7620.c
@@ -0,0 +1,168 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+#include "mdio.h"
+
+static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
+{
+ unsigned long t_start = jiffies;
+
+ while (1) {
+ if (!(mtk_switch_r32(gsw,
+ gsw->piac_offset + MT7620_GSW_REG_PIAC) &
+ GSW_MDIO_ACCESS))
+ return 0;
+ if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
+ break;
+ }
+
+ dev_err(gsw->dev, "mdio: MDIO timeout\n");
+ return -1;
+}
+
+u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
+ u32 phy_register, u32 write_data)
+{
+ if (mt7620_mii_busy_wait(gsw))
+ return -1;
+
+ write_data &= 0xffff;
+
+ mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
+ (phy_register << GSW_MDIO_REG_SHIFT) |
+ (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
+ MT7620_GSW_REG_PIAC);
+
+ if (mt7620_mii_busy_wait(gsw))
+ return -1;
+
+ return 0;
+}
+
+u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
+{
+ u32 d;
+
+ if (mt7620_mii_busy_wait(gsw))
+ return 0xffff;
+
+ mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
+ (phy_reg << GSW_MDIO_REG_SHIFT) |
+ (phy_addr << GSW_MDIO_ADDR_SHIFT),
+ MT7620_GSW_REG_PIAC);
+
+ if (mt7620_mii_busy_wait(gsw))
+ return 0xffff;
+
+ d = mtk_switch_r32(gsw, MT7620_GSW_REG_PIAC) & 0xffff;
+
+ return d;
+}
+
+int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
+{
+ struct mtk_eth *eth = bus->priv;
+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
+
+ return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
+}
+
+int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+ struct mtk_eth *eth = bus->priv;
+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
+
+ return _mt7620_mii_read(gsw, phy_addr, phy_reg);
+}
+
+void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
+{
+ _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
+ _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
+ _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
+}
+
+u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
+{
+ u16 high, low;
+
+ _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
+ low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
+ high = _mt7620_mii_read(gsw, 0x1f, 0x10);
+
+ return (high << 16) | (low & 0xffff);
+}
+
+void mt7530_mdio_m32(struct mt7620_gsw *gsw, u32 mask, u32 set, u32 reg)
+{
+ u32 val = mt7530_mdio_r32(gsw, reg);
+
+ val &= mask;
+ val |= set;
+ mt7530_mdio_w32(gsw, reg, val);
+}
+
+static unsigned char *mtk_speed_str(int speed)
+{
+ switch (speed) {
+ case 2:
+ case SPEED_1000:
+ return "1000";
+ case 1:
+ case SPEED_100:
+ return "100";
+ case 0:
+ case SPEED_10:
+ return "10";
+ }
+
+ return "? ";
+}
+
+int mt7620_has_carrier(struct mtk_eth *eth)
+{
+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
+ int i;
+
+ for (i = 0; i < GSW_PORT6; i++)
+ if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
+ return 1;
+ return 0;
+}
+
+void mt7620_print_link_state(struct mtk_eth *eth, int port, int link,
+ int speed, int duplex)
+{
+ struct mt7620_gsw *gsw = eth->sw_priv;
+
+ if (link)
+ dev_info(gsw->dev, "port %d link up (%sMbps/%s duplex)\n",
+ port, mtk_speed_str(speed),
+ (duplex) ? "Full" : "Half");
+ else
+ dev_info(gsw->dev, "port %d link down\n", port);
+}
+
+void mt7620_mdio_link_adjust(struct mtk_eth *eth, int port)
+{
+ mt7620_print_link_state(eth, port, eth->link[port],
+ eth->phy->speed[port],
+ (eth->phy->duplex[port] == DUPLEX_FULL));
+}
diff --git a/drivers/net/ethernet/mediatek/soc_mt7620.c b/drivers/net/ethernet/mediatek/soc_mt7620.c
new file mode 100644
index 0000000..faf2a84
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/soc_mt7620.c
@@ -0,0 +1,296 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/if_vlan.h>
+#include <linux/of_net.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include <mt7620.h>
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+#include "mdio.h"
+
+#define MT7620_CDMA_CSG_CFG 0x400
+#define MT7620_DMA_VID (MT7620_CDMA_CSG_CFG + 0x30)
+#define MT7620_RESET_FE BIT(21)
+#define MT7620_RESET_ESW BIT(23)
+#define MT7620_L4_VALID BIT(23)
+
+#define MT7620_TX_DMA_UDF BIT(15)
+#define TX_DMA_FP_BMAP ((0xff) << 19)
+
+#define CDMA_ICS_EN BIT(2)
+#define CDMA_UCS_EN BIT(1)
+#define CDMA_TCS_EN BIT(0)
+
+#define GDMA_ICS_EN BIT(22)
+#define GDMA_TCS_EN BIT(21)
+#define GDMA_UCS_EN BIT(20)
+#define GDMA_FRC_P_MASK 0x07
+
+/* frame engine counters */
+#define MT7620_REG_MIB_OFFSET 0x1000
+#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
+#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
+#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
+
+#define GSW_REG_GDMA1_MAC_ADRL 0x508
+#define GSW_REG_GDMA1_MAC_ADRH 0x50C
+
+#define MT7620_MTK_RST_GL 0x04
+#define MT7620_MTK_INT_STATUS2 0x08
+
+/* MTK_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
+ * but after test it should be BIT(13).
+ */
+#define MT7620_MTK_GDM1_AF BIT(13)
+
+static const u16 mt7620_reg_table[MTK_REG_COUNT] = {
+ [MTK_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
+ [MTK_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
+ [MTK_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
+ [MTK_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+ [MTK_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+ [MTK_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+ [MTK_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+ [MTK_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+ [MTK_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+ [MTK_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+ [MTK_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+ [MTK_REG_MTK_INT_ENABLE] = RT5350_MTK_INT_ENABLE,
+ [MTK_REG_MTK_INT_STATUS] = RT5350_MTK_INT_STATUS,
+ [MTK_REG_MTK_DMA_VID_BASE] = MT7620_DMA_VID,
+ [MTK_REG_MTK_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
+ [MTK_REG_MTK_RST_GL] = MT7620_MTK_RST_GL,
+ [MTK_REG_MTK_INT_STATUS2] = MT7620_MTK_INT_STATUS2,
+};
+
+static void mt7620_set_mac(struct mtk_mac *mac, unsigned char *hwaddr)
+{
+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)mac->hw->sw_priv;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mac->hw->page_lock, flags);
+ mtk_switch_w32(gsw, (hwaddr[0] << 8) | hwaddr[1], GSW_REG_SMACCR1);
+ mtk_switch_w32(gsw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
+ (hwaddr[4] << 8) | hwaddr[5],
+ GSW_REG_SMACCR0);
+ spin_unlock_irqrestore(&mac->hw->page_lock, flags);
+}
+
+/* figure out which is the lowest and highest phy connected and enable
+ * autopolling for those phys
+ */
+static void mt7620_auto_poll(struct mt7620_gsw *gsw)
+{
+ int phy;
+ int lsb = -1, msb = 0;
+
+ for_each_set_bit(phy, &gsw->autopoll, 32) {
+ if (lsb < 0)
+ lsb = phy;
+ msb = phy;
+ }
+
+ if (lsb == msb)
+ lsb--;
+
+ mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
+ (msb << 8) | lsb, MT7620_ESW_PHY_POLLING);
+}
+
+static void mt7620_port_init(struct mtk_eth *eth, struct mtk_mac *mac,
+ struct device_node *np)
+{
+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
+ const __be32 *_id = of_get_property(np, "reg", NULL);
+ int phy_mode, size, id;
+ int shift = 12;
+ u32 val, mask = 0;
+ int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
+
+ if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
+ if (_id)
+ pr_err("%s: invalid port id %d\n", np->name,
+ be32_to_cpu(*_id));
+ else
+ pr_err("%s: invalid port id\n", np->name);
+ return;
+ }
+
+ id = be32_to_cpu(*_id);
+
+ if (id == 4)
+ shift = 14;
+
+ eth->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
+ &size);
+ if (eth->phy->phy_fixed[id] &&
+ (size != (4 * sizeof(*eth->phy->phy_fixed[id])))) {
+ pr_err("%s: invalid fixed link property\n", np->name);
+ eth->phy->phy_fixed[id] = NULL;
+ return;
+ }
+
+ phy_mode = of_get_phy_mode(np);
+ switch (phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ mask = 0;
+ break;
+ case PHY_INTERFACE_MODE_MII:
+ mask = 1;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ mask = 2;
+ break;
+ default:
+ dev_err(eth->dev, "port %d - invalid phy mode\n", id);
+ return;
+ }
+
+ eth->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
+ if (!eth->phy->phy_node[id] && !eth->phy->phy_fixed[id])
+ return;
+
+ val = rt_sysc_r32(SYSC_REG_CFG1);
+ val &= ~(3 << shift);
+ val |= mask << shift;
+ rt_sysc_w32(val, SYSC_REG_CFG1);
+
+ if (eth->phy->phy_fixed[id]) {
+ const __be32 *link = eth->phy->phy_fixed[id];
+ int tx_fc, rx_fc;
+ u32 val = 0;
+
+ eth->phy->speed[id] = be32_to_cpup(link++);
+ tx_fc = be32_to_cpup(link++);
+ rx_fc = be32_to_cpup(link++);
+ eth->phy->duplex[id] = be32_to_cpup(link++);
+ eth->link[id] = 1;
+
+ switch (eth->phy->speed[id]) {
+ case SPEED_10:
+ val = 0;
+ break;
+ case SPEED_100:
+ val = 1;
+ break;
+ case SPEED_1000:
+ val = 2;
+ break;
+ default:
+ dev_err(eth->dev, "invalid link speed: %d\n",
+ eth->phy->speed[id]);
+ eth->phy->phy_fixed[id] = 0;
+ return;
+ }
+ val = PMCR_SPEED(val);
+ val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
+ PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
+ if (tx_fc)
+ val |= PMCR_TX_FC;
+ if (rx_fc)
+ val |= PMCR_RX_FC;
+ if (eth->phy->duplex[id])
+ val |= PMCR_DUPLEX;
+ mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
+ dev_info(eth->dev, "using fixed link parameters\n");
+ return;
+ }
+
+ if (eth->phy->phy_node[id] && eth->mii_bus->phy_map[id]) {
+ u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
+ PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
+
+ mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
+ mtk_connect_phy_node(eth, mac, eth->phy->phy_node[id]);
+ gsw->autopoll |= BIT(id);
+ mt7620_auto_poll(gsw);
+ return;
+ }
+}
+
+static void mt7620_mtk_reset(struct mtk_eth *eth)
+{
+ mtk_reset(eth, MT7620_RESET_FE | MT7620_RESET_ESW);
+}
+
+static int mt7620_fwd_config(struct mtk_eth *eth)
+{
+ /* Make sure that the CPU port is used as the mac destination port */
+ mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) & ~GDMA_FRC_P_MASK,
+ MT7620_GDMA1_FWD_CFG);
+
+ /* Enable TX Checksum Offloading */
+ mtk_w32(eth,
+ mtk_r32(eth, MT7620_GDMA1_FWD_CFG) |
+ (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN),
+ MT7620_GDMA1_FWD_CFG);
+
+ /* Enable RX Checksum Offloading */
+ mtk_w32(eth,
+ mtk_r32(eth, MT7620_CDMA_CSG_CFG) |
+ (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN),
+ MT7620_CDMA_CSG_CFG);
+
+ return 0;
+}
+
+static void mt7620_init_data(struct mtk_soc_data *data,
+ struct net_device *netdev)
+{
+ if (mt7620_get_eco() >= 5)
+ netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
+ NETIF_F_IPV6_CSUM;
+}
+
+static struct mtk_soc_data mt7620_data = {
+ .hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
+ NETIF_F_HW_VLAN_CTAG_TX,
+ .dma_type = MTK_PDMA,
+ .dma_ring_size = 256,
+ .napi_weight = 64,
+ .piac_offset = 0x7000,
+ .padding_64b = 1,
+ .rx_2b_offset = 1,
+ .rx_sg_dma = 1,
+ .has_switch = 1,
+ .mac_count = 1,
+ .init_data = mt7620_init_data,
+ .reset_fe = mt7620_mtk_reset,
+ .set_mac = mt7620_set_mac,
+ .fwd_config = mt7620_fwd_config,
+ .switch_init = mtk_gsw_init,
+ .port_init = mt7620_port_init,
+ .reg_table = mt7620_reg_table,
+ .pdma_glo_cfg = MTK_PDMA_SIZE_16DWORDS,
+ .rx_int = RT5350_RX_DONE_INT,
+ .tx_int = RT5350_TX_DONE_INT,
+ .status_int = MT7620_MTK_GDM1_AF,
+ .checksum_bit = MT7620_L4_VALID,
+ .has_carrier = mt7620_has_carrier,
+ .mdio_read = mt7620_mdio_read,
+ .mdio_write = mt7620_mdio_write,
+ .mdio_adjust_link = mt7620_mdio_link_adjust,
+};
+
+const struct of_device_id of_mtk_match[] = {
+ { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_mtk_match);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH V2 09/12] net-next: mediatek: add support for mt7621
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (7 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 08/12] net-next: mediatek: add support for mt7620 John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 14:21 ` [PATCH V2 10/12] net-next: mediatek: add support for mt7623 John Crispin
` (2 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
Add support for SoCs from the mt7621 family. These all have 2 GMAC ports,
both of which are attached to the same internal 1000MBit switch. Currently
we only support GMAC1 as the sole CPU port. MT7621 is very similar to
MT7620 with only a few registers having different offsets. MT7621 is the
first SoC to have the new QDMA engine builtin. The older PDMA engine is
also present. unfortunatley, to get the best performance we need to run RX
on PDMA and TX on QDMA. This SoC is also the first to have TX vlan
offloading and TSO6 support.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
drivers/net/ethernet/mediatek/soc_mt7621.c | 148 ++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/soc_mt7621.c
diff --git a/drivers/net/ethernet/mediatek/soc_mt7621.c b/drivers/net/ethernet/mediatek/soc_mt7621.c
new file mode 100644
index 0000000..dcc3289
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/soc_mt7621.c
@@ -0,0 +1,148 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/if_vlan.h>
+#include <linux/of_net.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+#include "mdio.h"
+
+#define MT7620_CDMA_CSG_CFG 0x400
+#define MT7621_CDMP_IG_CTRL (MT7620_CDMA_CSG_CFG + 0x00)
+#define MT7621_CDMP_EG_CTRL (MT7620_CDMA_CSG_CFG + 0x04)
+#define MT7621_RESET_FE BIT(6)
+#define MT7621_L4_VALID BIT(24)
+
+#define MT7621_TX_DMA_UDF BIT(19)
+
+#define CDMA_ICS_EN BIT(2)
+#define CDMA_UCS_EN BIT(1)
+#define CDMA_TCS_EN BIT(0)
+
+#define GDMA_ICS_EN BIT(22)
+#define GDMA_TCS_EN BIT(21)
+#define GDMA_UCS_EN BIT(20)
+
+/* frame engine counters */
+#define MT7621_REG_MIB_OFFSET 0x2000
+#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
+#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
+#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
+
+#define GSW_REG_GDMA1_MAC_ADRL 0x508
+#define GSW_REG_GDMA1_MAC_ADRH 0x50C
+
+#define MT7621_MTK_RST_GL 0x04
+#define MT7620_MTK_INT_STATUS2 0x08
+
+/* MTK_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
+ * but after test it should be BIT(13).
+ */
+#define MT7621_MTK_GDM1_AF BIT(28)
+#define MT7621_MTK_GDM2_AF BIT(29)
+
+static const u16 mt7621_reg_table[MTK_REG_COUNT] = {
+ [MTK_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
+ [MTK_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
+ [MTK_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
+ [MTK_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+ [MTK_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+ [MTK_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+ [MTK_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+ [MTK_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+ [MTK_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+ [MTK_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+ [MTK_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+ [MTK_REG_MTK_INT_ENABLE] = RT5350_MTK_INT_ENABLE,
+ [MTK_REG_MTK_INT_STATUS] = RT5350_MTK_INT_STATUS,
+ [MTK_REG_MTK_DMA_VID_BASE] = 0,
+ [MTK_REG_MTK_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
+ [MTK_REG_MTK_RST_GL] = MT7621_MTK_RST_GL,
+ [MTK_REG_MTK_INT_STATUS2] = MT7620_MTK_INT_STATUS2,
+};
+
+static void mt7621_mtk_reset(struct mtk_eth *eth)
+{
+ mtk_reset(eth, MT7621_RESET_FE);
+}
+
+static int mt7621_fwd_config(struct mtk_eth *eth)
+{
+ /* Setup GMAC1 only, there is no support for GMAC2 yet */
+ mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) & ~0xffff,
+ MT7620_GDMA1_FWD_CFG);
+
+ /* Enable RX checksum */
+ mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
+ GDMA_TCS_EN | GDMA_UCS_EN),
+ MT7620_GDMA1_FWD_CFG);
+
+ /* Enable RX VLan Offloading */
+ mtk_w32(eth, 1, MT7621_CDMP_EG_CTRL);
+
+ return 0;
+}
+
+static void mt7621_set_mac(struct mtk_mac *mac, unsigned char *hwaddr)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mac->hw->page_lock, flags);
+ mtk_w32(mac->hw, (hwaddr[0] << 8) | hwaddr[1], GSW_REG_GDMA1_MAC_ADRH);
+ mtk_w32(mac->hw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
+ (hwaddr[4] << 8) | hwaddr[5],
+ GSW_REG_GDMA1_MAC_ADRL);
+ spin_unlock_irqrestore(&mac->hw->page_lock, flags);
+}
+
+static struct mtk_soc_data mt7621_data = {
+ .hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
+ NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
+ NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
+ NETIF_F_IPV6_CSUM,
+ .dma_type = MTK_PDMA_RX_QDMA_TX,
+ .dma_ring_size = 256,
+ .napi_weight = 64,
+ .new_stats = 1,
+ .padding_64b = 1,
+ .rx_2b_offset = 1,
+ .rx_sg_dma = 1,
+ .has_switch = 1,
+ .reset_fe = mt7621_mtk_reset,
+ .set_mac = mt7621_set_mac,
+ .fwd_config = mt7621_fwd_config,
+ .switch_init = mtk_gsw_init,
+ .reg_table = mt7621_reg_table,
+ .pdma_glo_cfg = MTK_PDMA_SIZE_16DWORDS,
+ .rx_int = RT5350_RX_DONE_INT,
+ .tx_int = RT5350_TX_DONE_INT,
+ .status_int = MT7621_MTK_GDM1_AF | MT7621_MTK_GDM2_AF,
+ .checksum_bit = MT7621_L4_VALID,
+ .has_carrier = mt7620_has_carrier,
+ .mdio_read = mt7620_mdio_read,
+ .mdio_write = mt7620_mdio_write,
+ .mdio_adjust_link = mt7620_mdio_link_adjust,
+};
+
+const struct of_device_id of_mtk_match[] = {
+ { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_mtk_match);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH V2 10/12] net-next: mediatek: add support for mt7623
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (8 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 09/12] net-next: mediatek: add support for mt7621 John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-26 14:21 ` [PATCH V2 11/12] net-next: mediatek: add Kconfig and Makefile John Crispin
2016-02-26 14:21 ` [PATCH V2 12/12] net-next: mediatek: add an entry to MAINTAINERS John Crispin
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
Add support for SoCs from the mt7623 family. With this generation of SoCs
we have seen a change from MIPS to ARM cores. Due to the fact that ARM SoC
tend to be a bit more complex than MIPS, we need support for power domains.
The code should also run on MT2701, however this has not been tested yet on
device. To my understanding only changes to the devicetree are required as
irqs and reset gpios have changed. The DMA issues have also been solved on
this silicon allowing us to run on pure QDMA without having to bringup the
PDMA engine. However, in order for QDMA to work, we need to bringup the 3rd
DMA engine called FQ_DMA. This just needs to be setup and is more scratch
memory used internally by the SoC. The reason is that this SoC has many new
advanced features such as internal SFQ QoS and HW_LRO. for these to work,
the SoC needs extra DMA memory to be able to reorganize the packets
internally. I have not had time yet to look at these new features in
detail.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
drivers/net/ethernet/mediatek/soc_mt7623.c | 169 ++++++++++++++++++++++++++++
1 file changed, 169 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/soc_mt7623.c
diff --git a/drivers/net/ethernet/mediatek/soc_mt7623.c b/drivers/net/ethernet/mediatek/soc_mt7623.c
new file mode 100644
index 0000000..cff9868
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/soc_mt7623.c
@@ -0,0 +1,169 @@
+/* This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/if_vlan.h>
+#include <linux/of_net.h>
+
+#include "mtk_eth_soc.h"
+#include "gsw_mt7620.h"
+#include "mdio.h"
+
+#define MT7620_CDMA_CSG_CFG 0x400
+#define MT7621_CDMP_IG_CTRL (MT7620_CDMA_CSG_CFG + 0x00)
+#define MT7621_CDMP_EG_CTRL (MT7620_CDMA_CSG_CFG + 0x04)
+#define MT7621_RESET_FE BIT(6)
+#define MT7621_L4_VALID BIT(24)
+
+#define MT7621_TX_DMA_UDF BIT(19)
+
+#define CDMA_ICS_EN BIT(2)
+#define CDMA_UCS_EN BIT(1)
+#define CDMA_TCS_EN BIT(0)
+
+#define GDMA_ICS_EN BIT(22)
+#define GDMA_TCS_EN BIT(21)
+#define GDMA_UCS_EN BIT(20)
+
+/* frame engine counters */
+#define MT7621_REG_MIB_OFFSET 0x2000
+#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
+#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
+#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
+
+#define GSW_REG_GDMA1_MAC_ADRL 0x508
+#define GSW_REG_GDMA1_MAC_ADRH 0x50C
+
+#define GSW_REG_GDMA2_MAC_ADRL 0x1508
+#define GSW_REG_GDMA2_MAC_ADRH 0x150C
+
+#define MT7621_MTK_RST_GL 0x04
+#define MT7620_MTK_INT_STATUS2 0x08
+
+#define MT7623_RX_BT_32DWORDS (3 << 11)
+
+#define MT7621_MTK_GDM1_AF BIT(28)
+#define MT7621_MTK_GDM2_AF BIT(29)
+
+static const u16 mt7623_reg_table[MTK_REG_COUNT] = {
+ [MTK_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
+ [MTK_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
+ [MTK_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
+ [MTK_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
+ [MTK_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
+ [MTK_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
+ [MTK_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
+ [MTK_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
+ [MTK_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
+ [MTK_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
+ [MTK_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
+ [MTK_REG_MTK_INT_ENABLE] = RT5350_MTK_INT_ENABLE,
+ [MTK_REG_MTK_INT_STATUS] = RT5350_MTK_INT_STATUS,
+ [MTK_REG_MTK_DMA_VID_BASE] = 0,
+ [MTK_REG_MTK_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
+ [MTK_REG_MTK_RST_GL] = MT7621_MTK_RST_GL,
+ [MTK_REG_MTK_INT_STATUS2] = MT7620_MTK_INT_STATUS2,
+};
+
+static void mt7623_mtk_reset(struct mtk_eth *eth)
+{
+ mtk_reset(eth, MT7621_RESET_FE);
+}
+
+static int mt7623_fwd_config(struct mtk_eth *eth)
+{
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ u32 val = mtk_r32(eth, MT7621_GDMA_FWD_CFG(i));
+
+ /* setup the forward port */
+ val &= ~0xffff;
+ if (eth->soc->dma_type == MTK_QDMA)
+ val |= 0x5555;
+
+ /* Enable RX checksum */
+ val |= GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN;
+
+ /* setup the mac dma */
+ mtk_w32(eth, val, MT7621_GDMA_FWD_CFG(i));
+ }
+
+ /* Enable RX VLan Offloading */
+ mtk_w32(eth, 1, MT7621_CDMP_EG_CTRL);
+
+ /* FE int grouping */
+ mtk_w32(eth, 0, 0x20);
+
+ return 0;
+}
+
+static void mt7623_set_mac(struct mtk_mac *mac, unsigned char *macaddr)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mac->hw->page_lock, flags);
+ if (mac->id == 0) {
+ mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
+ GSW_REG_GDMA1_MAC_ADRH);
+ mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
+ (macaddr[4] << 8) | macaddr[5],
+ GSW_REG_GDMA1_MAC_ADRL);
+ } else {
+ mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
+ GSW_REG_GDMA2_MAC_ADRH);
+ mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
+ (macaddr[4] << 8) | macaddr[5],
+ GSW_REG_GDMA2_MAC_ADRL);
+ }
+ spin_unlock_irqrestore(&mac->hw->page_lock, flags);
+}
+
+static struct mtk_soc_data mt7623_data = {
+ .hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
+ NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
+ NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
+ NETIF_F_IPV6_CSUM,
+ .dma_type = MTK_QDMA,
+ .dma_ring_size = 256,
+ .napi_weight = 64,
+ .new_stats = 1,
+ .padding_64b = 1,
+ .rx_2b_offset = 1,
+ .rx_sg_dma = 1,
+ .has_switch = 1,
+ .mac_count = 2,
+ .reset_fe = mt7623_mtk_reset,
+ .set_mac = mt7623_set_mac,
+ .fwd_config = mt7623_fwd_config,
+ .switch_init = mtk_gsw_init,
+ .reg_table = mt7623_reg_table,
+ .pdma_glo_cfg = MTK_PDMA_SIZE_16DWORDS | MT7623_RX_BT_32DWORDS,
+ .rx_int = RT5350_RX_DONE_INT,
+ .tx_int = RT5350_TX_DONE_INT,
+ .status_int = (MT7621_MTK_GDM1_AF | MT7621_MTK_GDM2_AF),
+ .checksum_bit = MT7621_L4_VALID,
+ .has_carrier = mt7620_has_carrier,
+ .mdio_read = mt7620_mdio_read,
+ .mdio_write = mt7620_mdio_write,
+ .mdio_adjust_link = mt7620_mdio_link_adjust,
+};
+
+const struct of_device_id of_mtk_match[] = {
+ { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_mtk_match);
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH V2 11/12] net-next: mediatek: add Kconfig and Makefile
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (9 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 10/12] net-next: mediatek: add support for mt7623 John Crispin
@ 2016-02-26 14:21 ` John Crispin
2016-02-27 3:29 ` kbuild test robot
2016-02-26 14:21 ` [PATCH V2 12/12] net-next: mediatek: add an entry to MAINTAINERS John Crispin
11 siblings, 1 reply; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
This patch adds the Makefile and Kconfig required to make the driver build.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Michael Lee <igvtee@gmail.com>
---
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/mediatek/Kconfig | 70 ++++++++++++++++++++++++++++++++
drivers/net/ethernet/mediatek/Makefile | 23 +++++++++++
4 files changed, 95 insertions(+)
create mode 100644 drivers/net/ethernet/mediatek/Kconfig
create mode 100644 drivers/net/ethernet/mediatek/Makefile
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 31c5e47..cd28b95 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -106,6 +106,7 @@ config LANTIQ_ETOP
Support for the MII0 inside the Lantiq SoC
source "drivers/net/ethernet/marvell/Kconfig"
+source "drivers/net/ethernet/mediatek/Kconfig"
source "drivers/net/ethernet/mellanox/Kconfig"
source "drivers/net/ethernet/micrel/Kconfig"
source "drivers/net/ethernet/microchip/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 071f84e..c62191f 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_JME) += jme.o
obj-$(CONFIG_KORINA) += korina.o
obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
+obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/
obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/
diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig
new file mode 100644
index 0000000..a9b9434
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/Kconfig
@@ -0,0 +1,70 @@
+config NET_VENDOR_MEDIATEK
+ tristate "Mediatek/Ralink ethernet driver"
+ depends on RALINK || ARCH_MEDIATEK
+ help
+ This driver supports the ethernet mac inside the Mediatek and Ralink WiSoCs
+
+config NET_MEDIATEK_SOC
+ def_tristate NET_VENDOR_MEDIATEK
+
+if NET_MEDIATEK_SOC
+choice
+ prompt "MAC type"
+
+config NET_MEDIATEK_RT2880
+ bool "RT2882"
+ depends on MIPS && SOC_RT288X
+
+config NET_MEDIATEK_RT3050
+ bool "RT3050/MT7628"
+ depends on MIPS && (SOC_RT305X || SOC_MT7620)
+
+config NET_MEDIATEK_RT3883
+ bool "RT3883"
+ depends on MIPS && SOC_RT3883
+
+config NET_MEDIATEK_MT7620
+ bool "MT7620"
+ depends on MIPS && SOC_MT7620
+
+config NET_MEDIATEK_MT7621
+ bool "MT7621"
+ depends on MIPS && SOC_MT7621
+
+config NET_MEDIATEK_MT7623
+ bool "MT7623"
+ depends on ARM && MACH_MT7623
+
+endchoice
+
+config NET_MEDIATEK_MDIO
+ def_bool NET_MEDIATEK_SOC
+ depends on (NET_MEDIATEK_RT2880 || NET_MEDIATEK_RT3883 || NET_MEDIATEK_MT7620 || NET_MEDIATEK_MT7621 || NET_MEDIATEK_MT7623)
+ select PHYLIB
+
+config NET_MEDIATEK_MDIO_RT2880
+ def_bool NET_MEDIATEK_SOC
+ depends on (NET_MEDIATEK_RT2880 || NET_MEDIATEK_RT3883)
+ select NET_MEDIATEK_MDIO
+
+config NET_MEDIATEK_MDIO_MT7620
+ def_bool NET_MEDIATEK_SOC
+ depends on (NET_MEDIATEK_MT7620 || NET_MEDIATEK_MT7621 || NET_MEDIATEK_MT7623)
+ select NET_MEDIATEK_MDIO
+
+config NET_MEDIATEK_ESW_RT3050
+ def_tristate NET_MEDIATEK_SOC
+ depends on NET_MEDIATEK_RT3050
+
+config NET_MEDIATEK_GSW_MT7620
+ def_tristate NET_MEDIATEK_SOC
+ depends on NET_MEDIATEK_MT7620
+
+config NET_MEDIATEK_GSW_MT7621
+ def_tristate NET_MEDIATEK_SOC
+ depends on NET_MEDIATEK_MT7621
+
+config NET_MEDIATEK_GSW_MT7623
+ def_tristate NET_MEDIATEK_SOC
+ depends on NET_MEDIATEK_MT7623
+endif
diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile
new file mode 100644
index 0000000..d9a161d
--- /dev/null
+++ b/drivers/net/ethernet/mediatek/Makefile
@@ -0,0 +1,23 @@
+#
+# Makefile for the Ralink SoCs built-in ethernet macs
+#
+
+mtk-eth-soc-y += mtk_eth_soc.o ethtool.o
+
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO) += mdio.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_RT2880) += mdio_rt2880.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_MT7620) += mdio_mt7620.o
+
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT2880) += soc_rt2880.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT3050) += soc_rt3050.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT3883) += soc_rt3883.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7620) += soc_mt7620.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7621) += soc_mt7621.o
+mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7623) += soc_mt7623.o
+
+obj-$(CONFIG_NET_MEDIATEK_ESW_RT3050) += esw_rt3050.o
+obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620) += gsw_mt7620.o
+obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621) += gsw_mt7621.o
+obj-$(CONFIG_NET_MEDIATEK_GSW_MT7623) += gsw_mt7623.o
+
+obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk-eth-soc.o
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH V2 11/12] net-next: mediatek: add Kconfig and Makefile
2016-02-26 14:21 ` [PATCH V2 11/12] net-next: mediatek: add Kconfig and Makefile John Crispin
@ 2016-02-27 3:29 ` kbuild test robot
0 siblings, 0 replies; 26+ messages in thread
From: kbuild test robot @ 2016-02-27 3:29 UTC (permalink / raw)
To: John Crispin
Cc: kbuild-all, David S. Miller, netdev, linux-arm-kernel,
linux-mediatek, linux-kernel, Matthias Brugger,
Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau, Michael Lee
[-- Attachment #1: Type: text/plain, Size: 3670 bytes --]
Hi John,
[auto build test ERROR on net/master]
[also build test ERROR on v4.5-rc5 next-20160226]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/John-Crispin/net-next-mediatek-add-ethernet-driver/20160226-223245
config: arm64-allmodconfig (attached as .config)
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All error/warnings (new ones prefixed by >>):
drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function 'mtk_init_fq_dma':
>> drivers/net/ethernet/mediatek/mtk_eth_soc.c:771:22: warning: passing argument 3 of 'dma_alloc_coherent' from incompatible pointer type
eth->scratch_ring = dma_alloc_coherent(eth->dev,
^
In file included from drivers/net/ethernet/mediatek/mtk_eth_soc.c:18:0:
include/linux/dma-mapping.h:396:21: note: expected 'dma_addr_t *' but argument is of type 'unsigned int *'
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
^
drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function 'mtk_probe':
>> drivers/net/ethernet/mediatek/mtk_eth_soc.c:2059:2: warning: ignoring return value of 'device_reset', declared with attribute warn_unused_result [-Wunused-result]
device_reset(&pdev->dev);
^
--
drivers/net/ethernet/mediatek/ethtool.c: In function 'mtk_set_settings':
>> drivers/net/ethernet/mediatek/ethtool.c:49:38: error: 'struct phy_device' has no member named 'addr'
if (cmd->phy_address != mac->phy_dev->addr) {
^
>> drivers/net/ethernet/mediatek/ethtool.c:54:23: error: 'struct mii_bus' has no member named 'phy_map'
mac->hw->mii_bus->phy_map[cmd->phy_address]) {
^
drivers/net/ethernet/mediatek/ethtool.c:56:21: error: 'struct mii_bus' has no member named 'phy_map'
mac->hw->mii_bus->phy_map[cmd->phy_address];
^
vim +49 drivers/net/ethernet/mediatek/ethtool.c
79b0e682 John Crispin 2016-02-26 43 {
79b0e682 John Crispin 2016-02-26 44 struct mtk_mac *mac = netdev_priv(dev);
79b0e682 John Crispin 2016-02-26 45
79b0e682 John Crispin 2016-02-26 46 if (!mac->phy_dev)
79b0e682 John Crispin 2016-02-26 47 return -ENODEV;
79b0e682 John Crispin 2016-02-26 48
79b0e682 John Crispin 2016-02-26 @49 if (cmd->phy_address != mac->phy_dev->addr) {
79b0e682 John Crispin 2016-02-26 50 if (mac->hw->phy->phy_node[cmd->phy_address]) {
79b0e682 John Crispin 2016-02-26 51 mac->phy_dev = mac->hw->phy->phy[cmd->phy_address];
79b0e682 John Crispin 2016-02-26 52 mac->phy_flags = MTK_PHY_FLAG_PORT;
79b0e682 John Crispin 2016-02-26 53 } else if (mac->hw->mii_bus &&
79b0e682 John Crispin 2016-02-26 @54 mac->hw->mii_bus->phy_map[cmd->phy_address]) {
79b0e682 John Crispin 2016-02-26 55 mac->phy_dev =
79b0e682 John Crispin 2016-02-26 56 mac->hw->mii_bus->phy_map[cmd->phy_address];
79b0e682 John Crispin 2016-02-26 57 mac->phy_flags = MTK_PHY_FLAG_ATTACH;
:::::: The code at line 49 was first introduced by commit
:::::: 79b0e682b3b2ed2a983b0263c6b8b3af61fdbf8e net-next: mediatek: add the drivers core files
:::::: TO: John Crispin <blogic@openwrt.org>
:::::: CC: 0day robot <fengguang.wu@intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 47927 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH V2 12/12] net-next: mediatek: add an entry to MAINTAINERS
2016-02-26 14:21 [PATCH V2 00/12] net-next: mediatek: add ethernet driver John Crispin
` (10 preceding siblings ...)
2016-02-26 14:21 ` [PATCH V2 11/12] net-next: mediatek: add Kconfig and Makefile John Crispin
@ 2016-02-26 14:21 ` John Crispin
11 siblings, 0 replies; 26+ messages in thread
From: John Crispin @ 2016-02-26 14:21 UTC (permalink / raw)
To: David S. Miller
Cc: netdev, linux-arm-kernel, linux-mediatek, linux-kernel,
Matthias Brugger, Steven Liu (劉人豪),
Carlos Huang (黃士彰),
Fred Chang (張嘉宏),
John Crispin, Felix Fietkau
Add myself and Felix as the Maintainers for the driver.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 156e1d3..4a51c66 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6908,6 +6908,13 @@ F: include/uapi/linux/meye.h
F: include/uapi/linux/ivtv*
F: include/uapi/linux/uvcvideo.h
+MEDIATEK ETHERNET DRIVER
+M: John Crispin <blogic@openwrt.org>
+M: Felix Fietkau <nbd@openwrt.org>
+L: netdev@vger.kernel.org
+S: Maintained
+F: drivers/net/ethernet/mediatek/
+
MEDIATEK MT7601U WIRELESS LAN DRIVER
M: Jakub Kicinski <kubakici@wp.pl>
L: linux-wireless@vger.kernel.org
--
1.7.10.4
^ permalink raw reply related [flat|nested] 26+ messages in thread