* [PATCH v1 1/1] x86/platform/intel-mid: Make vertical indentation consistent
@ 2016-06-14 14:33 Andy Shevchenko
2016-06-14 15:33 ` Ingo Molnar
0 siblings, 1 reply; 3+ messages in thread
From: Andy Shevchenko @ 2016-06-14 14:33 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, H . Peter Anvin, x86, linux-kernel
Cc: Andy Shevchenko
The vertical indentation is kinda chaotic in intel-mid.h. Let's be consisten
with it.
Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/include/asm/intel-mid.h | 48 ++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h
index 2bda94c..d1a57fa 100644
--- a/arch/x86/include/asm/intel-mid.h
+++ b/arch/x86/include/asm/intel-mid.h
@@ -42,11 +42,11 @@ struct devs_id {
void *(*get_platform_data)(void *info);
/* Custom handler for devices */
void (*device_handler)(struct sfi_device_table_entry *pentry,
- struct devs_id *dev);
+ struct devs_id *dev);
};
-#define sfi_device(i) \
- static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
+#define sfi_device(i) \
+ static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
__attribute__((__section__(".x86_intel_mid_dev.init"))) = &i
/*
@@ -78,20 +78,20 @@ struct intel_mid_ops {
};
/* Helper API's for INTEL_MID_OPS_INIT */
-#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \
- [cpuid] = get_##cpuname##_ops
+#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \
+ [cpuid] = get_##cpuname##_ops
/* Maximum number of CPU ops */
-#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
+#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
/*
* For every new cpu addition, a weak get_<cpuname>_ops() function needs be
* declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h.
*/
-#define INTEL_MID_OPS_INIT {\
- DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
- DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
- DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
+#define INTEL_MID_OPS_INIT { \
+ DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
+ DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
+ DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
};
#ifdef CONFIG_X86_INTEL_MID
@@ -108,8 +108,8 @@ static inline bool intel_mid_has_msic(void)
#else /* !CONFIG_X86_INTEL_MID */
-#define intel_mid_identify_cpu() (0)
-#define intel_mid_has_msic() (0)
+#define intel_mid_identify_cpu() (0)
+#define intel_mid_has_msic() (0)
#endif /* !CONFIG_X86_INTEL_MID */
@@ -125,15 +125,15 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
* Penwell uses spread spectrum clock, so the freq number is not exactly
* the same as reported by MSR based on SDM.
*/
-#define FSB_FREQ_83SKU 83200
-#define FSB_FREQ_100SKU 99840
-#define FSB_FREQ_133SKU 133000
+#define FSB_FREQ_83SKU 83200
+#define FSB_FREQ_100SKU 99840
+#define FSB_FREQ_133SKU 133000
-#define FSB_FREQ_167SKU 167000
-#define FSB_FREQ_200SKU 200000
-#define FSB_FREQ_267SKU 267000
-#define FSB_FREQ_333SKU 333000
-#define FSB_FREQ_400SKU 400000
+#define FSB_FREQ_167SKU 167000
+#define FSB_FREQ_200SKU 200000
+#define FSB_FREQ_267SKU 267000
+#define FSB_FREQ_333SKU 333000
+#define FSB_FREQ_400SKU 400000
/* Bus Select SoC Fuse value */
#define BSEL_SOC_FUSE_MASK 0x7
@@ -141,19 +141,19 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
-#define SFI_MTMR_MAX_NUM 8
-#define SFI_MRTC_MAX 8
+#define SFI_MTMR_MAX_NUM 8
+#define SFI_MRTC_MAX 8
extern void intel_scu_devices_create(void);
extern void intel_scu_devices_destroy(void);
/* VRTC timer */
#define MRST_VRTC_MAP_SZ (1024)
-/*#define MRST_VRTC_PGOFFSET (0xc00) */
+/* #define MRST_VRTC_PGOFFSET (0xc00) */
extern void intel_mid_rtc_init(void);
/* the offset for the mapping of global gpio pin to irq */
-#define INTEL_MID_IRQ_OFFSET 0x100
+#define INTEL_MID_IRQ_OFFSET 0x100
#endif /* _ASM_X86_INTEL_MID_H */
--
2.8.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v1 1/1] x86/platform/intel-mid: Make vertical indentation consistent
2016-06-14 14:33 [PATCH v1 1/1] x86/platform/intel-mid: Make vertical indentation consistent Andy Shevchenko
@ 2016-06-14 15:33 ` Ingo Molnar
2016-06-14 15:47 ` Andy Shevchenko
0 siblings, 1 reply; 3+ messages in thread
From: Ingo Molnar @ 2016-06-14 15:33 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Thomas Gleixner, Ingo Molnar, H . Peter Anvin, x86, linux-kernel
How about this as well, on top of yours?
=================>
Make vertical alignment really consistent across this header, plus fix various
uglies like unnecessary parentheses and C comments from definition values.
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/include/asm/intel-mid.h | 45 ++++++++++++++++++++-------------------
1 file changed, 24 insertions(+), 21 deletions(-)
Index: tip/arch/x86/include/asm/intel-mid.h
===================================================================
--- tip.orig/arch/x86/include/asm/intel-mid.h
+++ tip/arch/x86/include/asm/intel-mid.h
@@ -74,7 +74,7 @@ struct intel_mid_ops {
[cpuid] = get_##cpuname##_ops
/* Maximum number of CPU ops */
-#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
+#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
/*
* For every new cpu addition, a weak get_<cpuname>_ops() function needs be
@@ -100,8 +100,8 @@ static inline bool intel_mid_has_msic(vo
#else /* !CONFIG_X86_INTEL_MID */
-#define intel_mid_identify_cpu() (0)
-#define intel_mid_has_msic() (0)
+#define intel_mid_identify_cpu() 0
+#define intel_mid_has_msic() 0
#endif /* !CONFIG_X86_INTEL_MID */
@@ -117,35 +117,38 @@ extern enum intel_mid_timer_options inte
* Penwell uses spread spectrum clock, so the freq number is not exactly
* the same as reported by MSR based on SDM.
*/
-#define FSB_FREQ_83SKU 83200
-#define FSB_FREQ_100SKU 99840
-#define FSB_FREQ_133SKU 133000
-
-#define FSB_FREQ_167SKU 167000
-#define FSB_FREQ_200SKU 200000
-#define FSB_FREQ_267SKU 267000
-#define FSB_FREQ_333SKU 333000
-#define FSB_FREQ_400SKU 400000
+#define FSB_FREQ_83SKU 83200
+#define FSB_FREQ_100SKU 99840
+#define FSB_FREQ_133SKU 133000
+
+#define FSB_FREQ_167SKU 167000
+#define FSB_FREQ_200SKU 200000
+#define FSB_FREQ_267SKU 267000
+#define FSB_FREQ_333SKU 333000
+#define FSB_FREQ_400SKU 400000
/* Bus Select SoC Fuse value */
-#define BSEL_SOC_FUSE_MASK 0x7
-#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */
-#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
-#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
+#define BSEL_SOC_FUSE_MASK 0x7
+/* FSB 133MHz: */
+#define BSEL_SOC_FUSE_001 0x1
+/* FSB 100MHz: */
+#define BSEL_SOC_FUSE_101 0x5
+/* FSB 83MHz: */
+#define BSEL_SOC_FUSE_111 0x7
-#define SFI_MTMR_MAX_NUM 8
-#define SFI_MRTC_MAX 8
+#define SFI_MTMR_MAX_NUM 8
+#define SFI_MRTC_MAX 8
extern void intel_scu_devices_create(void);
extern void intel_scu_devices_destroy(void);
/* VRTC timer */
-#define MRST_VRTC_MAP_SZ (1024)
-/* #define MRST_VRTC_PGOFFSET (0xc00) */
+#define MRST_VRTC_MAP_SZ 1024
+/* #define MRST_VRTC_PGOFFSET 0xc00 */
extern void intel_mid_rtc_init(void);
/* the offset for the mapping of global gpio pin to irq */
-#define INTEL_MID_IRQ_OFFSET 0x100
+#define INTEL_MID_IRQ_OFFSET 0x100
#endif /* _ASM_X86_INTEL_MID_H */
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1 1/1] x86/platform/intel-mid: Make vertical indentation consistent
2016-06-14 15:33 ` Ingo Molnar
@ 2016-06-14 15:47 ` Andy Shevchenko
0 siblings, 0 replies; 3+ messages in thread
From: Andy Shevchenko @ 2016-06-14 15:47 UTC (permalink / raw)
To: Ingo Molnar
Cc: Thomas Gleixner, Ingo Molnar, H . Peter Anvin, x86, linux-kernel
On Tue, 2016-06-14 at 17:33 +0200, Ingo Molnar wrote:
> How about this as well, on top of yours?
Looks definitely good to me! Thanks!
>
> =================>
>
> Make vertical alignment really consistent across this header, plus fix
> various
> uglies like unnecessary parentheses and C comments from definition
> values.
>
> Cc: Linus Torvalds <torvalds@linux-foundation.org>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Ingo Molnar <mingo@kernel.org>
> ---
> arch/x86/include/asm/intel-mid.h | 45 ++++++++++++++++++++---------
> ----------
> 1 file changed, 24 insertions(+), 21 deletions(-)
>
> Index: tip/arch/x86/include/asm/intel-mid.h
> ===================================================================
> --- tip.orig/arch/x86/include/asm/intel-mid.h
> +++ tip/arch/x86/include/asm/intel-mid.h
> @@ -74,7 +74,7 @@ struct intel_mid_ops {
> [cpuid] = get_##cpuname##_ops
>
> /* Maximum number of CPU ops */
> -#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
> +#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void
> *))
>
> /*
> * For every new cpu addition, a weak get_<cpuname>_ops() function
> needs be
> @@ -100,8 +100,8 @@ static inline bool intel_mid_has_msic(vo
>
> #else /* !CONFIG_X86_INTEL_MID */
>
> -#define intel_mid_identify_cpu() (0)
> -#define intel_mid_has_msic() (0)
> +#define intel_mid_identify_cpu() 0
> +#define intel_mid_has_msic() 0
>
> #endif /* !CONFIG_X86_INTEL_MID */
>
> @@ -117,35 +117,38 @@ extern enum intel_mid_timer_options inte
> * Penwell uses spread spectrum clock, so the freq number is not
> exactly
> * the same as reported by MSR based on SDM.
> */
> -#define FSB_FREQ_83SKU 83200
> -#define FSB_FREQ_100SKU 99840
> -#define FSB_FREQ_133SKU 133000
> -
> -#define FSB_FREQ_167SKU 167000
> -#define FSB_FREQ_200SKU 200000
> -#define FSB_FREQ_267SKU 267000
> -#define FSB_FREQ_333SKU 333000
> -#define FSB_FREQ_400SKU 400000
> +#define FSB_FREQ_83SKU 83200
> +#define FSB_FREQ_100SKU 99840
> +#define FSB_FREQ_133SKU 133000
> +
> +#define FSB_FREQ_167SKU 167000
> +#define FSB_FREQ_200SKU 200000
> +#define FSB_FREQ_267SKU 267000
> +#define FSB_FREQ_333SKU 333000
> +#define FSB_FREQ_400SKU 400000
>
> /* Bus Select SoC Fuse value */
> -#define BSEL_SOC_FUSE_MASK 0x7
> -#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */
> -#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
> -#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
> +#define BSEL_SOC_FUSE_MASK 0x7
> +/* FSB 133MHz: */
> +#define BSEL_SOC_FUSE_001 0x1
> +/* FSB 100MHz: */
> +#define BSEL_SOC_FUSE_101 0x5
> +/* FSB 83MHz: */
> +#define BSEL_SOC_FUSE_111 0x7
>
> -#define SFI_MTMR_MAX_NUM 8
> -#define SFI_MRTC_MAX 8
> +#define SFI_MTMR_MAX_NUM 8
> +#define SFI_MRTC_MAX 8
>
> extern void intel_scu_devices_create(void);
> extern void intel_scu_devices_destroy(void);
>
> /* VRTC timer */
> -#define MRST_VRTC_MAP_SZ (1024)
> -/* #define MRST_VRTC_PGOFFSET (0xc00) */
> +#define MRST_VRTC_MAP_SZ 1024
> +/* #define MRST_VRTC_PGOFFSET 0xc00 */
>
> extern void intel_mid_rtc_init(void);
>
> /* the offset for the mapping of global gpio pin to irq */
> -#define INTEL_MID_IRQ_OFFSET 0x100
> +#define INTEL_MID_IRQ_OFFSET 0x100
>
> #endif /* _ASM_X86_INTEL_MID_H */
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
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2016-06-14 15:47 ` Andy Shevchenko
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