From: Douglas Anderson <dianders@chromium.org>
To: ulf.hansson@linaro.org, Heiko Stuebner <heiko@sntech.de>
Cc: kishon@ti.com, robh+dt@kernel.org, shawn.lin@rock-chips.com,
xzy.xu@rock-chips.com, briannorris@chromium.org,
adrian.hunter@intel.com, linux-rockchip@lists.infradead.org,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
groeck@chromium.org, Douglas Anderson <dianders@chromium.org>,
pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v3 10/15] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock
Date: Mon, 20 Jun 2016 10:56:49 -0700 [thread overview]
Message-ID: <1466445414-11974-11-git-send-email-dianders@chromium.org> (raw)
In-Reply-To: <1466445414-11974-1-git-send-email-dianders@chromium.org>
Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work
with arasan,sdhci-5.1) need to know the card clock frequency in order to
function properly. Physically in a SoC this clock is exported from the
SDHCI IP block to the PHY IP block and the PHY needs to know the speed.
Let's export the SDHCI card clock using a standard device tree mechanism
so that the PHY can get access to it and query the card clock frequency.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
Changes in v3:
- Add collected tags
Changes in v2:
- Adjust commit message wording (Rob)
- Add Rob Herring's Ack.
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 476604e6ce2a..3404afa9b938 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -30,6 +30,12 @@ Optional Properties:
- arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
used to access core corecfg registers. Offsets of registers in this
syscon are determined based on the main compatible string for the device.
+ - clock-output-names: If specified, this will be the name of the card clock
+ which will be exposed by this device. Required if #clock-cells is
+ specified.
+ - #clock-cells: If specified this should be the value <0>. With this property
+ in place we will export a clock representing the Card Clock. This clock
+ is expected to be consumed by our PHY. You must also specify
Example:
sdhci@e0100000 {
@@ -61,7 +67,9 @@ Example:
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
phys = <&emmc_phy>;
phy-names = "phy_arasan";
+ #clock-cells = <0>;
status = "disabled";
};
--
2.8.0.rc3.226.g39d4020
next prev parent reply other threads:[~2016-06-20 18:32 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-20 17:56 [PATCH v3 0/15] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 01/15] phy: rockchip-emmc: give DLL some extra time to be ready Douglas Anderson
2016-06-20 19:23 ` Guenter Roeck
2016-06-20 19:30 ` Doug Anderson
2016-06-20 19:36 ` Guenter Roeck
2016-06-20 19:38 ` Doug Anderson
2016-06-20 17:56 ` [PATCH v3 02/15] phy: rockchip-emmc: configure frequency range and drive impedance Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 03/15] phy: rockchip-emmc: configure default output tap delay Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 04/15] phy: rockchip-emmc: reindent the register definitions Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 05/15] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson
2016-06-20 19:29 ` Guenter Roeck
2016-06-20 19:36 ` Doug Anderson
2016-06-20 19:38 ` Guenter Roeck
2016-06-20 17:56 ` [PATCH v3 06/15] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Douglas Anderson
2016-06-22 12:34 ` Adrian Hunter
2016-06-20 17:56 ` [PATCH v3 07/15] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 08/15] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson
2016-06-22 12:34 ` Adrian Hunter
2016-06-20 17:56 ` [PATCH v3 09/15] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson
2016-06-22 16:30 ` Heiko Stübner
2016-06-20 17:56 ` Douglas Anderson [this message]
2016-06-20 17:56 ` [PATCH v3 11/15] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson
2016-06-22 12:35 ` Adrian Hunter
2016-06-20 17:56 ` [PATCH v3 12/15] Documentation: phy: Let the rockchip eMMC PHY get an exported " Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 13/15] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_on/off() Douglas Anderson
2016-06-20 17:56 ` [PATCH v3 14/15] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Douglas Anderson
2016-06-20 18:14 ` Heiko Stübner
2016-06-20 17:56 ` [PATCH v3 15/15] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson
2016-06-22 16:31 ` Heiko Stübner
2016-06-20 18:17 ` [PATCH v3 0/15] Changes to support 150 MHz eMMC on rk3399 Heiko Stübner
2016-06-22 15:23 ` Ulf Hansson
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