* [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs
@ 2016-07-06 8:05 Caesar Wang
2016-07-06 8:05 ` [PATCH v2 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on " Caesar Wang
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Caesar Wang @ 2016-07-06 8:05 UTC (permalink / raw)
To: Marc Zyngier, Heiko Stuebner
Cc: dianders, mark.rutland, linux-rockchip, cf, huangtao,
linux-arm-kernel, Caesar Wang, devicetree, David Wu,
Masahiro Yamada, Brian Norris, linux-kernel, Will Deacon,
Jianqun Xu, Rob Herring, Catalin Marinas, Xing Zheng
Hello Heiko, Marc & ARM guys
When Jay first submitted the rk3399.dtsi upstream
<https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there,
but then took it out because the upstream binding wasn't done yet.
It looks as if the upstream stuff has landed, since in linux/master I see:
287e9357abcc DT/arm,gic-v3: Documment PPI partition support
e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs
9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library
222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved
651e8b54abde irqdomain: Allow domain matching on irq_fwspec
This series patches add to support the rk3399 SoCs PMU.
I pick up the https://patchwork.kernel.org/patch/9209369/.
As do some tests with ChromeOs for my rk3399 board.
Tested with linus master 4.7-rc6 kernel on rk3399 board.
https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream
localhost / # perf list
List of pre-defined events (to be used in -e):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
cache-references [Hardware event]
cache-misses [Hardware event]
branch-instructions OR branches [Hardware event]
branch-misses [Hardware event]
bus-cycles [Hardware event]
...
perf stat --cpu 0/1/2/3..... to minitor
e.g. cpu0;
localhost / # perf stat --cpu 0
Performance counter stats for 'CPU(s) 0':
3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%]
20 context-switches # 0.006 K/sec [100.00%]
2 cpu-migrations # 0.001 K/sec [100.00%]
55 page-faults # 0.016 K/sec
7151843 cycles # 0.002 GHz [100.00%]
<not supported> stalled-cycles-frontend
<not supported> stalled-cycles-backend
4272536 instructions # 0.60 insns per cycle [100.00%]
568406 branches # 0.168 M/sec [100.00%]
65652 branch-misses # 11.55% of all branches
Also, 'perf top' to monitor the PMU interrupts from cpus
-Caesar
Changes in v2:
- AS Mark comments on https://patchwork.kernel.org/patch/9209369/
remove the interrupt-affinity property, we need depend on Marc' perf
code on https://patchwork.kernel.org/patch/9209369/.
Caesar Wang (2):
arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
arm64: dts: rockchip: support the pmu node for rk3399
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 118 ++++++++++++++++++-------------
1 file changed, 69 insertions(+), 49 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
2016-07-06 8:05 [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Caesar Wang
@ 2016-07-06 8:05 ` Caesar Wang
2016-07-06 8:05 ` [PATCH v2 2/2] arm64: dts: rockchip: support the pmu node for rk3399 Caesar Wang
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Caesar Wang @ 2016-07-06 8:05 UTC (permalink / raw)
To: Marc Zyngier, Heiko Stuebner
Cc: dianders, mark.rutland, linux-rockchip, cf, huangtao,
linux-arm-kernel, Caesar Wang, Will Deacon, Rob Herring,
Catalin Marinas, Brian Norris, Jianqun Xu, Masahiro Yamada,
Xing Zheng, David Wu, devicetree, linux-kernel
Add the interrupts cells value for 4, and the 4th cell is zero.
Due to the doc[0] said:" the system requires describing PPI affinity,
then the value must be at least 4"
The 4th cell is a phandle to a node describing a set of CPUs this
interrupt is affine to. The interrupt must be a PPI, and the node
pointed must be a subnode of the "ppi-partitions" subnode. For
interrupt types other than PPI or PPIs that are not partitionned,
this cell must be zero. See the "ppi-partitions" node description
below.
[0]:
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
CC: linux-arm-kernel@lists.infradead.org
---
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 98 ++++++++++++++++----------------
1 file changed, 49 insertions(+), 49 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index a6dd623..8f0a069 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -159,10 +159,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
xin24m: xin24m {
@@ -181,8 +181,8 @@
dmac_bus: dma-controller@ff6d0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff6d0000 0x0 0x4000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC0_PERILP>;
clock-names = "apb_pclk";
@@ -191,8 +191,8 @@
dmac_peri: dma-controller@ff6e0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff6e0000 0x0 0x4000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC1_PERILP>;
clock-names = "apb_pclk";
@@ -203,7 +203,7 @@
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe310000 0x0 0x4000>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
@@ -216,7 +216,7 @@
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe320000 0x0 0x4000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
@@ -228,7 +228,7 @@
sdhci: sdhci@fe330000 {
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
reg = <0x0 0xfe330000 0x0 0x10000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
@@ -244,7 +244,7 @@
usb_host0_ehci: usb@fe380000 {
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
clock-names = "hclk_host0", "hclk_host0_arb";
status = "disabled";
@@ -253,7 +253,7 @@
usb_host0_ohci: usb@fe3a0000 {
compatible = "generic-ohci";
reg = <0x0 0xfe3a0000 0x0 0x20000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
clock-names = "hclk_host0", "hclk_host0_arb";
status = "disabled";
@@ -262,7 +262,7 @@
usb_host1_ehci: usb@fe3c0000 {
compatible = "generic-ehci";
reg = <0x0 0xfe3c0000 0x0 0x20000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
clock-names = "hclk_host1", "hclk_host1_arb";
status = "disabled";
@@ -271,7 +271,7 @@
usb_host1_ohci: usb@fe3e0000 {
compatible = "generic-ohci";
reg = <0x0 0xfe3e0000 0x0 0x20000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
clock-names = "hclk_host1", "hclk_host1_arb";
status = "disabled";
@@ -279,7 +279,7 @@
gic: interrupt-controller@fee00000 {
compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
+ #interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -290,7 +290,7 @@
<0x0 0xfff00000 0 0x10000>, /* GICC */
<0x0 0xfff10000 0 0x10000>, /* GICH */
<0x0 0xfff20000 0 0x10000>; /* GICV */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
its: interrupt-controller@fee20000 {
compatible = "arm,gic-v3-its";
msi-controller;
@@ -305,7 +305,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
#address-cells = <1>;
@@ -320,7 +320,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
#address-cells = <1>;
@@ -335,7 +335,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
#address-cells = <1>;
@@ -350,7 +350,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_xfer>;
#address-cells = <1>;
@@ -365,7 +365,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_xfer>;
#address-cells = <1>;
@@ -380,7 +380,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_xfer>;
#address-cells = <1>;
@@ -393,7 +393,7 @@
reg = <0x0 0xff180000 0x0 0x100>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -406,7 +406,7 @@
reg = <0x0 0xff190000 0x0 0x100>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -419,7 +419,7 @@
reg = <0x0 0xff1a0000 0x0 0x100>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -432,7 +432,7 @@
reg = <0x0 0xff1b0000 0x0 0x100>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -445,7 +445,7 @@
reg = <0x0 0xff1c0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
#address-cells = <1>;
@@ -458,7 +458,7 @@
reg = <0x0 0xff1d0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
#address-cells = <1>;
@@ -471,7 +471,7 @@
reg = <0x0 0xff1e0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
#address-cells = <1>;
@@ -484,7 +484,7 @@
reg = <0x0 0xff1f0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
#address-cells = <1>;
@@ -497,7 +497,7 @@
reg = <0x0 0xff200000 0x0 0x1000>;
clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
#address-cells = <1>;
@@ -577,7 +577,7 @@
tsadc: tsadc@ff260000 {
compatible = "rockchip,rk3399-tsadc";
reg = <0x0 0xff260000 0x0 0x100>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <750000>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
@@ -611,7 +611,7 @@
reg = <0x0 0xff350000 0x0 0x1000>;
clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
#address-cells = <1>;
@@ -624,7 +624,7 @@
reg = <0x0 0xff370000 0x0 0x100>;
clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -639,7 +639,7 @@
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
@@ -654,7 +654,7 @@
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
#address-cells = <1>;
@@ -669,7 +669,7 @@
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
clock-names = "i2c", "pclk";
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_xfer>;
#address-cells = <1>;
@@ -778,13 +778,13 @@
compatible = "snps,dw-wdt";
reg = <0x0 0xff840000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
};
rktimer: rktimer@ff850000 {
compatible = "rockchip,rk3399-timer";
reg = <0x0 0xff850000 0x0 0x1000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
clock-names = "pclk", "timer";
};
@@ -792,7 +792,7 @@
spdif: spdif@ff870000 {
compatible = "rockchip,rk3399-spdif";
reg = <0x0 0xff870000 0x0 0x1000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 7>;
dma-names = "tx";
clock-names = "mclk", "hclk";
@@ -806,7 +806,7 @@
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff880000 0x0 0x1000>;
rockchip,grf = <&grf>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
@@ -819,7 +819,7 @@
i2s1: i2s@ff890000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 2>, <&dmac_bus 3>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
@@ -832,7 +832,7 @@
i2s2: i2s@ff8a0000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff8a0000 0x0 0x1000>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 4>, <&dmac_bus 5>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
@@ -852,7 +852,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff720000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@@ -865,7 +865,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff730000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO1_PMU>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@@ -878,7 +878,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@@ -891,7 +891,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff788000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@@ -904,7 +904,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO4>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] arm64: dts: rockchip: support the pmu node for rk3399
2016-07-06 8:05 [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Caesar Wang
2016-07-06 8:05 ` [PATCH v2 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on " Caesar Wang
@ 2016-07-06 8:05 ` Caesar Wang
2016-07-06 11:24 ` [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Mark Rutland
2016-09-03 0:13 ` Caesar Wang
3 siblings, 0 replies; 8+ messages in thread
From: Caesar Wang @ 2016-07-06 8:05 UTC (permalink / raw)
To: Marc Zyngier, Heiko Stuebner
Cc: dianders, mark.rutland, linux-rockchip, cf, huangtao,
linux-arm-kernel, Caesar Wang, Rob Herring, Catalin Marinas,
Will Deacon, Brian Norris, Jianqun Xu, David Wu, Xing Zheng,
devicetree, linux-kernel
This patch add to enable the ARM Performance Monitor Units for rk3399.
ARM cores often have a PMU for counting cpu and cache events like cache
misses and hits.
Also, as the Marc posted the patches [0] to support Partitioning per-cpu
interrupts. Let's add this patch to match it on rk3399 SoCs.
[0]:
https://lkml.org/lkml/2016/4/11/182
https://patchwork.kernel.org/patch/9209369/
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Marc Zyngier <marc.zyngier@arm.com>
CC: linux-arm-kernel@lists.infradead.org
---
Changes in v2:
- AS Mark comments on https://patchwork.kernel.org/patch/9209369/
remove the interrupt-affinity property, we need depend on Marc' perf
code on https://patchwork.kernel.org/patch/9209369/.
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 8f0a069..4bcd02b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -165,6 +165,16 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
+ };
+
+ pmu_a72 {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
+ };
+
xin24m: xin24m {
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -296,6 +306,16 @@
msi-controller;
reg = <0x0 0xfee20000 0x0 0x20000>;
};
+
+ ppi-partitions {
+ part0: interrupt-partition-0 {
+ affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
+ };
+
+ part1: interrupt-partition-1 {
+ affinity = <&cpu_b0 &cpu_b1>;
+ };
+ };
};
i2c1: i2c@ff110000 {
--
1.9.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs
2016-07-06 8:05 [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Caesar Wang
2016-07-06 8:05 ` [PATCH v2 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on " Caesar Wang
2016-07-06 8:05 ` [PATCH v2 2/2] arm64: dts: rockchip: support the pmu node for rk3399 Caesar Wang
@ 2016-07-06 11:24 ` Mark Rutland
2016-07-14 1:14 ` Caesar Wang
2016-09-03 0:13 ` Caesar Wang
3 siblings, 1 reply; 8+ messages in thread
From: Mark Rutland @ 2016-07-06 11:24 UTC (permalink / raw)
To: Caesar Wang, Will Deacon, Marc Zyngier
Cc: Heiko Stuebner, dianders, linux-rockchip, cf, huangtao,
linux-arm-kernel, devicetree, David Wu, Masahiro Yamada,
Brian Norris, linux-kernel, Jianqun Xu, Rob Herring,
Catalin Marinas, Xing Zheng
On Wed, Jul 06, 2016 at 04:05:55PM +0800, Caesar Wang wrote:
> Hello Heiko, Marc & ARM guys
Hi,
These patches themselves look fine, so FWIW:
Acked-by: Mark Rutland <mark.rutland@arm.com>
The prerequisite patch from Marc [1] also largely looks fine, but there
are some minor details to sort out [2], so at this point in time I'm
guesssing this is all v4.9 material.
Thanks,
Mark.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/440647.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/441495.html
> When Jay first submitted the rk3399.dtsi upstream
> <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there,
> but then took it out because the upstream binding wasn't done yet.
> It looks as if the upstream stuff has landed, since in linux/master I see:
> 287e9357abcc DT/arm,gic-v3: Documment PPI partition support
> e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs
> 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library
> 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved
> 651e8b54abde irqdomain: Allow domain matching on irq_fwspec
>
> This series patches add to support the rk3399 SoCs PMU.
> I pick up the https://patchwork.kernel.org/patch/9209369/.
>
> As do some tests with ChromeOs for my rk3399 board.
> Tested with linus master 4.7-rc6 kernel on rk3399 board.
> https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream
>
> localhost / # perf list
>
> List of pre-defined events (to be used in -e):
> cpu-cycles OR cycles [Hardware event]
> instructions [Hardware event]
> cache-references [Hardware event]
> cache-misses [Hardware event]
> branch-instructions OR branches [Hardware event]
> branch-misses [Hardware event]
> bus-cycles [Hardware event]
> ...
>
> perf stat --cpu 0/1/2/3..... to minitor
> e.g. cpu0;
>
> localhost / # perf stat --cpu 0
>
> Performance counter stats for 'CPU(s) 0':
>
> 3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%]
> 20 context-switches # 0.006 K/sec [100.00%]
> 2 cpu-migrations # 0.001 K/sec [100.00%]
> 55 page-faults # 0.016 K/sec
> 7151843 cycles # 0.002 GHz [100.00%]
> <not supported> stalled-cycles-frontend
> <not supported> stalled-cycles-backend
> 4272536 instructions # 0.60 insns per cycle [100.00%]
> 568406 branches # 0.168 M/sec [100.00%]
> 65652 branch-misses # 11.55% of all branches
>
> Also, 'perf top' to monitor the PMU interrupts from cpus
>
> -Caesar
>
>
> Changes in v2:
> - AS Mark comments on https://patchwork.kernel.org/patch/9209369/
> remove the interrupt-affinity property, we need depend on Marc' perf
> code on https://patchwork.kernel.org/patch/9209369/.
>
> Caesar Wang (2):
> arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
> arm64: dts: rockchip: support the pmu node for rk3399
>
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 118 ++++++++++++++++++-------------
> 1 file changed, 69 insertions(+), 49 deletions(-)
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs
2016-07-06 11:24 ` [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Mark Rutland
@ 2016-07-14 1:14 ` Caesar Wang
0 siblings, 0 replies; 8+ messages in thread
From: Caesar Wang @ 2016-07-14 1:14 UTC (permalink / raw)
To: Mark Rutland, Heiko Stuebner
Cc: Caesar Wang, Will Deacon, Marc Zyngier, huangtao, devicetree,
Xing Zheng, Masahiro Yamada, Catalin Marinas, Brian Norris,
dianders, linux-kernel, linux-rockchip, Rob Herring, David Wu,
cf, Jianqun Xu, linux-arm-kernel
Hi,
On 2016年07月06日 19:24, Mark Rutland wrote:
> On Wed, Jul 06, 2016 at 04:05:55PM +0800, Caesar Wang wrote:
>> Hello Heiko, Marc & ARM guys
> Hi,
>
> These patches themselves look fine, so FWIW:
>
> Acked-by: Mark Rutland <mark.rutland@arm.com>
Thanks your ack.
>
> The prerequisite patch from Marc [1] also largely looks fine, but there
> are some minor details to sort out [2], so at this point in time I'm
> guesssing this is all v4.9 material.
>
> Thanks,
> Mark.
>
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/440647.html
> [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/441495.html
Okay, I saw the Marc's patch had been merged on next kernel.:-)
-Caesar
>
>> When Jay first submitted the rk3399.dtsi upstream
>> <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there,
>> but then took it out because the upstream binding wasn't done yet.
>> It looks as if the upstream stuff has landed, since in linux/master I see:
>> 287e9357abcc DT/arm,gic-v3: Documment PPI partition support
>> e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs
>> 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library
>> 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved
>> 651e8b54abde irqdomain: Allow domain matching on irq_fwspec
>>
>> This series patches add to support the rk3399 SoCs PMU.
>> I pick up the https://patchwork.kernel.org/patch/9209369/.
>>
>> As do some tests with ChromeOs for my rk3399 board.
>> Tested with linus master 4.7-rc6 kernel on rk3399 board.
>> https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream
>>
>> localhost / # perf list
>>
>> List of pre-defined events (to be used in -e):
>> cpu-cycles OR cycles [Hardware event]
>> instructions [Hardware event]
>> cache-references [Hardware event]
>> cache-misses [Hardware event]
>> branch-instructions OR branches [Hardware event]
>> branch-misses [Hardware event]
>> bus-cycles [Hardware event]
>> ...
>>
>> perf stat --cpu 0/1/2/3..... to minitor
>> e.g. cpu0;
>>
>> localhost / # perf stat --cpu 0
>>
>> Performance counter stats for 'CPU(s) 0':
>>
>> 3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%]
>> 20 context-switches # 0.006 K/sec [100.00%]
>> 2 cpu-migrations # 0.001 K/sec [100.00%]
>> 55 page-faults # 0.016 K/sec
>> 7151843 cycles # 0.002 GHz [100.00%]
>> <not supported> stalled-cycles-frontend
>> <not supported> stalled-cycles-backend
>> 4272536 instructions # 0.60 insns per cycle [100.00%]
>> 568406 branches # 0.168 M/sec [100.00%]
>> 65652 branch-misses # 11.55% of all branches
>>
>> Also, 'perf top' to monitor the PMU interrupts from cpus
>>
>> -Caesar
>>
>>
>> Changes in v2:
>> - AS Mark comments on https://patchwork.kernel.org/patch/9209369/
>> remove the interrupt-affinity property, we need depend on Marc' perf
>> code on https://patchwork.kernel.org/patch/9209369/.
>>
>> Caesar Wang (2):
>> arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
>> arm64: dts: rockchip: support the pmu node for rk3399
>>
>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 118 ++++++++++++++++++-------------
>> 1 file changed, 69 insertions(+), 49 deletions(-)
>>
>> --
>> 1.9.1
>>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs
2016-07-06 8:05 [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Caesar Wang
` (2 preceding siblings ...)
2016-07-06 11:24 ` [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Mark Rutland
@ 2016-09-03 0:13 ` Caesar Wang
2016-09-04 22:09 ` Heiko Stuebner
3 siblings, 1 reply; 8+ messages in thread
From: Caesar Wang @ 2016-09-03 0:13 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Caesar Wang, Marc Zyngier, mark.rutland, huangtao, Xing Zheng,
devicetree, Masahiro Yamada, Catalin Marinas, Brian Norris,
Will Deacon, dianders, linux-kernel, linux-rockchip, Rob Herring,
David Wu, cf, Jianqun Xu, linux-arm-kernel
Heiko,
What do you think of it?
Maybe I need re-update these patches on next kernel, and re-test them.
On 2016年07月06日 16:05, Caesar Wang wrote:
> Hello Heiko, Marc & ARM guys
>
> When Jay first submitted the rk3399.dtsi upstream
> <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there,
> but then took it out because the upstream binding wasn't done yet.
> It looks as if the upstream stuff has landed, since in linux/master I see:
> 287e9357abcc DT/arm,gic-v3: Documment PPI partition support
> e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs
> 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library
> 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved
> 651e8b54abde irqdomain: Allow domain matching on irq_fwspec
>
> This series patches add to support the rk3399 SoCs PMU.
> I pick up the https://patchwork.kernel.org/patch/9209369/.
>
> As do some tests with ChromeOs for my rk3399 board.
> Tested with linus master 4.7-rc6 kernel on rk3399 board.
> https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream
>
> localhost / # perf list
>
> List of pre-defined events (to be used in -e):
> cpu-cycles OR cycles [Hardware event]
> instructions [Hardware event]
> cache-references [Hardware event]
> cache-misses [Hardware event]
> branch-instructions OR branches [Hardware event]
> branch-misses [Hardware event]
> bus-cycles [Hardware event]
> ...
>
> perf stat --cpu 0/1/2/3..... to minitor
> e.g. cpu0;
>
> localhost / # perf stat --cpu 0
>
> Performance counter stats for 'CPU(s) 0':
>
> 3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%]
> 20 context-switches # 0.006 K/sec [100.00%]
> 2 cpu-migrations # 0.001 K/sec [100.00%]
> 55 page-faults # 0.016 K/sec
> 7151843 cycles # 0.002 GHz [100.00%]
> <not supported> stalled-cycles-frontend
> <not supported> stalled-cycles-backend
> 4272536 instructions # 0.60 insns per cycle [100.00%]
> 568406 branches # 0.168 M/sec [100.00%]
> 65652 branch-misses # 11.55% of all branches
>
> Also, 'perf top' to monitor the PMU interrupts from cpus
>
> -Caesar
>
>
> Changes in v2:
> - AS Mark comments on https://patchwork.kernel.org/patch/9209369/
> remove the interrupt-affinity property, we need depend on Marc' perf
> code on https://patchwork.kernel.org/patch/9209369/.
>
> Caesar Wang (2):
> arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
> arm64: dts: rockchip: support the pmu node for rk3399
>
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 118 ++++++++++++++++++-------------
> 1 file changed, 69 insertions(+), 49 deletions(-)
>
--
caesar wang | software engineer | wxt@rock-chip.com
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs
2016-09-03 0:13 ` Caesar Wang
@ 2016-09-04 22:09 ` Heiko Stuebner
2016-09-04 22:47 ` Caesar Wang
0 siblings, 1 reply; 8+ messages in thread
From: Heiko Stuebner @ 2016-09-04 22:09 UTC (permalink / raw)
To: Caesar Wang
Cc: Marc Zyngier, mark.rutland, huangtao, Xing Zheng, devicetree,
Masahiro Yamada, Catalin Marinas, Brian Norris, Will Deacon,
dianders, linux-kernel, linux-rockchip, Rob Herring, David Wu,
cf, Jianqun Xu, linux-arm-kernel
Hi Caesar,
Am Samstag, 3. September 2016, 08:13:17 CEST schrieb Caesar Wang:
> Heiko,
>
> What do you think of it?
> Maybe I need re-update these patches on next kernel, and re-test them.
I checked linux-next and the underlying changes seem to all have gone in now,
so we should be fine.
Updating the patches would be cool. I tried applying them to my dts64 branch
just now, but they don't apply cleanly anymore due to other changes going in
before.
When you check against linux-next, please take into account that there is no
new linux-next since 20160825 and 20160905 is the next planned linux-next
release (probably Stephen being on holiday).
Thanks
Heiko
>
> On 2016年07月06日 16:05, Caesar Wang wrote:
> > Hello Heiko, Marc & ARM guys
> >
> > When Jay first submitted the rk3399.dtsi upstream
> > <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in
> > there,
> > but then took it out because the upstream binding wasn't done yet.
> > It looks as if the upstream stuff has landed, since in linux/master I see:
> > 287e9357abcc DT/arm,gic-v3: Documment PPI partition support
> > e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs
> > 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library
> > 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be
> > set/retrieved 651e8b54abde irqdomain: Allow domain matching on irq_fwspec
> >
> > This series patches add to support the rk3399 SoCs PMU.
> > I pick up the https://patchwork.kernel.org/patch/9209369/.
> >
> > As do some tests with ChromeOs for my rk3399 board.
> > Tested with linus master 4.7-rc6 kernel on rk3399 board.
> > https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream
> >
> > localhost / # perf list
> >
> > List of pre-defined events (to be used in -e):
> > cpu-cycles OR cycles [Hardware event]
> > instructions [Hardware event]
> > cache-references [Hardware event]
> > cache-misses [Hardware event]
> > branch-instructions OR branches [Hardware event]
> > branch-misses [Hardware event]
> > bus-cycles [Hardware event]
> > ...
> >
> > perf stat --cpu 0/1/2/3..... to minitor
> > e.g. cpu0;
> >
> > localhost / # perf stat --cpu 0
> >
> > Performance counter stats for 'CPU(s) 0':
> >
> > 3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%]
> > 20 context-switches # 0.006 K/sec [100.00%]
> > 2 cpu-migrations # 0.001 K/sec [100.00%]
> > 55 page-faults # 0.016 K/sec
> > 7151843 cycles # 0.002 GHz [100.00%]
> > <not supported> stalled-cycles-frontend
> > <not supported> stalled-cycles-backend
> > 4272536 instructions # 0.60 insns per cycle [100.00%]
> > 568406 branches # 0.168 M/sec [100.00%]
> > 65652 branch-misses # 11.55% of all branches
> >
> > Also, 'perf top' to monitor the PMU interrupts from cpus
> >
> > -Caesar
> >
> >
> > Changes in v2:
> > - AS Mark comments on https://patchwork.kernel.org/patch/9209369/
> >
> > remove the interrupt-affinity property, we need depend on Marc' perf
> > code on https://patchwork.kernel.org/patch/9209369/.
> >
> > Caesar Wang (2):
> > arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
> > arm64: dts: rockchip: support the pmu node for rk3399
> >
> > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 118
> > ++++++++++++++++++------------- 1 file changed, 69 insertions(+), 49
> > deletions(-)
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs
2016-09-04 22:09 ` Heiko Stuebner
@ 2016-09-04 22:47 ` Caesar Wang
0 siblings, 0 replies; 8+ messages in thread
From: Caesar Wang @ 2016-09-04 22:47 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Caesar Wang, mark.rutland, huangtao, Xing Zheng, devicetree,
Marc Zyngier, Catalin Marinas, Brian Norris, Will Deacon,
dianders, linux-kernel, Masahiro Yamada, Rob Herring, David Wu,
cf, linux-rockchip, Jianqun Xu, linux-arm-kernel
On 2016年09月05日 06:09, Heiko Stuebner wrote:
> Hi Caesar,
>
> Am Samstag, 3. September 2016, 08:13:17 CEST schrieb Caesar Wang:
>> Heiko,
>>
>> What do you think of it?
>> Maybe I need re-update these patches on next kernel, and re-test them.
> I checked linux-next and the underlying changes seem to all have gone in now,
> so we should be fine.
>
> Updating the patches would be cool. I tried applying them to my dts64 branch
> just now, but they don't apply cleanly anymore due to other changes going in
> before.
>
> When you check against linux-next, please take into account that there is no
> new linux-next since 20160825 and 20160905 is the next planned linux-next
> release (probably Stephen being on holiday).
I will update/resend them base on your v4.9-armsoc/dts64 branch. (Wait a
moment to retest them)
Thanks.
>
>
> Thanks
> Heiko
>
>> On 2016年07月06日 16:05, Caesar Wang wrote:
>>> Hello Heiko, Marc & ARM guys
>>>
>>> When Jay first submitted the rk3399.dtsi upstream
>>> <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in
>>> there,
>>> but then took it out because the upstream binding wasn't done yet.
>>> It looks as if the upstream stuff has landed, since in linux/master I see:
>>> 287e9357abcc DT/arm,gic-v3: Documment PPI partition support
>>> e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs
>>> 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library
>>> 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be
>>> set/retrieved 651e8b54abde irqdomain: Allow domain matching on irq_fwspec
>>>
>>> This series patches add to support the rk3399 SoCs PMU.
>>> I pick up the https://patchwork.kernel.org/patch/9209369/.
>>>
>>> As do some tests with ChromeOs for my rk3399 board.
>>> Tested with linus master 4.7-rc6 kernel on rk3399 board.
>>> https://github.com/Caesar-github/rockchip/tree/rk3399/pmu-upstream
>>>
>>> localhost / # perf list
>>>
>>> List of pre-defined events (to be used in -e):
>>> cpu-cycles OR cycles [Hardware event]
>>> instructions [Hardware event]
>>> cache-references [Hardware event]
>>> cache-misses [Hardware event]
>>> branch-instructions OR branches [Hardware event]
>>> branch-misses [Hardware event]
>>> bus-cycles [Hardware event]
>>> ...
>>>
>>> perf stat --cpu 0/1/2/3..... to minitor
>>> e.g. cpu0;
>>>
>>> localhost / # perf stat --cpu 0
>>>
>>> Performance counter stats for 'CPU(s) 0':
>>>
>>> 3374.917571 task-clock (msec) # 1.001 CPUs utilized [100.00%]
>>> 20 context-switches # 0.006 K/sec [100.00%]
>>> 2 cpu-migrations # 0.001 K/sec [100.00%]
>>> 55 page-faults # 0.016 K/sec
>>> 7151843 cycles # 0.002 GHz [100.00%]
>>> <not supported> stalled-cycles-frontend
>>> <not supported> stalled-cycles-backend
>>> 4272536 instructions # 0.60 insns per cycle [100.00%]
>>> 568406 branches # 0.168 M/sec [100.00%]
>>> 65652 branch-misses # 11.55% of all branches
>>>
>>> Also, 'perf top' to monitor the PMU interrupts from cpus
>>>
>>> -Caesar
>>>
>>>
>>> Changes in v2:
>>> - AS Mark comments on https://patchwork.kernel.org/patch/9209369/
>>>
>>> remove the interrupt-affinity property, we need depend on Marc' perf
>>> code on https://patchwork.kernel.org/patch/9209369/.
>>>
>>> Caesar Wang (2):
>>> arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs
>>> arm64: dts: rockchip: support the pmu node for rk3399
>>>
>>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 118
>>> ++++++++++++++++++------------- 1 file changed, 69 insertions(+), 49
>>> deletions(-)
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
--
caesar wang | software engineer | wxt@rock-chip.com
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-09-04 22:54 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-07-06 8:05 [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Caesar Wang
2016-07-06 8:05 ` [PATCH v2 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on " Caesar Wang
2016-07-06 8:05 ` [PATCH v2 2/2] arm64: dts: rockchip: support the pmu node for rk3399 Caesar Wang
2016-07-06 11:24 ` [PATCH v2 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Mark Rutland
2016-07-14 1:14 ` Caesar Wang
2016-09-03 0:13 ` Caesar Wang
2016-09-04 22:09 ` Heiko Stuebner
2016-09-04 22:47 ` Caesar Wang
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