[PATCH RFCv1 0/1] Update struct spi_transfer to specify 8x bit transfers

[PATCH RFCv1 0/1] Update struct spi_transfer to specify 8x bit transfers

[Girish Mahadevan]

We’re working on a driver for a Quad SPI controller [using up to 4 data lines] which can use dual-data-sampling to implement 8-bit transfers. To allow a slave driver to specify the 8-bit transfer we'd like to make this change to the spi_transfer data structure. We are still working on the driver we will send an RFC for the driver patches separately once it is ready.

Girish Mahadevan (1):
  spi: Expand tx_nbits/rx_nbits to add 8-bit transfer

 include/linux/spi/spi.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

[PATCH RFCv1 1/1] spi: Expand tx_nbits/rx_nbits to add 8-bit transfer

[Girish Mahadevan]

Expand the tx_nbits/rx_nbits member of the spi_transfer struct to a 4 bit
value to allow specifying 8 bit transfers (SPI_NBITS_OCTO).

Change-Id: I0b7ab41b2caa8495da431944ccbc0b90942d5dd9
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
---
 include/linux/spi/spi.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 857a9a1..45b958a 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -717,10 +717,11 @@ extern void spi_res_release(struct spi_master *master,
  * by the results of previous messages and where the whole transaction
  * ends when the chipselect goes intactive.
  *
- * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
+ * When SPI can transfer in 1x,2x,4x or 8x. It can get this transfer information
  * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
  * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
- * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
+ * SPI_NBITS_DUAL(2x) SPI_NBITS_QUAD(4x) and SPI_NBITS_OCTO(8x) to support
+ * these four transfers.
  *
  * The code that submits an spi_message (and its spi_transfers)
  * to the lower layers is responsible for managing its memory.
@@ -744,11 +745,12 @@ struct spi_transfer {
 	struct sg_table rx_sg;
 
 	unsigned	cs_change:1;
-	unsigned	tx_nbits:3;
-	unsigned	rx_nbits:3;
+	unsigned	tx_nbits:4;
+	unsigned	rx_nbits:4;
 #define	SPI_NBITS_SINGLE	0x01 /* 1bit transfer */
 #define	SPI_NBITS_DUAL		0x02 /* 2bits transfer */
 #define	SPI_NBITS_QUAD		0x04 /* 4bits transfer */
+#define	SPI_NBITS_OCTO		0x08 /* 4bits transfer */
 	u8		bits_per_word;
 	u16		delay_usecs;
 	u32		speed_hz;
-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

Re: [PATCH RFCv1 0/1] Update struct spi_transfer to specify 8x bit transfers

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 926 bytes --]

On Wed, Jul 13, 2016 at 01:34:36PM -0600, Girish Mahadevan wrote:
> We’re working on a driver for a Quad SPI controller [using up to 4 data lines] which can use dual-data-sampling to implement 8-bit transfers. To allow a slave driver to specify the 8-bit transfer we'd like to make this change to the spi_transfer data structure. We are still working on the driver we will send an RFC for the driver patches separately once it is ready.

Please don't send cover letters for single patches, if there is anything
that needs saying put it in the changelog of the patch or after the ---
if it's administrative stuff.  This reduces mail volume and ensures that 
any important information is recorded in the changelog rather than being
lost. 

Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns.  Doing this makes your messages much
easier to read and reply to.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]

Re: [PATCH RFCv1 1/1] spi: Expand tx_nbits/rx_nbits to add 8-bit transfer

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 564 bytes --]

On Wed, Jul 13, 2016 at 01:34:37PM -0600, Girish Mahadevan wrote:
> Expand the tx_nbits/rx_nbits member of the spi_transfer struct to a 4 bit
> value to allow specifying 8 bit transfers (SPI_NBITS_OCTO).

Do you have any examples of hardware that might use this on both the
controller and device side?  Hardware like this tends to be memory
mapped rather than driven by a SPI controller in my experience.

> Change-Id: I0b7ab41b2caa8495da431944ccbc0b90942d5dd9

Don't include noise like this in upstream submissions, it means nothing
outside your gerritt install.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]