* [PATCH 01/10] Documentation: dt: socfpga: Add Arria10 NAND EDAC binding
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-16 23:05 ` Rob Herring
2016-07-14 16:06 ` [PATCH 02/10] Documentation: dt: socfpga: Add Arria10 DMA " tthayer
` (9 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera NAND
FIFO buffers EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 32 ++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index b545856..1bcbab2 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -90,6 +90,14 @@ Required Properties:
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
+NAND FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-nand-ecc"
+- reg : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent NAND node.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
+
Example:
eccmgr: eccmgr@ffd06000 {
@@ -132,4 +140,28 @@ Example:
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ nand-buf-ecc@ff8c2000 {
+ compatible = "altr,socfpga-nand-ecc";
+ reg = <0xff8c2000 0x400>;
+ altr,ecc-parent = <&nand>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
+ <43 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ nand-rd-ecc@ff8c2400 {
+ compatible = "altr,socfpga-nand-ecc";
+ reg = <0xff8c2400 0x400>;
+ altr,ecc-parent = <&nand>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
+ <45 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ nand-wr-ecc@ff8c2800 {
+ compatible = "altr,socfpga-nand-ecc";
+ reg = <0xff8c2800 0x400>;
+ altr,ecc-parent = <&nand>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <44 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 01/10] Documentation: dt: socfpga: Add Arria10 NAND EDAC binding
2016-07-14 16:06 ` [PATCH 01/10] Documentation: dt: socfpga: Add Arria10 NAND EDAC binding tthayer
@ 2016-07-16 23:05 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2016-07-16 23:05 UTC (permalink / raw)
To: tthayer
Cc: bp, dougthompson, m.chehab, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-kernel, tthayer.linux, linux-arm-kernel,
linux-edac
On Thu, Jul 14, 2016 at 11:06:39AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the device tree bindings needed to support the Altera NAND
> FIFO buffers EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> .../bindings/arm/altera/socfpga-eccmgr.txt | 32 ++++++++++++++++++++
> 1 file changed, 32 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 02/10] Documentation: dt: socfpga: Add Arria10 DMA EDAC binding
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
2016-07-14 16:06 ` [PATCH 01/10] Documentation: dt: socfpga: Add Arria10 NAND EDAC binding tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-16 23:06 ` Rob Herring
2016-07-14 16:06 ` [PATCH 03/10] Documentation: dt: socfpga: Add Arria10 USB " tthayer
` (8 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera DMA
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 1bcbab2..ad8245b 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -98,6 +98,14 @@ Required Properties:
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
+DMA FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-dma-ecc"
+- reg : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent DMA node.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
+
Example:
eccmgr: eccmgr@ffd06000 {
@@ -164,4 +172,12 @@ Example:
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ dma-ecc@ff8c8000 {
+ compatible = "altr,socfpga-dma-ecc";
+ reg = <0xff8c8000 0x400>;
+ altr,ecc-parent = <&pdma>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+ <42 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 02/10] Documentation: dt: socfpga: Add Arria10 DMA EDAC binding
2016-07-14 16:06 ` [PATCH 02/10] Documentation: dt: socfpga: Add Arria10 DMA " tthayer
@ 2016-07-16 23:06 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2016-07-16 23:06 UTC (permalink / raw)
To: tthayer
Cc: bp, dougthompson, m.chehab, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-kernel, tthayer.linux, linux-arm-kernel,
linux-edac
On Thu, Jul 14, 2016 at 11:06:40AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the device tree bindings needed to support the Altera DMA
> FIFO buffer EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> .../bindings/arm/altera/socfpga-eccmgr.txt | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 03/10] Documentation: dt: socfpga: Add Arria10 USB EDAC binding
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
2016-07-14 16:06 ` [PATCH 01/10] Documentation: dt: socfpga: Add Arria10 NAND EDAC binding tthayer
2016-07-14 16:06 ` [PATCH 02/10] Documentation: dt: socfpga: Add Arria10 DMA " tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-16 23:07 ` Rob Herring
2016-07-14 16:06 ` [PATCH 04/10] Documentation: dt: socfpga: Add Arria10 QSPI " tthayer
` (7 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera USB
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index ad8245b..3ffeb12 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -106,6 +106,14 @@ Required Properties:
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
+USB FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-usb-ecc"
+- reg : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent USB node.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
+
Example:
eccmgr: eccmgr@ffd06000 {
@@ -179,5 +187,12 @@ Example:
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<42 IRQ_TYPE_LEVEL_HIGH>;
+
+ usb0-ecc@ff8c8800 {
+ compatible = "altr,socfpga-usb-ecc";
+ reg = <0xff8c8800 0x400>;
+ altr,ecc-parent = <&usb0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
+ <34 IRQ_TYPE_LEVEL_HIGH>;
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 03/10] Documentation: dt: socfpga: Add Arria10 USB EDAC binding
2016-07-14 16:06 ` [PATCH 03/10] Documentation: dt: socfpga: Add Arria10 USB " tthayer
@ 2016-07-16 23:07 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2016-07-16 23:07 UTC (permalink / raw)
To: tthayer
Cc: bp, dougthompson, m.chehab, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-kernel, tthayer.linux, linux-arm-kernel,
linux-edac
On Thu, Jul 14, 2016 at 11:06:41AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the device tree bindings needed to support the Altera USB
> FIFO buffer EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> .../bindings/arm/altera/socfpga-eccmgr.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 04/10] Documentation: dt: socfpga: Add Arria10 QSPI EDAC binding
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
` (2 preceding siblings ...)
2016-07-14 16:06 ` [PATCH 03/10] Documentation: dt: socfpga: Add Arria10 USB " tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-16 23:07 ` Rob Herring
2016-07-14 16:06 ` [PATCH 05/10] EDAC, altera: Add Arria10 NAND EDAC support tthayer
` (6 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree bindings needed to support the Altera QSPI
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 3ffeb12..ee66df0 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -114,6 +114,14 @@ Required Properties:
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
+QSPI FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-qspi-ecc"
+- reg : Address and size for ECC block registers.
+- altr,ecc-parent : phandle to parent QSPI node.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt, in this order.
+
Example:
eccmgr: eccmgr@ffd06000 {
@@ -195,4 +203,12 @@ Example:
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<34 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ qspi-ecc@ff8c8400 {
+ compatible = "altr,socfpga-qspi-ecc";
+ reg = <0xff8c8400 0x400>;
+ altr,ecc-parent = <&qspi>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <46 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 04/10] Documentation: dt: socfpga: Add Arria10 QSPI EDAC binding
2016-07-14 16:06 ` [PATCH 04/10] Documentation: dt: socfpga: Add Arria10 QSPI " tthayer
@ 2016-07-16 23:07 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2016-07-16 23:07 UTC (permalink / raw)
To: tthayer
Cc: bp, dougthompson, m.chehab, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-kernel, tthayer.linux, linux-arm-kernel,
linux-edac
On Thu, Jul 14, 2016 at 11:06:42AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the device tree bindings needed to support the Altera QSPI
> FIFO buffer EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> .../bindings/arm/altera/socfpga-eccmgr.txt | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 05/10] EDAC, altera: Add Arria10 NAND EDAC support
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
` (3 preceding siblings ...)
2016-07-14 16:06 ` [PATCH 04/10] Documentation: dt: socfpga: Add Arria10 QSPI " tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-27 17:10 ` Borislav Petkov
2016-07-14 16:06 ` [PATCH 06/10] EDAC, altera: Add Arria10 DMA " tthayer
` (5 subsequent siblings)
10 siblings, 1 reply; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add Altera Arria10 NAND FIFO memory EDAC support.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
drivers/edac/Kconfig | 7 +++++++
drivers/edac/altera_edac.c | 34 +++++++++++++++++++++++++++++++++-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index d0c1dab..47378b3 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -398,6 +398,13 @@ config EDAC_ALTERA_ETHERNET
Support for error detection and correction on the
Altera Ethernet FIFO Memory for Altera SoCs.
+config EDAC_ALTERA_NAND
+ bool "Altera NAND FIFO ECC"
+ depends on EDAC_ALTERA=y && MTD_NAND_DENALI
+ help
+ Support for error detection and correction on the
+ Altera NAND FIFO Memory for Altera SoCs.
+
config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 2398d07..35d87d1 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1285,6 +1285,33 @@ early_initcall(socfpga_init_ethernet_ecc);
#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
+/********************** NAND Device Functions **********************/
+
+#ifdef CONFIG_EDAC_ALTERA_NAND
+
+static const struct edac_device_prv_data a10_nandecc_data = {
+ .setup = altr_check_ecc_deps,
+ .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
+ .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
+ .dbgfs_name = "altr_trigger",
+ .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
+ .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
+ .ce_set_mask = ALTR_A10_ECC_TSERRA,
+ .ue_set_mask = ALTR_A10_ECC_TDERRA,
+ .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
+ .ecc_irq_handler = altr_edac_a10_ecc_irq,
+ .inject_fops = &altr_edac_a10_device_inject_fops,
+};
+
+static int __init socfpga_init_nand_ecc(void)
+{
+ return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
+}
+
+early_initcall(socfpga_init_nand_ecc);
+
+#endif /* CONFIG_EDAC_ALTERA_NAND */
+
/********************* Arria10 EDAC Device Functions *************************/
static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_L2C
@@ -1298,6 +1325,9 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
{ .compatible = "altr,socfpga-eth-mac-ecc",
.data = &a10_enetecc_data },
#endif
+#ifdef CONFIG_EDAC_ALTERA_NAND
+ { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
+#endif
{},
};
MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
@@ -1589,7 +1619,9 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
else if ((of_device_is_compatible(child,
"altr,socfpga-a10-ocram-ecc")) ||
(of_device_is_compatible(child,
- "altr,socfpga-eth-mac-ecc")))
+ "altr,socfpga-eth-mac-ecc")) ||
+ (of_device_is_compatible(child,
+ "altr,socfpga-nand-ecc")))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child,
"altr,sdram-edac-a10"))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 05/10] EDAC, altera: Add Arria10 NAND EDAC support
2016-07-14 16:06 ` [PATCH 05/10] EDAC, altera: Add Arria10 NAND EDAC support tthayer
@ 2016-07-27 17:10 ` Borislav Petkov
2016-07-27 18:43 ` Thor Thayer
0 siblings, 1 reply; 21+ messages in thread
From: Borislav Petkov @ 2016-07-27 17:10 UTC (permalink / raw)
To: tthayer
Cc: dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-edac, linux-kernel, linux-arm-kernel,
tthayer.linux
On Thu, Jul 14, 2016 at 11:06:43AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add Altera Arria10 NAND FIFO memory EDAC support.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> drivers/edac/Kconfig | 7 +++++++
> drivers/edac/altera_edac.c | 34 +++++++++++++++++++++++++++++++++-
> 2 files changed, 40 insertions(+), 1 deletion(-)
...
> @@ -1589,7 +1619,9 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
> else if ((of_device_is_compatible(child,
> "altr,socfpga-a10-ocram-ecc")) ||
> (of_device_is_compatible(child,
> - "altr,socfpga-eth-mac-ecc")))
> + "altr,socfpga-eth-mac-ecc")) ||
> + (of_device_is_compatible(child,
> + "altr,socfpga-nand-ecc")))
> altr_edac_a10_device_add(edac, child);
> else if (of_device_is_compatible(child,
> "altr,sdram-edac-a10"))
Can we simplify this loop like this?
for_each_child_of_node(pdev->dev.of_node, child) {
if (!of_device_is_available(child))
continue;
if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
of_device_is_compatible(child, "altr,socfpga-nand-ecc"))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
of_platform_populate(pdev->dev.of_node,
altr_sdram_ctrl_of_match,
NULL, &pdev->dev);
}
I've merged the first "if" and subsequent "else if" because they all
do altr_edac_a10_device_add(edac, child) and added spacing for better
readability.
Look ok?
Or have I fatfingered it?
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 05/10] EDAC, altera: Add Arria10 NAND EDAC support
2016-07-27 17:10 ` Borislav Petkov
@ 2016-07-27 18:43 ` Thor Thayer
2016-07-27 20:17 ` Borislav Petkov
0 siblings, 1 reply; 21+ messages in thread
From: Thor Thayer @ 2016-07-27 18:43 UTC (permalink / raw)
To: Borislav Petkov
Cc: dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-edac, linux-kernel, linux-arm-kernel,
tthayer.linux
On 07/27/2016 12:10 PM, Borislav Petkov wrote:
> On Thu, Jul 14, 2016 at 11:06:43AM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add Altera Arria10 NAND FIFO memory EDAC support.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>> drivers/edac/Kconfig | 7 +++++++
>> drivers/edac/altera_edac.c | 34 +++++++++++++++++++++++++++++++++-
>> 2 files changed, 40 insertions(+), 1 deletion(-)
>
> ...
>
>> @@ -1589,7 +1619,9 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
>> else if ((of_device_is_compatible(child,
>> "altr,socfpga-a10-ocram-ecc")) ||
>> (of_device_is_compatible(child,
>> - "altr,socfpga-eth-mac-ecc")))
>> + "altr,socfpga-eth-mac-ecc")) ||
>> + (of_device_is_compatible(child,
>> + "altr,socfpga-nand-ecc")))
>> altr_edac_a10_device_add(edac, child);
>> else if (of_device_is_compatible(child,
>> "altr,sdram-edac-a10"))
>
> Can we simplify this loop like this?
>
> for_each_child_of_node(pdev->dev.of_node, child) {
> if (!of_device_is_available(child))
> continue;
>
> if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
> of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
> of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
> of_device_is_compatible(child, "altr,socfpga-nand-ecc"))
>
> altr_edac_a10_device_add(edac, child);
>
> else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
> of_platform_populate(pdev->dev.of_node,
> altr_sdram_ctrl_of_match,
> NULL, &pdev->dev);
> }
>
> I've merged the first "if" and subsequent "else if" because they all
> do altr_edac_a10_device_add(edac, child) and added spacing for better
> readability.
>
> Look ok?
>
> Or have I fatfingered it?
>
Yes, that's better. I was trying to stay within the 80 character limit
but missed the if/else if improvement. Thanks, Boris!
Should I re-submit?
Thanks,
Thor
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 05/10] EDAC, altera: Add Arria10 NAND EDAC support
2016-07-27 18:43 ` Thor Thayer
@ 2016-07-27 20:17 ` Borislav Petkov
0 siblings, 0 replies; 21+ messages in thread
From: Borislav Petkov @ 2016-07-27 20:17 UTC (permalink / raw)
To: Thor Thayer
Cc: dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-edac, linux-kernel, linux-arm-kernel,
tthayer.linux
On Wed, Jul 27, 2016 at 01:43:04PM -0500, Thor Thayer wrote:
> Yes, that's better. I was trying to stay within the 80 character limit but
> missed the if/else if improvement. Thanks, Boris!
>
> Should I re-submit?
Nah, no need.
I'd only ask you to test the final result once I've pushed it out after
the merge window is over.
Thanks.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 06/10] EDAC, altera: Add Arria10 DMA EDAC support
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
` (4 preceding siblings ...)
2016-07-14 16:06 ` [PATCH 05/10] EDAC, altera: Add Arria10 NAND EDAC support tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-14 16:06 ` [PATCH 07/10] EDAC, altera: Add Arria10 USB " tthayer
` (4 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add Altera Arria10 DMA FIFO memory EDAC support.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
drivers/edac/Kconfig | 7 +++++++
drivers/edac/altera_edac.c | 34 +++++++++++++++++++++++++++++++++-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 47378b3..d1fd57a 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -405,6 +405,13 @@ config EDAC_ALTERA_NAND
Support for error detection and correction on the
Altera NAND FIFO Memory for Altera SoCs.
+config EDAC_ALTERA_DMA
+ bool "Altera DMA FIFO ECC"
+ depends on EDAC_ALTERA=y && PL330_DMA=y
+ help
+ Support for error detection and correction on the
+ Altera DMA FIFO Memory for Altera SoCs.
+
config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 35d87d1..6e4afbc 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1312,6 +1312,33 @@ early_initcall(socfpga_init_nand_ecc);
#endif /* CONFIG_EDAC_ALTERA_NAND */
+/********************** DMA Device Functions **********************/
+
+#ifdef CONFIG_EDAC_ALTERA_DMA
+
+static const struct edac_device_prv_data a10_dmaecc_data = {
+ .setup = altr_check_ecc_deps,
+ .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
+ .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
+ .dbgfs_name = "altr_trigger",
+ .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
+ .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
+ .ce_set_mask = ALTR_A10_ECC_TSERRA,
+ .ue_set_mask = ALTR_A10_ECC_TDERRA,
+ .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
+ .ecc_irq_handler = altr_edac_a10_ecc_irq,
+ .inject_fops = &altr_edac_a10_device_inject_fops,
+};
+
+static int __init socfpga_init_dma_ecc(void)
+{
+ return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
+}
+
+early_initcall(socfpga_init_dma_ecc);
+
+#endif /* CONFIG_EDAC_ALTERA_DMA */
+
/********************* Arria10 EDAC Device Functions *************************/
static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_L2C
@@ -1328,6 +1355,9 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_NAND
{ .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
#endif
+#ifdef CONFIG_EDAC_ALTERA_DMA
+ { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
+#endif
{},
};
MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
@@ -1621,7 +1651,9 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
(of_device_is_compatible(child,
"altr,socfpga-eth-mac-ecc")) ||
(of_device_is_compatible(child,
- "altr,socfpga-nand-ecc")))
+ "altr,socfpga-nand-ecc")) ||
+ (of_device_is_compatible(child,
+ "altr,socfpga-dma-ecc")))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child,
"altr,sdram-edac-a10"))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 07/10] EDAC, altera: Add Arria10 USB EDAC support
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
` (5 preceding siblings ...)
2016-07-14 16:06 ` [PATCH 06/10] EDAC, altera: Add Arria10 DMA " tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-14 16:06 ` [PATCH 08/10] EDAC, altera: Add Arria10 QSPI " tthayer
` (3 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add Altera Arria10 USB FIFO memory EDAC support.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
drivers/edac/Kconfig | 7 +++++++
drivers/edac/altera_edac.c | 34 +++++++++++++++++++++++++++++++++-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index d1fd57a..1966068 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -412,6 +412,13 @@ config EDAC_ALTERA_DMA
Support for error detection and correction on the
Altera DMA FIFO Memory for Altera SoCs.
+config EDAC_ALTERA_USB
+ bool "Altera USB FIFO ECC"
+ depends on EDAC_ALTERA=y && USB_DWC2
+ help
+ Support for error detection and correction on the
+ Altera USB FIFO Memory for Altera SoCs.
+
config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 6e4afbc..439d6cb 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1339,6 +1339,33 @@ early_initcall(socfpga_init_dma_ecc);
#endif /* CONFIG_EDAC_ALTERA_DMA */
+/********************** USB Device Functions **********************/
+
+#ifdef CONFIG_EDAC_ALTERA_USB
+
+static const struct edac_device_prv_data a10_usbecc_data = {
+ .setup = altr_check_ecc_deps,
+ .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
+ .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
+ .dbgfs_name = "altr_trigger",
+ .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
+ .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
+ .ce_set_mask = ALTR_A10_ECC_TSERRA,
+ .ue_set_mask = ALTR_A10_ECC_TDERRA,
+ .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
+ .ecc_irq_handler = altr_edac_a10_ecc_irq,
+ .inject_fops = &altr_edac_a10_device_inject_fops,
+};
+
+static int __init socfpga_init_usb_ecc(void)
+{
+ return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
+}
+
+early_initcall(socfpga_init_usb_ecc);
+
+#endif /* CONFIG_EDAC_ALTERA_USB */
+
/********************* Arria10 EDAC Device Functions *************************/
static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_L2C
@@ -1358,6 +1385,9 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_DMA
{ .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
#endif
+#ifdef CONFIG_EDAC_ALTERA_USB
+ { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
+#endif
{},
};
MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
@@ -1653,7 +1683,9 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
(of_device_is_compatible(child,
"altr,socfpga-nand-ecc")) ||
(of_device_is_compatible(child,
- "altr,socfpga-dma-ecc")))
+ "altr,socfpga-dma-ecc")) ||
+ (of_device_is_compatible(child,
+ "altr,socfpga-usb-ecc")))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child,
"altr,sdram-edac-a10"))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 08/10] EDAC, altera: Add Arria10 QSPI EDAC support
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
` (6 preceding siblings ...)
2016-07-14 16:06 ` [PATCH 07/10] EDAC, altera: Add Arria10 USB " tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-14 16:06 ` [PATCH 09/10] ARM: dts: Add Arria10 DMA EDAC devicetree entry tthayer
` (2 subsequent siblings)
10 siblings, 0 replies; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add Altera Arria10 QSPI FIFO memory EDAC support.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
drivers/edac/Kconfig | 7 +++++++
drivers/edac/altera_edac.c | 34 +++++++++++++++++++++++++++++++++-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 1966068..72752f4 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -419,6 +419,13 @@ config EDAC_ALTERA_USB
Support for error detection and correction on the
Altera USB FIFO Memory for Altera SoCs.
+config EDAC_ALTERA_QSPI
+ bool "Altera QSPI FIFO ECC"
+ depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
+ help
+ Support for error detection and correction on the
+ Altera QSPI FIFO Memory for Altera SoCs.
+
config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 439d6cb..b2900df 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1366,6 +1366,33 @@ early_initcall(socfpga_init_usb_ecc);
#endif /* CONFIG_EDAC_ALTERA_USB */
+/********************** QSPI Device Functions **********************/
+
+#ifdef CONFIG_EDAC_ALTERA_QSPI
+
+static const struct edac_device_prv_data a10_qspiecc_data = {
+ .setup = altr_check_ecc_deps,
+ .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
+ .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
+ .dbgfs_name = "altr_trigger",
+ .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
+ .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
+ .ce_set_mask = ALTR_A10_ECC_TSERRA,
+ .ue_set_mask = ALTR_A10_ECC_TDERRA,
+ .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
+ .ecc_irq_handler = altr_edac_a10_ecc_irq,
+ .inject_fops = &altr_edac_a10_device_inject_fops,
+};
+
+static int __init socfpga_init_qspi_ecc(void)
+{
+ return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
+}
+
+early_initcall(socfpga_init_qspi_ecc);
+
+#endif /* CONFIG_EDAC_ALTERA_QSPI */
+
/********************* Arria10 EDAC Device Functions *************************/
static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_L2C
@@ -1388,6 +1415,9 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_USB
{ .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
#endif
+#ifdef CONFIG_EDAC_ALTERA_QSPI
+ { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
+#endif
{},
};
MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
@@ -1685,7 +1715,9 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
(of_device_is_compatible(child,
"altr,socfpga-dma-ecc")) ||
(of_device_is_compatible(child,
- "altr,socfpga-usb-ecc")))
+ "altr,socfpga-usb-ecc")) ||
+ (of_device_is_compatible(child,
+ "altr,socfpga-qspi-ecc")))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child,
"altr,sdram-edac-a10"))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 09/10] ARM: dts: Add Arria10 DMA EDAC devicetree entry
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
` (7 preceding siblings ...)
2016-07-14 16:06 ` [PATCH 08/10] EDAC, altera: Add Arria10 QSPI " tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-20 16:05 ` Dinh Nguyen
2016-07-14 16:06 ` [PATCH 10/10] ARM: dts: Add Arria10 USB " tthayer
2016-07-28 11:47 ` [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC Borislav Petkov
10 siblings, 1 reply; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree entries needed to support the Altera DMA
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 228f663..a506ec0 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -644,6 +644,14 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ dma-ecc@ff8c8000 {
+ compatible = "altr,socfpga-dma-ecc";
+ reg = <0xff8c8000 0x400>;
+ altr,ecc-parent = <&pdma>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+ <42 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
rst: rstmgr@ffd05000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 09/10] ARM: dts: Add Arria10 DMA EDAC devicetree entry
2016-07-14 16:06 ` [PATCH 09/10] ARM: dts: Add Arria10 DMA EDAC devicetree entry tthayer
@ 2016-07-20 16:05 ` Dinh Nguyen
0 siblings, 0 replies; 21+ messages in thread
From: Dinh Nguyen @ 2016-07-20 16:05 UTC (permalink / raw)
To: tthayer, bp, dougthompson, m.chehab, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, linux, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux
On 07/14/2016 11:06 AM, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the device tree entries needed to support the Altera DMA
> FIFO buffer EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> arch/arm/boot/dts/socfpga_arria10.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index 228f663..a506ec0 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -644,6 +644,14 @@
> interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
> <37 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + dma-ecc@ff8c8000 {
> + compatible = "altr,socfpga-dma-ecc";
> + reg = <0xff8c8000 0x400>;
> + altr,ecc-parent = <&pdma>;
> + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
> + <42 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> rst: rstmgr@ffd05000 {
>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 10/10] ARM: dts: Add Arria10 USB EDAC devicetree entry
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
` (8 preceding siblings ...)
2016-07-14 16:06 ` [PATCH 09/10] ARM: dts: Add Arria10 DMA EDAC devicetree entry tthayer
@ 2016-07-14 16:06 ` tthayer
2016-07-20 16:05 ` Dinh Nguyen
2016-07-28 11:47 ` [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC Borislav Petkov
10 siblings, 1 reply; 21+ messages in thread
From: tthayer @ 2016-07-14 16:06 UTC (permalink / raw)
To: bp, dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux, tthayer
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree entries needed to support the Altera USB
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a506ec0..bd548ab 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -652,6 +652,14 @@
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<42 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ usb0-ecc@ff8c8800 {
+ compatible = "altr,socfpga-usb-ecc";
+ reg = <0xff8c8800 0x400>;
+ altr,ecc-parent = <&usb0>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
+ <34 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
rst: rstmgr@ffd05000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 10/10] ARM: dts: Add Arria10 USB EDAC devicetree entry
2016-07-14 16:06 ` [PATCH 10/10] ARM: dts: Add Arria10 USB " tthayer
@ 2016-07-20 16:05 ` Dinh Nguyen
0 siblings, 0 replies; 21+ messages in thread
From: Dinh Nguyen @ 2016-07-20 16:05 UTC (permalink / raw)
To: tthayer, bp, dougthompson, m.chehab, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, linux, grant.likely
Cc: devicetree, linux-doc, linux-edac, linux-kernel,
linux-arm-kernel, tthayer.linux
On 07/14/2016 11:06 AM, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the device tree entries needed to support the Altera USB
> FIFO buffer EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> arch/arm/boot/dts/socfpga_arria10.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index a506ec0..bd548ab 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -652,6 +652,14 @@
> interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
> <42 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + usb0-ecc@ff8c8800 {
> + compatible = "altr,socfpga-usb-ecc";
> + reg = <0xff8c8800 0x400>;
> + altr,ecc-parent = <&usb0>;
> + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
> + <34 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> rst: rstmgr@ffd05000 {
>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC
2016-07-14 16:06 [PATCH 00/10] Add NAND, DMA, USB, and QSPI EDAC tthayer
` (9 preceding siblings ...)
2016-07-14 16:06 ` [PATCH 10/10] ARM: dts: Add Arria10 USB " tthayer
@ 2016-07-28 11:47 ` Borislav Petkov
10 siblings, 0 replies; 21+ messages in thread
From: Borislav Petkov @ 2016-07-28 11:47 UTC (permalink / raw)
To: tthayer
Cc: dougthompson, m.chehab, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, linux, dinguyen, grant.likely, devicetree,
linux-doc, linux-edac, linux-kernel, linux-arm-kernel,
tthayer.linux
On Thu, Jul 14, 2016 at 11:06:38AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> This patch series adds the NAND, DMA, USB and QSPI FIFO EDAC modules.
>
> Thor Thayer (10):
> Documentation: dt: socfpga: Add Arria10 NAND EDAC binding
> Documentation: dt: socfpga: Add Arria10 DMA EDAC binding
> Documentation: dt: socfpga: Add Arria10 USB EDAC binding
> Documentation: dt: socfpga: Add Arria10 QSPI EDAC binding
> EDAC, altera: Add Arria10 NAND EDAC support
> EDAC, altera: Add Arria10 DMA EDAC support
> EDAC, altera: Add Arria10 USB EDAC support
> EDAC, altera: Add Arria10 QSPI EDAC support
> ARM: dts: Add Arria10 DMA EDAC devicetree entry
> ARM: dts: Add Arria10 USB EDAC devicetree entry
>
> .../bindings/arm/altera/socfpga-eccmgr.txt | 79 ++++++++++++
> arch/arm/boot/dts/socfpga_arria10.dtsi | 16 +++
> drivers/edac/Kconfig | 28 +++++
> drivers/edac/altera_edac.c | 130 +++++++++++++++++++-
> 4 files changed, 252 insertions(+), 1 deletion(-)
All applied, thanks!
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
^ permalink raw reply [flat|nested] 21+ messages in thread