[PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier

[Matt Redfearn <matt.redfearn@imgtec.com>]

Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but
architecturally defined ordering barrier. If a CPU does not implement it,
the arch specifies that it must fall back to SYNC(0).

Define the barrier type and always use it in the pm-cps code rather than
falling back to the heavyweight sync(0) such that we can benefit from
the lighter weight sync.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/include/asm/barrier.h | 10 ++++++++++
 arch/mips/kernel/pm-cps.c       |  3 +--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index d296633d890e..90c7a97db7e1 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -10,6 +10,16 @@
 
 #include <asm/addrspace.h>
 
+/*
+ * Lightweight sync types defined by the MIPS architecture
+ * These values are used with the sync instruction to perform memory barriers
+ * other than the standard heavyweight sync(0) completion barrier.
+ */
+
+/* Lightweight ordering barrier */
+#define STYPE_SYNC_MB 0x10
+
+
 #ifdef CONFIG_CPU_HAS_SYNC
 #define __sync()				\
 	__asm__ __volatile__(			\
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index f8c8edd0a451..572dc1d016a0 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -76,7 +76,7 @@ static struct uasm_reloc relocs[32] __initdata;
 /* CPU dependant sync types */
 static unsigned stype_intervention;
 static unsigned stype_memory;
-static unsigned stype_ordering;
+static unsigned stype_ordering = STYPE_SYNC_MB;
 
 enum mips_reg {
 	zero, at, v0, v1, a0, a1, a2, a3,
@@ -677,7 +677,6 @@ static int __init cps_pm_init(void)
 	case CPU_P6600:
 		stype_intervention = 0x2;
 		stype_memory = 0x3;
-		stype_ordering = 0x10;
 		break;
 
 	default:
-- 
2.7.4