From: Matt Redfearn <matt.redfearn@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>,
Matt Redfearn <matt.redfearn@imgtec.com>,
Adam Buchbinder <adam.buchbinder@gmail.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Kees Cook <keescook@chromium.org>, <linux-kernel@vger.kernel.org>,
Markos Chandras <markos.chandras@imgtec.com>,
Paul Burton <paul.burton@imgtec.com>
Subject: [PATCH 05/10] MIPS: pm-cps: Add P6600 implementation lightweight sync types
Date: Wed, 31 Aug 2016 11:44:34 +0100 [thread overview]
Message-ID: <1472640279-26593-6-git-send-email-matt.redfearn@imgtec.com> (raw)
In-Reply-To: <1472640279-26593-1-git-send-email-matt.redfearn@imgtec.com>
P6600 implements the same lightweight sync types as previous CPUs.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
---
arch/mips/kernel/pm-cps.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index c6b9ad2256f0..f8c8edd0a451 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -674,6 +674,7 @@ static int __init cps_pm_init(void)
case CPU_PROAPTIV:
case CPU_M5150:
case CPU_P5600:
+ case CPU_P6600:
stype_intervention = 0x2;
stype_memory = 0x3;
stype_ordering = 0x10;
--
2.7.4
next prev parent reply other threads:[~2016-08-31 10:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-31 10:44 [PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn
2016-08-31 10:44 ` [PATCH 01/10] MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' Matt Redfearn
2016-08-31 10:44 ` [PATCH 02/10] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn
2016-08-31 10:44 ` [PATCH 03/10] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn
2016-08-31 10:44 ` [PATCH 04/10] MIPS: pm-cps: Remove I6400 sync types Matt Redfearn
2016-08-31 10:44 ` Matt Redfearn [this message]
2016-08-31 10:44 ` [PATCH 06/10] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn
2016-08-31 11:48 ` Peter Zijlstra
2016-08-31 13:36 ` Matt Redfearn
2016-08-31 14:28 ` Peter Zijlstra
2016-08-31 15:49 ` Matt Redfearn
2016-08-31 10:44 ` [PATCH 07/10] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn
2016-08-31 10:44 ` [PATCH 08/10] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn
2016-08-31 10:44 ` [PATCH 09/10] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn
2016-08-31 10:44 ` [PATCH 10/10] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs Matt Redfearn
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